MM54C173/MM74C173 TRI-STATEÉ Quad D Flip-Flop General Description Features The MM54C173/MM74C173 TRI-STATE quad D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. The four D-type flip-flops operate synchronously from a common clock. The TRI-STATE output allows the device to be used in bus-organized systems. The outputs are placed in the TRI-STATE mode when either of the two output disable pins are in the logic ‘‘1’’ level. The input disable allows the flip-flops to remain in their present states without disrupting the clock. If either of the two input disables are taken to a logic ‘‘1’’ level, the Q outputs are fed back to the inputs and in this manner the flip-flops do not change state. Clearing is enabled by taking the input to a logic ‘’1’’ level. Clocking occurs on the positive-going transition. Y Y Y Y Y Y Y Supply voltage range 3V to 15V Tenth power TTL compatible Drive 2 LPTTL loads High noise immunity 0.45 VCC (typ.) Low power Medium speed operation High impedance TRI-STATE Input disable without gating the clock Applications Y Y Y Y Automotive Data terminals Instrumentation Medical electronics Y Y Y Y Alarm systems Industrial electronics Remote metering Computers Connection Diagram Dual-In-Line Package TL/F/5898 – 2 Top View Order Number MM54C173 or MM74C173 Truth Table (Both Output Disables Low) tn tn a 1 Data Input Disable Data Input Output Logic ‘‘1’’ on One or Both Inputs Logic ‘‘0’’ on Both Inputs Logic ‘‘0’’ on Both Inputs X 1 0 Qn 1 0 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/5898 RRD-B30M105/Printed in U. S. A. MM54C173/MM74C173 TRI-STATE Quad D Flip-Flop February 1988 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin b 0.3V to VCC a 0.3V Operating Temperature Range MM54C173 MM74C173 b 55§ C to a 125§ C b 40§ C to a 85§ C Storage Temperature Range b 65§ C to a 150§ C Maximum VCC Voltage 18V Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range 700 mW 500 mW 3V to 15V 260§ C Lead Temperature (Soldering, 10 seconds) DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage VCC e 5V VCC e 10V VIN(0) Logical ‘‘0’’ Input Voltage VCC e 5V VCC e 10V VOUT(1) Logical ‘‘1’’ Output Voltage VCC e 5V VCC e 10V VOUT(0) Logical ‘‘0’’ Output Voltage VCC e 5V VCC e 10V IIN(1) Logical ‘‘1’’ Input Current VCC e 15V IIN(0) Logical ‘‘0’’ Input Current IOZ ICC 3.5 8.0 V V 1.5 2.0 4.5 9.0 V V 0.005 Output Current in High Impedance State VCC e 15V, VO e 15V VCC e 15V, VO e 0V Supply Current VCC e 15V V V 0.5 1.0 V V 1.0 mA b 1.0 0.005 0.001 0.001 1.0 b 1.0 mA mA 0.05 300 mA mA LOW POWER TTL/CMOS INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.5V VIN(0) Logical ‘‘0’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VOUT(1) Logical ‘‘1’’ Output Voltage 54C, VCC e 4.5V, IO e b360 mA 74C, VCC e 4.75V, IO e b360 mA VOUT(1) Logical ‘‘0’’ Output Voltage 54C, VCC e 4.5V, IO e 360 mA 74C, VCC e 4.75V, IO e 360 mA tpd0, tpd1 Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from Clock VCCb1.5 VCCb1.5 V V 0.8 0.8 2.4 2.4 V V 0.4 0.4 VCC e 5V, CL e 50 pF, TA e 25§ C V V 500 V V ns OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current VCC e 5V, VIN(0) e 0V TA e 25§ C, VOUT e 0V b 1.75 mA ISOURCE Output Source Current VCC e 10V, VIN(0) e 0V TA e 25§ C, VOUT e 0V b 8.0 mA ISINK Output Sink Current VCC e 5V, VIN(1) e 5V TA e 25§ C, VOUT e VCC 1.75 mA ISINK Output Sink Current VCC e 10V, VIN(1) e 10V TA e 25§ C, VOUT e VCC 8.0 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. 2 AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, unless otherwise noted Typ Max Units tpd0, tpd1 Symbol Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from Clock to Output Parameter VCC e 5V VCC e 10V Conditions Min 220 80 400 200 ns ns tS Input Data Set-up Time VCC e 5V VCC e 10V 40 15 80 30 ns ns tH Input Data Hold Time VCC e 5V VCC e 10V 0 0 0 0 ns ns tS Input Disable Set-up Time, tS DISS VCC e 5V VCC e 10V 100 35 200 70 ns ns tH Input Disable Hold Time, tH DISS VCC e 5V VCC e 10V 0 0 0 0 ns ns t1H, t0H Delay from Output Disable to High Impedance State (from Logical ‘‘1’’ or Logical ‘‘0’’ Level) VCC e 5V, RL e 10k VCC e 10V, RL e 10k 170 70 340 140 ns ns tH1 Delay from Output Disable to Logical ‘‘1’’ Level (from High Impedance State) VCC e 5V VCC e 10V 170 70 340 140 ns ns tH0 Delay from Output Disable to Logical ‘‘0’’ Level (from High Impedance State) VCC e 5V VCC e 10V 170 70 340 140 ns ns tpd0, tpd1 Propagation Delay from Clear to Output VCC e 5V VCC e 10V 240 90 490 180 ns ns fMAX Maximum Clock Frequency VCC e 5V VCC e 10V tW Minimum Clear Pulse Width VCC e 5V VCC e 10V tr, tf Maximum Clock Rise and Fall Time VCC e 5V VCC e 10V CIN Input Capacitance (Note 2) CPD Power Dissipation Capacitance (Note 3) 3 7.0 4 12 MHz MHz 150 70 ns ns 10 5 ms ms 5 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guarantee.d Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note AN-90. Switching Time Waveforms TL/F/5898 – 3 3 Logic Diagram TL/F/5898 – 1 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C173J or MM74C173J NS Package Number J16A 5 MM54C173/MM74C173 TRI-STATE Quad D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C173N or MM74C173N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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