NEC UPA1706TP

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1706TP
SWITCHING
N-CHANNEL POWER MOS FET
PACKAGE DRAWING (Unit: mm)
DESCRIPTION
The µPA1706TP which has a heat spreader is N-Channel
MOS Field Effect Transistor designed for DC/DC converter
and power management application of notebook computer.
8
5
1, 2, 3
; Source
4
; Gate
5, 6, 7, 8, 9 ; Drain
1
0.8 ±0.2
0.05 ±0.05
0.10 S
1.27 TYP.
0.40
+0.10
–0.05
4
2.0 ±0.2
2.9 MAX.
PACKAGE
Power HSOP8
0.12 M
1.1 ±0.2
ORDERING INFORMATION
µPA1706TP
4.4 ±0.15
0.15
S
1
PART NUMBER
6.0 ±0.3
4
5.2 +0.17
–0.2
+0.10
–0.05
1.49 ±0.21
1.44 TYP.
FEATURES
• Low on-state resistance
RDS(on)1 = 7.8 mΩ MAX. (VGS = 10 V, ID = 7.0 A)
RDS(on)2 = 10.0 mΩ MAX. (VGS = 4.5 V, ID = 7.0 A)
• Low Ciss: Ciss = 3000 pF TYP. (VDS = 10 V, VGS = 0 V)
• Small and surface mount package (Power HSOP8)
9
4.1 MAX.
8
5
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS
30
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
V
Drain Current (DC) (TC = 25°C)
ID(DC)1
±28
A
Drain Current (DC)
Note1
Drain Current (pulse)
Note2
Total Power Dissipation (TC = 25°C)
Total Power Dissipation
Note1
ID(DC)2
±17
A
ID(pulse)
±100
A
PT1
39
W
PT2
3
W
Channel Temperature
Tch
150
°C
Storage Temperature
Tstg
–55 to + 150
°C
IAS
19
A
EAS
36.1
mJ
Single Avalanche Current
Note3
Single Avalanche Energy
Note3
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Notes 1. Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec
2. PW ≤ 10 µs, Duty cycle ≤ 1%
3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, L = 100 µH, VGS = 20 → 0 V
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G15850EJ1V0DS00 (1st edition)
Date Published May 2002 NS CP(K)
Printed in Japan
©
2001
µPA1706TP
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = 30 V, VGS = 0 V
10
µA
Gate Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
±10
µA
VGS(off)
VDS = 10 V, ID = 1 mA
1.5
2.0
2.5
V
| yfs |
VDS = 10 V, ID = 7.0 A
10
22
RDS(on)1
VGS = 10 V, ID = 7.0 A
5.8
7.8
mΩ
RDS(on)2
VGS = 4.5 V, ID = 7.0 A
7.0
10.0
mΩ
RDS(on)3
VGS = 4.0 V, ID = 7.0 A
8.0
12.0
mΩ
Gate Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
S
Input Capacitance
Ciss
VDS = 10 V
3000
pF
Output Capacitance
Coss
VGS = 0 V
950
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
380
pF
Turn-on Delay Time
td(on)
VDD = 15 V, ID = 13 A
20
ns
tr
VGS = 10 V
20
ns
td(off)
RG = 10 Ω
80
ns
30
ns
Rise Time
Turn-off Delay Time
Fall Time
tf
Total Gate Charge
QG
VDD = 24 V
56
nC
Gate to Source Charge
QGS
VGS = 10 V
9
nC
Gate to Drain Charge
QGD
ID = 13 A
14
nC
VF(S-D)
IF = 13 A, VGS = 0 V
0.8
V
Reverse Recovery Time
trr
IF = 13 A, VGS = 0 V
43
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/µs
50
nC
Body Diode Forward Voltage
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 → 0 V
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
50 Ω
VGS
RL
Wave Form
RG
PG.
VDD
VGS
0
VGS
10%
90%
VDD
VDS
90%
BVDSS
IAS
VDS
VDS
ID
Starting Tch
τ
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
PG.
2
50 Ω
10%
0
10%
Wave Form
VDD
D.U.T.
IG = 2 mA
90%
VDS
VGS
0
RL
VDD
Data Sheet G15850EJ1V0DS
td(on)
tr
ton
td(off)
tf
toff
µPA1706TP
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
50
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
120
100
80
60
40
20
0
20
40
60
80
40
30
20
10
0
100 120 140 160
20
TC - Case Temperature - ˚C
40
60
80
100 120 140 160
TC - Case Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
1000
PW
ID(DC)
d
ite )
im 0 V
)L 1
on S =
(
S
RD t VG
(a
10
=
1
m
s
10
m
P
Li ow
m e
ite r D
d is
s
sip
at
io
n
1
TC = 25˚C
Single Pulse
0.1
0.01
0.1
1
10
100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
100
rth(t) - Transient Thermal Resistance - ˚C/W
ID - Drain Current - A
ID(pulse)
100
10
Rth(ch-C) = 3.21˚C/W
1
0.1
Single Pulse
0.01
100 µ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet G15850EJ1V0DS
3
µPA1706TP
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
100
Pulsed
Pulsed
4.5 V
VGS = 10 V
50
ID - Drain Current - A
ID - Drain Current - A
4.0 V
TA = 125˚C
75˚C
25˚C
−25˚C
10
1
40
30
20
0.1
0.01
10
VDS = 10 V
1
0
3
2
4
0
100
TA = −25˚C
25˚C
75˚C
125˚C
10
1
10
1
0.1
100
RDS(on) - Drain to Source On-state Resistance - mΩ
ID- Drain Current - A
4
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
50
Pulsed
15
10
VGS = 4.0 V
4.5 V
5
0
0.1
10 V
1
10
100
Pulsed
40
30
20
10
0
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
20
0.8
0.6
ID = 7.0 A
2
4
6
8
10
12 14 16 18 20
VGS - Gate to Source Voltage - V
1000
VGS(off) - Gate to Source Cut-off Voltage - V
|yfs| - Forward Transfer Admittance - S
VDS =10 V
Pulsed
RDS(on) - Drain to Source On-state Resistance - mΩ
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
1000
0.4
0.2
VDS - Drain to Source Voltage - V
VGS - Gate to Source Voltage - V
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
2.6
VDS = 10 V
ID = 1 mA
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0
−40 −20
0
20 40 60 80 100 120 140 160
Tch - Channel Temperature - ˚C
ID - Drain Current - A
Data Sheet G15850EJ1V0DS
RDS(on) - Drain to Source On-state Resistance - mΩ
µPA1706TP
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
18
14
VGS = 4.0 V
4.5 V
12
10 V
10
8
6
4
2
0
-40 -20
IF - Diode Forward Current - A
16
1000
ID = 7.0 A
0
Pulsed
100
0V
VGS =10 V
10
1
0.1
0
20 40 60 80 100 120 140 160
0.2
0.4
0.6
1.0
0.8
1.2
1.4
VSD - Source to Drain Voltage - V
Tch - Channel Temperature - ˚C
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
VGS = 0 V
f = 1 MHz
td(on), tr, td(off), tf - Switching Time - ns
1000
Ciss
1000
Coss
Crss
100
1
10
td(off)
100
tf
tr
td(on)
10
VDD = 15 V
VGS = 10 V
RG = 10 Ω
1
0.1
100
1
VDS - Drain to Source Voltage - V
di/dt = 100 A/µ s
VGS = 0 V
100
10
1
0.1
1
10
ID - Drain Current - A
VDS - Drain to Source Voltage - V
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
1000
10
100
ID - Drain Current - A
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
40
ID = 13 A
30
VDD = 24 V
15 V
6V
12
10
VGS
20
8
6
4
10
2
VDS
100
0
20
40
60
80
VGS - Gate to Source Voltage - V
10
0.1
trr - Reverse Recovery Diode - ns
Ciss, Coss, Crss - Capacitance - pF
10000
0
100
QG - Gate Charge - nC
Data Sheet G15850EJ1V0DS
5
µPA1706TP
[MEMO]
6
Data Sheet G15850EJ1V0DS
µPA1706TP
[MEMO]
Data Sheet G15850EJ1V0DS
7
µPA1706TP
• The information in this document is current as of May, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
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patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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M8E 00. 4