NEC UPA1774G

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1774
SWITCHING
DUAL P-CHANNEL POWER MOS FET
PACKAGE DRAWING (Unit: mm)
DESCRIPTION
The µ PA1774 is Dual P-channel MOS Field Effect
Transistor.
8
5
1 : Source 1
2 : Gate 1
7, 8 : Drain 1
FEATURES
• Dual chip type
• Low on-state resistance
RDS(on)1 = 250 mΩ MAX. (VGS = –10 V, ID = –2.0 A)
RDS(on)2 = 300 mΩ MAX. (VGS = –4.5 V, ID = –2.0 A)
RDS(on)3 = 330 mΩ MAX. (VGS = –4.0 V, ID = –2.0 A)
• Low input capacitance
Ciss = 420 pF TYP.
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
3 : Source 2
4 : Gate 2
5, 6 : Drain 2
ORDERING INFORMATION
PART NUMBER
PACKAGE
µ PA1774G
Power SOP8
6.0 ±0.3
4
4.4
5.37 MAX.
0.8
0.15
+0.10
–0.05
1.44
0.05 MIN.
1.8 MAX.
1
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS
–60
V
Gate to Source Voltage (VDS = 0 V)
VGSS
m20
V
Drain Current (DC) (TC = 25°C)
ID(DC)
m2.8
A
Note1
ID(pulse)
m18
A
Total Power Dissipation (1 unit)
Note2
PT
0.6
W
Total Power Dissipation (2 unit)
Note2
PT
0.8
W
Tch
150
°C
°C
Drain Current (pulse)
Channel Temperature
Storage Temperature
Tstg
–55 to 150
Single Avalanche Current
Note3
IAS
–2.8
A
Single Avalanche Energy
Note3
EAS
0.78
mJ
EQUIVALENT CIRCUIT
(1/2 circuit)
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2
2
2. Mounted on Glass Epoxy Board of 1600 mm x 1.6 mm. Drain pad size: 264 mm x 35 µm, TA = 25°C
3. Starting Tch = 25°C, VDD = –30 V, RG = 25 Ω, VGS = –20→0 V
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G15380EJ2V0DS00 (2nd edition)
Date Published June 2002 NS CP(K)
Printed in Japan
©
2001
µPA1774
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = −60 V, VGS = 0 V
−10
µA
Gate Leakage Current
IGSS
VGS = m16 V, VDS = 0 V
m10
µA
VGS(off)
VDS = −10 V, ID = 1 mA
−1.5
−2.0
−2.5
V
| yfs |
VDS = −10 V, ID = −2.0 A
2.5
4.3
RDS(on)1
VGS = −10 V, ID = −2.0 A
200
250
mΩ
RDS(on)2
VGS = −4.5 V, ID = −2.0 A
230
300
mΩ
RDS(on)3
VGS = −4.0 V, ID = −2.0 A
240
330
mΩ
Gate Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
S
Input Capacitance
Ciss
VDS = −10 V
420
pF
Output Capacitance
Coss
VGS = 0 V
80
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
30
pF
Turn-on Delay Time
td(on)
VDD = −30 V, ID = −2.0 A
8
ns
VGS = −10 V
5
ns
RG = 0 Ω
35
ns
8
ns
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
VDD = −48 V
10
nC
Gate to Source Charge
QGS
VGS = −10 V
1.7
nC
Gate to Drain Charge
QGD
ID = −2.8 A
2.2
nC
VF(S-D)
IF = 2.8 A, VGS = 0 V
0.89
V
Reverse Recovery Time
trr
IF = 2.8 A, VGS = 0 V
45
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/µs
65
µC
Body Diode Forward Voltage
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
D.U.T.
L
RL
PG
50 Ω
VDD
VGS = –20 → 0 V
RG
PG.
VGS (−)
VGS
Wave Form
0
VGS
10%
90%
VDD
VDS (−)
−
IAS
90%
BVDSS
VDS
ID
VDS
Wave Form
τ
VDD
Starting Tch
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
2
IG = −2 mA
RL
50 Ω
VDD
90%
VDS
VGS (−)
0
Data Sheet G15380EJ2V0DS
10% 10%
0
td(on)
tr
ton
td(off)
tf
toff
µPA1774
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
1 .0
100
80
60
40
20
0
0 .8
2 u n it
0 .6
1 u n it
0 .4
0 .2
0 .0
0
20
40
60
80
100 120
140 160
0
20
TA - Ambient Temperature - °C
60
80
100
120
140
160
FORWARD BIAS SAFE OPERATING AREA
−100
−10
40
TA - Ambient Temperature - °C
T A = 2 5 °C
S ig le P u ls e
I D (p u ls e ) = − 1 8 A
I D (D C ) = − 2 .8 A
−1
−0.1
−0.01
R D S (on ) L im ite d
(V G S = − 1 0 V )
P W = 10 m s
100 m s
P o w e r D iss ip a tio n
L im ite d
−0.001
−0.1
−1
−10
−100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1 0 0 0
rth(t) - Transient Thermal Resistance - °C/W
ID - Drain Current - A
PW = 1 ms
Rth(ch-A) = 208.3°C/W
1 0 0
1 0
1
0 .1
0 .0 1
Mounted on Glass Epoxy Board of 1600 mm2×1.6 mm
Drain Pad size:264 mm2×35 µm
0 .0 0 1
0 .0 0 0 1
Single Pulse,1unit
10 µ
100 µ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet G15380EJ2V0DS
3
µPA1774
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
−20
FORWARD TRANSFER CHARACTERISTICS
−100
−18
−10
−16
−14
V GS = −10 V
−4.5 V
−4 V
−12
ID - Drain Current - A
ID - Drain Current - A
V DS = − 1 0 V
P u ls e d
Pulsed
−10
−8
−6
−4
−1
−0.1
T A = 1 5 0 °C
1 2 5 °C
7 5 °C
2 5 °C
-2 5 °C
−0.01
−0.001
−2
0
−1
0
−2
−3
−4
−0.0001
−5
VDS - Drain to Source Voltage - V
−2.0
−1.5
−1.0
−0.5
0
25
50
75 100 125 150 175
| yfs | - Forward Transfer Admittance - S
VGS(off) – Gate Cut-off Voltage - V
−2.5
0
1 0 .0 0
700
600
500
V G S = − 4 .0 V
− 4 .5 V
−10 V
300
200
100
0
−100
RDS(on) - Drain to Source On-state Resistance - mΩ
RDS(on) - Drain to Source On-state Resistance - mΩ
P u ls e d
−10
0 .1 0
0 .0 1
−0.01
−0.1
−1
−10
−100
400
P u ls e d
I D = −2 .8 A
300
200
100
ID - Drain Current - A
4
P u ls e d
V DS = − 1 0 V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
800
−1
T A = −2 5 °C
2 5 °C
7 5 °C
1 2 5°C
1 5 0°C
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
−0.1
−5
1 .0 0
Tch - Channel Temperature - °C
400
−4
1 0 0 .0 0
−3.0
-5 0 -2 5
−3
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
V SD = − 1 0 V
ID = − 1 m A
−3.5
−2
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
−4.0
−1
0
0
−5
−10
−15
VGS - Gate to Source Voltage - V
Data Sheet G15380EJ2V0DS
−20
µPA1774
CAPACITANCE vs.
DRAIN TO SOURCE VOLTAGE
500
1000
P ulsed
C iss
V G S = −4V
− 4.5 V
−10 V
400
Ciss, Coss, Crss - Capacitance - pF
300
200
C oss
100
C r ss
10
VGS = 0 V
f= 1 M H z
100
-50 -25
0
25
50
1
75 100 125 150 175
−0.1
Tch - Channel Temperature - °C
SWITCHING CHARACTERISTICS
VDS - Drain to Source Voltage - V
td(on), tr, td(off), tf - Switching Time - ns
V DD = − 30 V
V GS = −10 V
R G = 10 Ω
100
t d (o f f)
tf
t d (o n )
10
−100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
−60
tr
ID = −2.8 A
−12
−10
−50
VDD = −48 V
−30 V
−12 V
−40
−8
VGS
−30
−6
−20
−4
−2
−10
VDS
0
0
1
−0.1
−1
−10
0
−100
2
4
6
8
10
ID - Drain Current - A
QG - Gate Charge - nC
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
REVERSE RECOVERY TIME vs. DRAIN CURRENT
1000
P u ls e d
VGS = 0 V
d i/ d t = 1 0 0 A / n s
VGS = 0 V
−10
trr - Reverse Recovery Time - ns
ISD - Diode Forward Current - A
−10
VDS - Drain to Source Voltage - V
1000
−100
−1
VGS - Gate to Drain Voltage - V
RDS(on) - Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
−1
−0.1
100
10
−0.01
0
−0.5
−1.0
−1.5
VSD - Source to Drain Voltage - V
1
−0.1
−1
−10
−100
IF - Drain Current - A
Data Sheet G15380EJ2V0DS
5
µPA1774
SINGLE AVALANCHE ENERGY
DERATING FACTOR
100
V DD = −30 V, RG = 25 Ω
V GS = −20 → 0 V
Starting Tch = 25°C
IAS = −2.8 A
Energy Derating Factor - %
IAS - Single Avalanche Current - A
−10
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
E AS = 0.78 mJ
−1
80
60
40
20
−0.1
0.01
0.1
1
10
0
25
50
75
100
125
150
Starting Tch - Starting Channel Temperature - °C
L - Inductive Load - mH
6
V DD = − 30 V
VGS =−20 → 0 V
RG = 25 Ω
I A S ≤ − 2 .8 A
Data Sheet G15380EJ2V0DS
µPA1774
[MEMO]
Data Sheet G15380EJ2V0DS
7
µPA1774
• The information in this document is current as of May, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
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written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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M8E 00. 4