September 2007 ADC12DC080/ADC12DC105 Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS Outputs General Description Features NOTE: This is Advance Information for products currently in development. ALL specifications are design targets and are subject to change. The ADC12DC080 and ADC12DC105 are high-performance CMOS analog-to-digital converters capable of converting two analog input signals into 12-bit digital words at rates up to 80/105 Mega Samples Per Second (MSPS) respectively. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12DC080/105 may be operated from a single +3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12DC080/105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC12DC080/105 is available in a 60-lead LLP package and operates over the industrial temperature range of −40°C to +85°C. ■ ■ ■ ■ ■ ■ ■ ■ 1 GHz Full Power Bandwidth Internal sample-and-hold circuit and precision reference Low power consumption Clock Duty Cycle Stabilizer Single +3.3V supply operation Power-down mode Offset binary or 2's complement output data format 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch) Key Specifications ■ ■ ■ ■ ■ ■ ■ For ADC12DC105 Resolution Conversion Rate SNR (fIN = 240 MHz) SFDR (fIN = 240 MHz) Full Power Bandwidth Power Consumption 12 Bits 105 MSPS 67 dBFS (typ) 83 dBFS (typ) 1 GHz (typ) 800 mW (typ) Applications ■ ■ ■ ■ ■ High IF Sampling Receivers Wireless Base Station Receivers Test and Measurement Equipment Communications Instrumentation Portable Instrumentation Connection Diagram 30015401 © 2007 National Semiconductor Corporation 300154 www.national.com ADC12DC080/ADC12DC105 Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS Outputs ADVANCE INFORMATION ADC12DC080/ADC12DC105 Block Diagram 30015402 Ordering Information www.national.com Industrial (−40°C ≤ TA ≤ +85°C) Package ADC12DC080CISQ 60 Pin LLP ADC12DC105CISQ 60 Pin LLP 2 Pin No. Symbol Equivalent Circuit Description ANALOG I/O 3 13 VINA+ VINB+ 2 14 VINAVINB- 5 11 VRPA VRPB 7 9 VCMOA VCMOB 6 10 VRNA VRNB Differential analog input pins. The differential full-scale input signal level is 2VP-P with each input pin signal centered on a common mode voltage, VCM. These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor placed very close to the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. VRP and VRN should not be loaded. VCMO may be loaded to 1mA for use as a temperature stable 1.5V reference. It is recommended to use VCMO to provide the common mode voltage, VCM, for the differential analog inputs. VREF Reference Voltage. This device provides an internally developed 1.2V reference. When using the internal reference, VREF should be decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series inductance (ESL) capacitor. This pin may be driven with an external 1.2V reference voltage. This pin should not be used to source or sink current. 19 OF/DCS This is a four-state pin controlling the input clock mode and output data format. OF/DCS = VA, output data format is 2's complement without duty cycle stabilization applied to the input clock OF/DCS = AGND, output data format is offset binary, without duty cycle stabilization applied to the input clock. OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle stabilization applied to the input clock OF/DCS = (1/3)*VA, output data is offset binary with duty cycle stabilization applied to the input clock. 18 CLK The clock input pin. The analog inputs are sampled on the rising edge of the clock input. 59 DIGITAL I/O 57 20 This is a two-state input controlling Power Down. PD = VA, Power Down is enabled and power dissipation is reduced. PD = AGND, Normal operation. PD_A PD_B 3 www.national.com ADC12DC080/ADC12DC105 Pin Descriptions and Equivalent Circuits ADC12DC080/ADC12DC105 Pin No. Symbol Equivalent Circuit Description 42-49, 52-55 DA0-DA7, DA8-DA11 Digital data output pins that make up the 12-bit conversion result for Channel A. DA0 (pin 42) is the LSB, while DA11 (pin 55) is the MSB of the output word. Output levels are CMOS compatible. 23-24, 27-36 DB0-DB1, DB3-DB11 Digital data output pins that make up the 12-bit conversion result for Channel B. DB0 (pin 23) is the LSB, while DB11 (pin 36) is the MSB of the output word. Output levels are CMOS compatible. 39 DRDY Data Ready Strobe. The data output transition is synchronized with the falling edge of this signal. This signal switches at the same frequency as the CLK input. 8, 16, 17, 58, 60 VA Positive analog supply pins. These pins should be connected to a quiet source and be bypassed to AGND with 0.1 µF capacitors located close to the power pins. 1, 4, 12, 15, Exposed Pad AGND ANALOG POWER The ground return for the analog supply. DIGITAL POWER 26, 38,50 VDR 25, 37, 51 DRGND www.national.com Positive driver supply pin for the output drivers. This pin should be connected to a quiet voltage source and be bypassed to DRGND with a 0.1 µF capacitor located close to the power pin. The ground return for the digital output driver supply. This pins should be connected to the system digital ground, but not be connected in close proximity to the ADC's AGND pins. 4 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VDR) Voltage on Any Pin (Not to exceed 4.2V) Input Current at Any Pin other than Supply Pins (Note 4) Package Input Current (Note 4) Max Junction Temp (TJ) (Notes 1, 3) Operating Temperature Supply Voltage (VA) Output Driver Supply (VDR) Clock Duty Cycle (DCS Enabled) (DCS disabled) VCM |AGND-DRGND| −0.3V to 4.2V −0.3V to (VA +0.3V) ±5 mA ±50 mA +150°C 30°C/W −40°C ≤ TA ≤ +85°C +2.7V to +3.6V +2.4V to VA 30/70 % 45/55 % 1.4V to 1.6V ≤100mV Thermal Resistance (θJA) ESD Rating Human Body Model (Note 6) 2500V Machine Model (Note 6) 250V Storage Temperature −65°C to +150°C Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 7) ADC12DC080 Converter Electrical Characteristics This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifications cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) 12 Bits (min) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL Integral Non Linearity (Note 11) ±0.5 LSB (max) LSB (min) DNL Differential Non Linearity ±0.4 LSB (max) LSB (min) Under Range Output Code 0 0 Over Range Output Code 4095 4095 REFERENCE AND ANALOG INPUT CHARACTERISTICS VCMO Common Mode Output Voltage 1.5 1.45 1.55 V (min) V (max) VCM Analog Input Common Mode Voltage 1.5 1.4 1.6 V (min) V (max) CIN VIN Input Capacitance (each pin to GND) (Note 12) VREF VIN = 1.5 Vdc ± 0.5 V External Reference Voltage (CLK LOW) 8.5 (CLK HIGH) 3.5 1.20 5 pF pF 1.176 1.224 V (min) V (max) www.national.com ADC12DC080/ADC12DC105 Operating Ratings Absolute Maximum Ratings (Notes 1, 3) ADC12DC080/ADC12DC105 ADC12DC080 Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) Units (Limits) (Note 2) DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS FPBW Full Power Bandwidth SNR Signal-to-Noise Ratio SFDR ENOB THD H2 H3 SINAD -1 dBFS Input, −3 dB Corner Spurious Free Dynamic Range Effective Number of Bits Total Harmonic Disortion Second Harmonic Distortion Third Harmonic Distortion Signal-to-Noise and Distortion Ratio 1.0 GHz fIN = 10 MHz 71.2 dBFS fIN = 70 MHz 70 dBFS fIN = 170 MHz 68 dBFS fIN = 10 MHz 90 dBFS fIN = 70 MHz 88 dBFS fIN = 170 MHz 83 dBFS fIN = 10 MHz 11.5 Bits fIN = 70 MHz 11.3 Bits fIN = 170 MHz 11 Bits fIN = 10 MHz −88 dBFS fIN = 70 MHz −85 dBFS fIN = 170 MHz −80 dBFS fIN = 10 MHz −100 dBFS fIN = 70 MHz −95 dBFS fIN = 170 MHz −85 dBFS fIN = 10 MHz −90 dBFS fIN = 70 MHz −88 dBFS fIN = 170 MHz −83 dBFS fIN = 10 MHz 71.1 dBFS fIN = 70 MHz 69.8 dBFS fIN = 170 MHz 67.7 dBFS ADC12DC080 Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) 2.0 V (min) 0.8 V (max) DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B) VIN(1) Logical “1” Input Voltage VD = 3.6V VIN(0) Logical “0” Input Voltage VD = 3.0V IIN(1) Logical “1” Input Current VIN = 3.3V 10 µA IIN(0) Logical “0” Input Current VIN = 0V −10 µA CIN Digital Input Capacitance 5 pF DIGITAL OUTPUT CHARACTERISTICS (DA0-DA11,DB0-DB11,DRDY) VOUT(1) Logical “1” Output Voltage IOUT = −0.5 mA , VDR = 2.4V VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA, VDR = 2.4V +ISC Output Short Circuit Source Current VOUT = 0V −10 mA −ISC Output Short Circuit Sink Current VOUT = VDR 10 mA COUT Digital Output Capacitance 5 pF POWER SUPPLY CHARACTERISTICS www.national.com 6 1.2 V (min) 0.4 V (max) Parameter Conditions Typical (Note 10) Limits Units (Limits) IA Analog Supply Current Full Operation 200 mA (max) IDR Digital Output Supply Current Full Operation (Note 13) 26 mA Power Consumption Excludes IDR (Note 13) 600 mW (max) Power Down Power Consumption PD_A=PD_B=VA 30 mW ADC12DC080 Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Typical (Note 10) Limits Units (Limits) Maximum Clock Frequency 80 MHz (max) Minimum Clock Frequency 20 MHz (min) Symb Parameter Conditions tCH Clock High Time 6 tCL Clock Low Time 6 tCONV Conversion Latency tOD Output Delay of CLK to DATA Relative to rising edge of CLK 4 tSU Data Output Setup Time Relative to DRDY 5 ns (min) tH Data Output Hold Time Relative to DRDY 5 ns (min) tAD Aperture Delay 0.6 ns tAJ Aperture Jitter 0.1 ps rms 7 ns ns 7 Clock Cycles 2 6 ns (min) ns (max) www.national.com ADC12DC080/ADC12DC105 Symbol ADC12DC080/ADC12DC105 ADC12DC105 Converter Electrical Characteristics This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifications cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) Units (Limits) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes 12 Bits (min) INL Integral Non Linearity (Note 11) ±0.5 LSB (max) LSB (min) DNL Differential Non Linearity ±0.4 LSB (max) LSB (min) Under Range Output Code 0 0 Over Range Output Code 4095 4095 REFERENCE AND ANALOG INPUT CHARACTERISTICS VCMO Common Mode Output Voltage 1.5 1.45 1.55 V (min) V (max) VCM Analog Input Common Mode Voltage 1.5 1.4 1.6 V (min) V (max) CIN VIN Input Capacitance (each pin to GND) VIN = 1.5 Vdc (Note 12) ± 0.5 V VREF (CLK LOW) 8.5 (CLK HIGH) 3.5 External Reference Voltage 1.20 pF pF 1.176 1.224 V (min) V (max) ADC12DC105 Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical Limits (Note 10) Units (Limits) (Note 2) DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS FPBW Full Power Bandwidth SNR Signal-to-Noise Ratio SFDR ENOB THD H2 Spurious Free Dynamic Range Effective Number of Bits Total Harmonic Disortion Second Harmonic Distortion www.national.com -1 dBFS Input, −3 dB Corner 1.0 GHz fIN = 10 MHz 70.1 dBFS fIN = 70 MHz 69.1 dBFS fIN = 240 MHz 67 dBFS fIN = 10 MHz 88 dBFS fIN = 70 MHz 85 dBFS fIN = 240 MHz 83 dBFS fIN = 10 MHz 11.3 Bits fIN = 70 MHz 11.2 Bits fIN = 240 MHz 10.8 Bits fIN = 10 MHz −86 dBFS fIN = 70 MHz −85 dBFS fIN = 240 MHz −80 dBFS fIN = 10 MHz −95 dBFS fIN = 70 MHz −90 dBFS fIN = 240 MHz −85 dBFS 8 H3 SINAD Parameter Conditions Third Harmonic Distortion Signal-to-Noise and Distortion Ratio Typical Limits (Note 10) Units (Limits) (Note 2) fIN = 10 MHz −88 dBFS fIN = 70 MHz −85 dBFS fIN = 240 MHz −83 dBFS fIN = 10 MHz 70 dBFS fIN = 70 MHz 69 dBFS fIN = 240 MHz 66.8 dBFS ADC12DC105 Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits Units (Limits) DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B) VIN(1) Logical “1” Input Voltage VD = 3.6V 2.0 V (min) VIN(0) Logical “0” Input Voltage VD = 3.0V 0.8 V (max) IIN(1) Logical “1” Input Current VIN = 3.3V 10 µA IIN(0) Logical “0” Input Current VIN = 0V −10 µA CIN Digital Input Capacitance 5 pF DIGITAL OUTPUT CHARACTERISTICS (DA0-DA11,DB0-DB11,DRDY) VOUT(1) Logical “1” Output Voltage IOUT = −0.5 mA , VDR = 2.4V 1.2 V (min) VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA, VDR = 2.4V 0.4 V (max) +ISC Output Short Circuit Source Current VOUT = 0V −10 mA −ISC Output Short Circuit Sink Current VOUT = VDR 10 mA COUT Digital Output Capacitance 5 pF 242 mA (max) POWER SUPPLY CHARACTERISTICS IA Analog Supply Current Full Operation IDR Digital Output Supply Current Full Operation (Note 13) 32 mA Power Consumption Excludes IDR (Note 13) 800 mW (max) Power Down Power Consumption PD_A=PD_B=VA 33 mW ADC12DC105 Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF = +1.2V, fCLK = 105 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9) Symb Parameter Conditions Typical (Note 10) Maximum Clock Frequency Minimum Clock Frequency Limits Units (Limits) 105 MHz (max) 20 MHz (min) tCH Clock High Time 4 ns tCL Clock Low Time 4 ns tCONV Conversion Latency 7 Clock Cycles tOD Output Delay of CLK to DATA Relative to rising edge of CLK 4 2 6 ns (min) ns (max) tSU Data Output Setup Time Relative to DRDY 3 ns (min) tH Data Output Hold Time Relative to DRDY 3 ns (min) tAD Aperture Delay 0.6 ns tAJ Aperture Jitter 0.1 ps rms 9 www.national.com ADC12DC080/ADC12DC105 Symbol ADC12DC080/ADC12DC105 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. Note 2: This parameter is specified in units of dBFS - indicating the value that would be attained with a full-scale input signal. Note 3: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified. Note 4: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10. Note 5: The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient temperature, (TA), and can be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Note 6: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω Note 7: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 8: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per (Note 4). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. 30015411 Note 9: With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV. Note 10: Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not guaranteed. Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. Note 12: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance. Note 13: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. Note 14: This parameter is guaranteed by design and/or characterization and is not tested in production. www.national.com 10 APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both input terminals of the ADC. CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. CROSSTALK is coupling of energy from one channel into the other channel. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio or SINAD. ENOB is defined as (SINAD 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error − Negative Full Scale Error It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as: PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight line. The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS. LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n, where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC is guaranteed not to have any missing codes. where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power of the first 9 harmonic frequencies in the output spectrum. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. 11 www.national.com ADC12DC080/ADC12DC105 MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of ½ LSB above negative full scale. OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN-)] required to cause a transition from code 2047 to 2048. OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the output pins. PIPELINE DELAY (LATENCY) See CONVERSION LATENCY. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 1½ LSB below positive full scale. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply limit to the FullScale output of the ADC with the supply at the maximum DC supply limit, expressed in dB. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as Specification Definitions ADC12DC080/ADC12DC105 Timing Diagrams 30015409 FIGURE 1. Output Timing Transfer Characteristic 30015410 FIGURE 2. Transfer Characteristic www.national.com 12 ADC12DC080/ADC12DC105 Physical Dimensions inches (millimeters) unless otherwise noted TOP View...............................SIDE View...............................BOTTOM View 60-Lead LLP Package Ordering Numbers: ADC12DC080CISQ / ADC12DC105CISQ NS Package Number SQA60A 13 www.national.com ADC12DC080/ADC12DC105 Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS Outputs Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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