54F/74F825 8-Bit D-Type Flip-Flop General Description Features The ’F825 is an 8-bit buffered register. It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included in the ’F825 are multiple enables that allow multiuser control of the interface. The ’F825 is functionally and pin compatible with AMD’s Am29825. Y Commercial Package Number Military 74F825SPC 54F825SDM (Note 2) 74F825SC (Note 1) Y Y Y TRI-STATEÉ output Clock enable and clear Multiple output enables Direct replacement for AMD’s Am24825 Package Description N24C 24-Lead (0.300× Wide) Molded Dual-In-Line J24F 24-Lead (0.300× Wide) Ceramic Dual-In-Line M24B 24-Lead (0.300× Wide) Molded Small Outline, JEDEC 54F825FM (Note 2) W24C 24-Lead Cerpack 54F825LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13× reel. Use suffix e SCX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e SDMQB, FMQB and LMQB. Logic Symbols IEEE/IEC TL/F/9597 – 1 TL/F/9597 – 4 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9597 RRD-B30M75/Printed in U. S. A. 54F/74F825 8-Bit D-Type Flip-Flop December 1994 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9597 – 3 TL/F/9597–2 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL D 0 – D7 O0 – O7 OE1, OE2, OE3 EN CLR CP Data Inputs TRI-STATE Data Outputs Output Enable Input Clock Enable Clear Clock Input 1.0/1.0 150/40 (33.3) 1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 20 mA/b0.6 mA b 3 mA/24 mA (20 mA) 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b1.2 mA 2 Functional Description The ’F825 consists of eight D-type edge-triggered flip-flops. This device has TRI-STATE true outputs and is organized in broadside pinning. In addition to the clock and output enable pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE LOW the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The ’F825 has Clear (CLR) and Clock Enable (EN) pins. When the CLR is LOW and the OE is LOW the outputs are LOW. When CLR is HIGH, data can be entered into the flipflops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH the outputs do not change state, regardless of the data or clock input transitions. Function Table Inputs Internal Output OE CLR EN CP D Q O H H H L H L H H L L L L H H H H L L H H H H H H L L H H X X L L L L L L H L X X X X L L L L H L X X X X X X L H L H X X NC NC NC NC H H H L H L NC NC Z Z Z NC Z L Z Z L H NC NC Function Hold Hold Hold Hold Clear Clear Load Load Data Available Data Available No Change in Data No Change in Data L e LOW Voltage Level H e HIGH Voltage Level X e Immaterial Z e High Impedance L e LOW-to-HIGH Transition NC e No Change Logic Diagram TL/F/9597 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 Absolute Maximum Ratings (Note 1) Current Applied to Output in LOW State (Max) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Note 2: Either voltage limit or current limit is sufficient to protect inputs. b 55§ C to a 175§ C b 55§ C to a 150§ C VCC Pin Potential to Ground Pin Recommended Operating Conditions b 0.5V to a 7.0V Free Air Ambient Temperature Military Commercial b 0.5V to a 7.0V Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. b 30 mA to a 5.0 mA b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 0.5V to VCC b 0.5V to a 5.5V a 4.5V to a 5.5V a 4.5V to a 5.5V DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage Typ Units 2.0 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC VCC Conditions Max V 0.8 V b 1.2 V 2.5 2.4 2.5 2.4 2.7 2.7 Recognized as a HIGH Signal Recognized as a LOW Signal Min IIN e b18 mA V Min IOH IOH IOH IOH IOH IOH IOL e 20 mA IOL e 24 mA e e e e e e b 1 mA b 3 mA b 1 mA b 3 mA b 1 mA b 3 mA VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC 0.5 0.5 V Min IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 mA Max VIN e 0.5V IOZH Output Leakage Current 50 mA Max VOUT e 2.7V IOZL Output Leakage Current b 50 mA Max VOUT e 0.5V IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V IZZ Buss Drainage Test 500 mA 0.0V VOUT e 5.25V ICCZ Power Supply Current 90 mA Max VO e HIGH Z 4.75 b 60 75 4 AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Max Min Typ fmax Maximum Clock Frequency 100 160 tPLH tPHL Propagation Delay CP to On 2.0 2.0 6.5 6.6 9.5 9.5 2.0 2.0 10.5 10.5 2.0 2.0 10.5 10.5 ns tPHL Propagation Delay CLR to On 4.0 7.4 12.0 4.0 13.0 4.0 13.0 ns tPZH tPZL Output Enable Time OE to On 2.0 2.0 6.5 6.6 10.5 10.5 2.0 2.0 13.0 13.0 2.0 2.0 11.5 11.5 tPHZ tPLZ Output Disable TIme OE to On 1.5 1.5 3.5 3.3 7.0 7.0 1.0 1.0 7.5 7.5 1.5 1.5 7.5 7.5 60 Min Units Max 70 MHz ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max ts(H) ts(L) Setup Time, HIGH or LOW Dn to CP 2.5 2.5 4.0 4.0 3.0 3.0 th(H) th(L) Hold Time, HIGH or LOW Dn to CP 2.5 2.5 2.5 2.5 2.5 2.5 ts(H) ts(L) Setup Time, HIGH or LOW EN to CP 4.5 2.5 5.0 3.0 5.0 3.0 th(H) th(L) Hold Time, HIGH or LOW EN to CP 2.0 0 3.0 2.0 1.0 0 tw(H) tw(L) CP Pulse Width HIGH or LOW 5.0 5.0 6.0 6.0 6.0 6.0 Units Max ns ns ns tw(L) CLR Pulse Width, LOW 5.0 5.0 5.0 ns trec CLR Recovery Time 5.0 5.0 5.0 ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 825 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations X e Devices shipped in 13× reels QB e Military grade with environmental and burn-in processing shipped in tubes Device Type Package Code SP e Slim Plastic DIP SD e Slim Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline (SOIC) Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) 5 Physical Dimensions inches (millimeters) 28-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead (0.300× Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 6 Physical Dimensions inches (millimeters) (Continued) 24-Lead (0.300× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M24B 24-Lead (0.300× Wide) Molded Dual-In-Line Package (SP) NS Package Number N24C 7 54F/74F825 8-Bit D-Type Flip-Flop Physical Dimensions inches (millimeters) (Continued) 24-Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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