DYNEX DCR820N60

DCR820N65
Phase Control Thyristor
Preliminary Information
DS5923-1.3 June 2008 (LN 26210)
FEATURES
KEY PARAMETERS
Double Side Cooling
High Surge Capability
VDRM
IT(AV)
ITSM
dV/dt*
dI/dt
APPLICATIONS
6500V
820A
12000A
1500V/µs
200A/µs
* Higher dV/dt selections available
Medium Voltage Soft Starts
High Voltage Power Supplies
Static Switches
VOLTAGE RATINGS
Part and
Ordering
Number
Repetitive Peak
Voltages
VDRM and VRRM
V
DCR820N65*
DCR820N60
DCR820N55
DCR820N50
6500
6000
5500
5000
Conditions
Tvj = -40°C to 125°C,
IDRM = IRRM = 200mA,
VDRM, VRRM tp = 10ms,
VDSM & VRSM =
VDRM & VRRM + 100V
respectively
Lower voltage grades available.
0
0
6200V @ -40 C, 6500V @ 0 C
Outline type code: N
(See Package Details for further information)
Fig. 1 Package outline
ORDERING INFORMATION
When ordering, select the required part number
shown in the Voltage Ratings selection table.
For example:
DCR820N65
Note: Please use the complete part number when ordering
and quote this number in any future correspondence
relating to your order.
1/11
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DCR820N65
SEMICONDUCTOR
CURRENT RATINGS
Tcase = 60°C unless stated otherwise
Parameter
Symbol
Test Conditions
Max.
Units
820
A
Double Side Cooled
IT(AV)
Mean on-state current
IT(RMS)
RMS value
-
1288
A
Continuous (direct) on-state current
-
1090
A
IT
Half wave resistive load
SURGE RATINGS
Parameter
Symbol
ITSM
2
It
Surge (non-repetitive) on-state current
Test Conditions
Max.
Units
10ms half sine, Tcase = 125°C
12.0
kA
VR = 0
0.72
MA s
Min.
Max.
Units
2
I t for fusing
2
THERMAL AND MECHANICAL RATINGS
Symbol
Rth(j-c)
Rth(c-h)
Tvj
Parameter
Thermal resistance – junction to case
Thermal resistance – case to heatsink
Virtual junction temperature
Test Conditions
Double side cooled
DC
-
0.0221
°C/W
Single side cooled
Anode DC
-
0.041
°C/W
Cathode DC
-
0.0516
°C/W
Clamping force 23 kN
Double side
-
0.004
°C/W
(with mounting compound)
Single side
-
0.008
°C/W
On-state (conducting)
-
135
°C
Reverse (blocking)
-
125
°C
Tstg
Storage temperature range
-55
125
°C
Fm
Clamping force
20.0
25.0
kN
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DCR820N65
SEMICONDUCTOR
DYNAMIC CHARACTERISTICS
Symbol
IRRM/IDRM
Parameter
Test Conditions
Min.
Max.
Units
Peak reverse and off-state current
At VRRM/VDRM, Tcase = 125°C
-
200
mA
dV/dt
Max. linear rate of rise of off-state voltage
To 67% VDRM, Tj = 125°C, gate open
-
1500
V/µs
dI/dt
Rate of rise of on-state current
From 67% VDRM to 2x IT(AV)
Repetitive 50Hz
-
100
A/µs
Gate source 30V, 10,
Non-repetitive
-
200
A/µs
tr < 0.5µs, Tj = 125°C
VT(TO)
rT
tgd
Threshold voltage – Low level
100A to 870A at Tcase = 125°C
-
1.0
V
Threshold voltage – High level
870A to 3000A at Tcase = 125°C
-
1.1847
V
On-state slope resistance – Low level
100A to 870A at Tcase = 125°C
-
1.1429
m
On-state slope resistance – High level
870A to 3000A at Tcase = 125°C
-
0.9472
m
VD = 67% VDRM, gate source 30V, 10
-
3
µs
600
1000
µs
90
120
A
2500
4000
µC
Delay time
tr = 0.5µs, Tj = 25°C
tq
Turn-off time
Tj = 125°C,I peak = 1000A, tp = 1000us,
VRM = 100V, dI/dt = -5A/µs,
dVDR/dt = 20V/µs linear to 2500V
IRR
Reverse recovery current
QS
Stored charge
IL
Latching current
Tj = 25°C, VD = 5V
-
3
A
IH
Holding current
Tj = 25°C, RG-K = , ITM = 500A, IT = 5A
-
300
mA
IT = 1000A, tp = 1000us,Tj = 125°C,
dI/dt = - 5A/µs, VR = 100V
3/11
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DCR820N65
SEMICONDUCTOR
GATE TRIGGER CHARACTERISTICS AND RATINGS
Symbol
Parameter
Test Conditions
Max.
Units
VGT
Gate trigger voltage
VDRM = 5V, Tcase = 25°C
1.5
V
VGD
Gate non-trigger voltage
At 50% VDRM, Tcase = 125°C
0.4
V
IGT
Gate trigger current
VDRM = 5V, Tcase = 25°C
250
mA
IGD
Gate non-trigger current
At 50% VDRM, Tcase = 125°C
15
mA
CURVES
Instantaneous on-state current, I T - (A)
3500
3000
2500
2000
1500
min 25°C
1000
25°C max
125°C min
500
125°C max
0
1.0
2.0
3.0
4.0
Instantaneous on-state voltage, VT - (V)
5.0
Fig.2 Maximum & minimum on-state characteristics
VTM EQUATION
VTM = A + Bln (IT) + C.IT+D.IT
Where
A = 0.739446
B = 0.018199
C = 0.000769
D = 0.017564
these values are valid for Tj = 125°C for IT 300A to 3000A
4/11
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DCR820N65
SEMICONDUCTOR
125
Maximum case temperature, T case ( C )
16
Mean power dissipation - (kW)
o
14
12
10
8
6
180
120
90
60
30
4
2
100
75
50
25
0
0
0
500
1000
1500
2000
0
2500
Fig.3 On-state power dissipation – sine wave
1000
75
50
25
16
14
Mean power dissipation - (kW)
180
120
90
60
30
12
10
8
6
d.c.
180
120
90
60
30
4
2
0
0
500
1500
Fig.4 Maximum permissible case temperature,
double side cooled – sine wave
125
100
500
Mean on-state current, IT(AV) - (A)
Mean on-state current, IT(AV) - (A)
Maximum heatsink temperature, T Heatsink - ( ° C)
180
120
90
60
30
1000
1500
Mean on-state current, IT(AV) - (A)
Fig.5 Maximum permissible heatsink temperature,
double side cooled – sine wave
0
0
1000
2000
3000
4000
Mean on-state current, IT(AV) - (A)
Fig.6 On-state power dissipation – rectangular wave
5/11
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DCR820N65
SEMICONDUCTOR
125
d.c.
180
120
90
60
30
100
Maximum heatsink temperature T heatsink -(o C)
Maximum permissible case temperature , T case -(° C)
125
75
50
25
d.c.
180
120
90
60
30
100
75
50
25
0
0
0
500
1000
1500
0
2000
500
1000
1500
Mean on-state current, IT(AV) - (A)
Mean on-state current, IT(AV) - (A)
Fig.7 Maximum permissible case temperature,
double side cooled – rectangular wave
Thermal Impedance, Z th(j-c) ( °C/kW )
55.0
Zth Double Side Cooled
45.0
Zth Cathode Side Cooled
40.0
Fig.8 Maximum permissible heatsink temperature,
double side cooled – rectangular wave
Double side cooled
50.0
2000
Anode side cooled
Cathode side cooled
Zth Anode Side Cooled
Ri (°C/kW)
1
3.4733
2
4.9047
3
9.1463
Ti (s)
0.1457
0.0166
1.2832
0.3767
Ri (°C/kW)
7.6674
5.0530
9.7355
27.5992
Ti (s)
0.2241
0.0169
4.0566
8.2780
Ri (°C/kW)
6.0393
4.2782
5.1301
25.0874
Ti (s)
0.1356
0.0143
0.6594
7.2358
Z th [ Ri (1 exp(T / Ti )]
i 4
35.0
30.0
i 1
25.0
20.0
Rth(j-c) Conduction
15.0
Tables show the increments of thermal resistance Rth(j-c) when the device
operates at conduction angles other than d.c.
10.0
Double side cooling
5.0
0.0
0.001
4
4.5220
°
0.01
0.1
1
Time ( s )
10
100
180
120
90
60
30
15
Zth (z)
sine.
3.03
3.49
3.99
4.43
4.77
4.92
rect.
2.07
2.95
3.43
3.94
4.49
4.77
Anode Side Cooling
°
180
120
90
60
30
15
Zth (z)
sine.
3.03
3.49
3.99
4.43
4.76
4.92
rect.
2.07
2.95
3.43
3.94
4.48
4.77
Cathode Sided Cooling
°
180
120
90
60
30
15
Zth (z)
sine.
3.12
3.61
4.13
4.60
4.96
5.13
rect.
2.12
3.04
3.54
4.08
4.66
4.97
Fig.9 Maximum (limit) transient thermal impedance – junction to case (°C/kW)
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DCR820N65
SEMICONDUCTOR
100
30
1.5
Conditions:
Tcase = 125°C
VR =0
Pulse width = 10ms
2
1
2
2
10
Conditions:
Tcase= 125°C
VR = 0
half-sine wave
0.5
ITSM
0
1
Surge current, ITSM- (kA)
20
I t (MA s)
Surge current, ITSM - (kA)
It
0
100
10
10
1
1
10
Pulse width, tP - (ms)
100
Number of cycles
Fig.10 Single-cycle surge current
Fig.11 Multi-cycle surge current
600
8000
0.2795
QSmax = 2550.9*(di/dt)
Reverse recovery current, I RR - (A)
7000
Stored charge, QS - (uC)
6000
5000
4000
QSmin = 1325.8(di/dt)0.3941
3000
Conditions :
IF = 1000A
tp = 1000us
VRM = 100V
2000
1000
IRRmax = 41.65*(di/dt)0.6452
500
400
300
IRRmin = 28.33*(di/dt)
0.7182
200
Conditions:
IF = 1000A
tp = 1000us
VRM = 100V
100
o
Tj = 125oC
Tj = 125 C
0
0
0
20
40
60
Rate of decay of on-state current, di/dt - (A/us)
Fig.12 Stored charge
0
10
20
30
40
50
60
Rate of decay of on-state current, di/dt - (A/us)
Fig.13 Reverse recovery current
7/11
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DCR820N65
SEMICONDUCTOR
10
9
Pulse
Width us
100
200
500
1000
10000
Gate trigger voltage, VGT - (V)
8
7
Pulse Power PGM (Watts)
Frequency Hz
50
100
150
150
150
150
150
150
150
100
20
-
400
150
125
100
25
-
Upper Limit
6
5
Preferred gate drive area
4
3
2
o
1
Tj = -40oC
Tj = 25oC
Lower Limit
Tj = 125 C
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Gate trigger current IGT, - (A)
Fig14 Gate Characteristics
30
Lower Limit
Upper Limit
5W
10W
20W
50W
100W
150W
-40C
Gate trigger voltage, VGT - (V)
25
20
15
10
5
0
0
1
2
3
4
5
6
7
8
9
10
Gate trigger current, IGT - (A)
Fig. 15 Gate characteristics
8/11
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DCR820N65
SEMICONDUCTOR
1.35
Normalised Turn-off time, Tq - (us)
1.3
Tq (dv/dt) =
1.25
Tq(20V/us).0.7148.(dv/dt)0.1124
1.2
1.15
1.1
1.05
Conditions:
o
Tj = 125 C
I F = 1000A
tp = 1000us
VRM = 100V
di/dt = -5A/us
1
0.95
0.9
0.85
0.8
0.75
0
20
40
60
80
100
120
Rate of change of reapplied voltage, dv/dt - (V/us)
Fig.16 Turn-off time
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DCR820N65
SEMICONDUCTOR
PACKAGE DETAILS
For further package information, please contact Customer Services. All dimensions in mm, unless stated otherwise.
DO NOT SCALE.
3rd ANGLE PROJECTION
DO NOT SCALE
IF IN DOUBT ASK
HOLE Ø3.60 X 2.00
DEEP (IN BOTH
ELECTRODES)
20° OFFSET (NOM.)
TO GATE TUBE
Device
DCR1710N22
DCR1530N28
DCR1260N42
DCR1110N52
DCR820N65
DCR890N65
DCR760N85
Maximum Minimum
Thickness Thickness
(mm)
(mm)
34.465
33.915
34.54
33.99
34.77
34.22
34.89
34.34
35.15
34.6
35.15
34.6
35.51
34.96
Ø73.0 MAX
Ø47.0 NOM
Ø1.5
CATHODE
GATE
ANODE
Ø47.0 NOM
FOR PACKAGE HEIGHT
SEE TABLE
Lead length: 420mm
Lead terminal connector: M4 ring
Package outline type code: N
Fig.17 Package outline
10/11
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DCR820N65
SEMICONDUCTOR
POWER ASSEMBLY CAPABILITY
The Power Assembly group was set up to provide a support service for those customers requiring more than the basic
semiconductor, and has developed a flexible range of heatsink and clamping systems in line with advances in device voltages
and current capability of our semiconductors.
We offer an extensive range of air and liquid cooled assemblies covering the full range of circuit designs in general use today.
The Assembly group offers high quality engineering support dedicated to designing new units to satisfy the growing needs of our
customers.
Using the latest CAD methods our team of design and applications engineers aim to provide the Power Assembly Complete
Solution (PACs).
HEATSINKS
The Power Assembly group has its own proprietary range of extruded aluminium heatsinks which have been designed to optimise
the performance of Dynex semiconductors. Data with respect to air natural, forced air and liquid cooling (with flow rates) is
available on request.
For further information on device clamps, heatsinks and assemblies, please contact your nearest sales representative or
Customer Services.
Stresses above those listed in this data sheet may cause permanent damage to the device. In extreme conditions, as with all
semiconductors, this may include potentially hazardous rupture of the package. Appropriate safety precautions should always be
followed.
http://www.dynexsemi.com
e-mail: power_solutions@dynexsemi.com
HEADQUARTERS OPERATIONS
DYNEX SEMICONDUCTOR LTD
Doddington Road, Lincoln
Lincolnshire, LN6 3LF. United Kingdom.
Tel: +44(0)1522 500500
Fax: +44(0)1522 500550
CUSTOMER SERVICE
Tel: +44(0)1522 502753 / 502901. Fax: +44(0)1522 500020
Dynex Semiconductor 2003 TECHNICAL DOCUMENTATION – NOT FOR
RESALE. PRODUCED IN UNITED KINGDOM.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or
contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or
suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible
methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to
fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These
products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided
subject to the Company’s conditions of sale, which are available on request.
All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners.
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