GM71V18160C GM71VS18160CL 1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM Description Features The GM71V(S)18160C/CL is the new generation dynamic RAM organized 1,048,576 x 16 bit. GM71V(S)18160C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)18160C/CL offers Fast Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71V(S)18160C/CL to be packaged in standard 400 mil 42pin plastic SOJ, and standard 400mil 44(50)pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. * 1,048,576 Words x 16 Bit Organization * Fast Page Mode Capability * Single Power Supply (3V+/-0.3V) * Fast Access Time & Cycle Time Pin Configuration tRAC tCAC 44(50) TSOP II VCC 1 42 VSS I/O0 I/O1 2 41 3 40 I/O15 I/O14 I/O2 I/O3 4 39 5 38 I/O13 I/O12 VCC 6 37 VSS I/O4 I/O5 7 36 8 35 I/O11 I/O10 I/O6 I/O7 NC 9 34 10 33 I/O9 I/O8 11 32 NC 12 31 13 30 LCAS UCAS RAS 14 29 OE NC NC A0 15 28 16 27 17 26 A9 A8 A7 A1 A2 A3 VCC 18 25 19 24 20 23 21 22 VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC A6 A5 A4 VSS (Top View) Rev 0.1 / Apr’01 13 15 18 tRC tPC 90 110 130 35 40 45 * Low Power Active : 684/612/540/468mW (MAX) Standby : 7.2mW (CMOS level : MAX) 0.54mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 1024 Refresh Cycles/16ms * 1024 Refresh Cycles/128ms (L-version) * Self Refresh Operation (L-version) * Battery Back Up Operation (L-version) * 2 CAS byte Control 42 SOJ NC WE 50 60 70 GM71V(S)18160C/CL-5 GM71V(S)18160C/CL-6 GM71V(S)18160C/CL-7 (Unit: ns) 1 50 2 49 3 48 4 47 5 46 6 45 7 44 8 43 9 42 10 41 11 40 NC NC 15 36 16 35 WE RAS A11 A10 A0 A1 A2 A3 VCC 17 34 18 33 19 32 20 31 21 30 22 29 23 28 24 27 25 26 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS GM71V18160C GM71VS18160CL Pin Description Pin Function Pin Function A0-A9 Address Inputs WE Read/Write Enable A0-A9 Refresh Address Inputs OE Output Enable I/O0-I/O15 Data Input/ Data Output VCC Power (+3.3V) Row Address Strobe VSS Ground Column Address Strobe NC No Connection RAS UCAS, LCAS Ordering Information Type No. Access Time Package GM71V(S)18160CJ/CLJ -5 GM71V(S)18160CJ/CLJ -6 GM71V(S)18160CJ/CLJ -7 50ns 60ns 70ns 400 Mil 42 Pin Plastic SOJ GM71V(S)18160CT/CLT -5 GM71V(S)18160CT/CLT -6 GM71V(S)18160CT/CLT -7 50ns 60ns 70ns 400 Mil 44(50) Pin Plastic TSOP II Absolute Maximum Ratings* Symbol Parameter Rating Unit 0 ~ 70 C -55 ~ 125 C -0.5 ~ Vcc+0.5 (<=4.6V(MAX)) V -0.5 ~ 4.6 V TA Ambient Temperature under Bias TSTG Storage Temperature VIN/OUT Voltage on any Pin Relative to VSS VCC Supply Voltage Relative to VSS IOUT Short Circuit Output Current 50 mA PD Power Dissipation 1.0 W Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability. Rev 0.1 / Apr’01 GM71V18160C GM71VS18160CL Recommended DC Operating Conditions (TA = 0 ~ +70C) Symbol Parameter Min Typ Max Unit VCC Supply Voltage 3.0 3.3 3.6 V VIH Input High Voltage 2.0 - VCC + 0.3 V VIL Input Low Voltage -0.3 - 0.8 V Note: All voltage referred to Vss. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. Truth Table RAS LCAS UCAS WE OE Output Operation H D D D D Open L L H H L Valid Lower byte L H L H L Valid Upper byte L L L H L Valid Word L L H L D Open Lower byte L H L L D Open Upper byte L L L L D Open Word L L H L H Undefined Lower byte L H L L H Undefined Upper byte L L L L H Undefined Word L L H H to L L to H Valid Lower byte L H L H to L L to H Valid Upper byte L L L H to L L to H Valid Word H to L H L D D Open Word H to L L H D D Open Word H to L L L D D Open Word L H H D D Open Word L L L H H Open Standby 1,3 Read cycle 1,3 Early write cycle 1,2,3 Delayed Write cycle 1,2,3 Read-modify -write cycle 1,3 CBR Refresh or Self Refresh (L-series) 1,3 RAS-only Refresh cycle 1,3 Read cycle (Output disabled) Notes: 1. H: High (inactive) L: Low(active) D: H or L 2. tWCS >= 0ns Early write cycle tWCS <= 0ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output High-Z control are done independently by each UCAS,LCAS. ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. Rev 0.1 / Apr’01 Notes 1,3 GM71V18160C GM71VS18160CL DC Electrical Characteristics (VCC = 3.3V+/-0.3V, Vss = 0V, TA = 0 ~ 70C) Symbol Parameter Min Max Unit VOH Output Level Output "H" Level Voltage (IOUT = -2mA) 2.4 VCC V VOL Output Level Output "L" Level Voltage (IOUT = 2mA) 0 0.4 V ICC1 Operating Current Average Power Supply Operating Current (RAS, UCAS or LCAS Cycling: tRC = tRC min) 50ns - 190 60ns - 170 70ns - 150 - 2 ICC2 ICC3 ICC4 ICC5 ICC6 Standby Current (TTL) Power Supply Standby Current (RAS, UCAS, LCAS = VIH, D OUT = High-Z) mA 50ns - 190 60ns - 170 70ns - 150 Fast Page Mode Current Average Power Supply Current Fast Page Mode (tPC = tPC min) 50ns - 185 60ns - 165 70ns - 145 - 1 mA - 150 uA 50ns - 190 60ns - 170 70ns - 150 CAS-before-RAS Refresh Current (tRC = tRC min) 1, 2 mA RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (tRC = tRC min) Standby Current (CMOS) Power Supply Standby Current (RAS, UCAS or LCAS >= VCC - 0.2V, DOUT = High-Z) Note mA 2 mA 1, 3 5 mA ICC7 Battery Back Up Operating Current (Standby with CBR Refresh) (tRC=125us, tRAS<=0.3us, DOUT=High-Z) - 400 uA 4,5 ICC8 Standby Current RAS = VIH UCAS, LCAS = VIL DOUT = Enable - 5 mA 1 ICC9 Self-Refresh Mode Current (RAS, UCAS or LCAS<=0.2V, DOUT=High-Z) Input Leakage Current Any Input (0V<=VIN<= 4.6V) - 250 uA 5 -10 10 uA -10 10 uA IL(I) IL(O) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<= 4.6V) Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while LCAS and UCAS = VIH. 4. UCAS = L (<=0.2) and LCAS = L (<=0.2) while RAS = L (<=0.2). 5. L-version. Rev 0.1 / Apr’01 GM71V18160C GM71VS18160CL Capacitance (VCC = 3.3V+/-0.3V, TA = 25C) Symbol Parameter Min Max Unit Note CI1 Input Capacitance (Address) - 5 pF 1 CI2 Input Capacitance (Clocks) - 7 pF 1 CI/O Output Capacitance (Data-In/Out) - 7 pF 1, 2 Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. UCAS and LCAS = VIH to disable DOUT. AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ 70C, Note 1, 2, 18, 19, 20) Test Conditions Input rise and fall times : 5 ns Input timing reference levels : 0.8V, 2.0V Output timing reference levels : 0.8V, 2.0V Output load : 1TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Symbol Parameter GM71V(S)18160 GM71V(S)18160 GM71V(S)18160 C/CL-6 C/CL-7 C/CL-5 Unit Note Min Max Min Max Min Max tRC Random Read or Write Cycle Time 90 - 110 - 130 - ns tRP RAS Precharge Time 30 - 40 - 50 - ns tCP CAS Precharge Time 8 - 10 - 10 - ns tRAS RAS Pulse Width 50 10,000 60 10,000 70 10,000 ns tCAS CAS Pulse Width 13 10,000 15 10,000 18 10,000 ns tASR Row Address Set up Time 0 - 0 - 0 - ns tRAH Row Address Hold Time 8 - 10 - 10 - ns tASC Column Address Set-up Time 0 - 0 - 0 - ns 21 tCAH tRCD tRAD Column Address Hold Time 8 - 10 - 15 - ns 21 RAS to CAS Delay Time 18 45 20 45 20 52 ns 3 RAS to Column Address Delay Time 13 30 15 30 15 35 ns 4 tRSH tCSH RAS Hold Time 13 - 15 - 18 - ns CAS Hold Time 50 - 60 - 70 - ns 23 tCRP tODD CAS to RAS Precharge Time 5 - 5 - 5 - ns 22 13 - 15 - 18 - ns 5 OE Delay Time from DIN 0 - 0 - 0 - ns 6 CAS Delay Time from DIN 0 - 0 - 0 - ns 6 Transition Time (Rise and Fall) 3 50 3 50 3 50 ns 7 tDZO tDZC tT OE to DIN Delay Time Rev 0.1 / Apr’01 24 GM71V18160C GM71VS18160CL Read Cycle Symbol Parameter GM71V(S)18160 GM71V(S)18160 GM71V(S)18160 C/CL-6 C/CL-5 C/CL-7 Min Max Unit Note Min Max Min Max tRAC Access Time from RAS - 50 - 60 - 70 ns 8,9 tCAC Access Time from CAS - 13 - 15 - 18 ns 9,10,17 tAA Access Time from Address - 25 - 30 - 35 ns 9,10,17 tOAC Access Time from OE - 13 - 15 - 18 ns 9,25 tRCS Read Command Setup Time 0 - 0 - 0 - ns tRCH Read Command Hold Time to CAS 0 - 0 - 0 - ns 12,22 tRRH tRAL Read Command Hold Time to RAS 5 - 5 - 5 - ns 12 Column Address to RAS Lead Time 25 - 30 - 35 - ns tCAL Column Address to CAS Lead Time 25 - 30 - 35 - ns tCLZ CAS to Output in Low-Z 0 - 0 - 0 - ns tOH Output Data Hold Time 3 - 3 - 3 - ns tOHO Output Data Hold Time from OE 3 - 3 - 3 - ns tOFF Output Buffer Turn-off Time - 13 - 15 - 15 ns 13 tOEZ Output Buffer Turn-off Time to OE - 13 - 15 - 15 ns 13 tCDD CAS to DIN Delay Time 13 - 15 - 18 - ns 5 Unit Note Write Cycle Symbol Parameter GM71V(S)18160 GM71V(S)18160 GM71V(S)18160 C/CL-5 C/CL-6 C/CL-7 Min Max Min Max Min Max tWCS Write Command Setup Time 0 - 0 - 0 - ns 14,21 tWCH Write Command Hold Time 8 - 10 - 15 - ns 21 tWP Write Command Pulse Width 8 - 10 - 10 - ns tRWL Write Command to RAS Lead Time 13 - 15 - 18 - ns tCWL Write Command to CAS Lead Time 13 - 15 - 18 - ns 23 tDS tD Data-in Setup Time 0 - 0 - 0 - ns 15,23 Data-in Hold Time 8 - 10 - 15 - ns 15,23 H Rev 0.1 / Apr’01 GM71V18160C GM71VS18160CL Read- Modify-Write Cycle Symbol Parameter GM71V(S)18160 GM71V(S)18160 GM71V(S)18160 C/CL-5 C/CL-6 C/CL-7 Unit Note Min Max Min Max Min Max tRWC Read-Modify-Write Cycle Time tRWD 131 - 155 - 181 - ns RAS to WE Delay Time 73 - 85 - 98 - ns 14 tCWD CAS to WE Delay Time 36 - 40 - 46 - ns 14 tAWD Column Address to WE Delay Time 48 - 55 - 63 - ns 14 tOEH OE Hold Time from WE 13 - 15 - 18 - ns Refresh Cycle Symbol Parameter GM71V(S)18160 GM71V(S)18160 GM71V(S)18160 C/CL-5 C/CL-6 C/CL-7 Unit Note Min Max Min Max Min Max tCSR CAS Setup Time (CAS-before-RAS Refresh Cycle) 5 - 5 - 5 - ns 21 tCHR CAS Hold Time (CAS-before-RAS Refresh Cycle) 8 - 10 - 10 - ns 22 tRPC RAS Precharge to CAS Hold Time 5 - 5 - 5 - ns 21 Unit Note Fast Page Mode Cycle Symbol Parameter GM71V(S)18160 GM71V(S)18160 GM71V(S)18160 C/CL-6 C/CL-7 C/CL-5 Min Max Min Max Min Max tPC Fast Page Mode Cycle Time tRASP 35 - 40 - 45 - ns Fast Page Mode RAS Pulse Width - 100,000 - 100,000 - 100,000 ns 16 tACP Access Time from CAS Precharge - 30 - 35 - 40 ns 9,17,22 tRHCP RAS Hold Time from CAS Precharge 30 - 35 - 40 - ns Fast Page Mode Read-Modify-Write Cycle Symbol Parameter GM71V(S)18160 GM71V(S)18160 GM71V(S)18160 C/CL-5 C/CL-6 C/CL-7 Unit Note Min Max Min Max Min Max tPRWC Fast Page Mode Read-Modify-Write Cycle Time 76 - 85 - 96 - ns tCPW WE Delay Time from CAS Precharge 53 - 60 - 68 - ns Rev 0.1 / Apr’01 14,22 GM71V18160C GM71VS18160CL Self Refresh Mode Symbol Parameter tRASS RAS Pulse Width(Self-Refresh) tRPS tCHS GM71VS18160 CL-5 GM71VS18160 CL-6 GM71VS18160 CL-7 Min Max Min Max Min Max Unit Note 26 100 - 100 - 100 - us RAS Precharge Time(Self-Refresh) 90 - 110 - 130 - ns CAS Hold Time(Self-Refresh) -50 - -50 - -50 - ns Notes: 1. AC measurements assume tT = 5ns. 2. An initial pause of 200us is required after power up followed by a minimum of eight initialization cycles(any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD(max)limit insures that tRAC(max)can be met, tRCD(max)is specified as a reference point only; if tRCD >= tRAD(max) + tAA(max) - tCAC(max), then access time is controlled exclusively by tCAC. 4. Operation with the tRAD(max) limit insures that tRAC(max)can be met, tRAD(max)is specified as a reference point only; if tRAD is greater than the specified tRAD(max)limit, then access time is controlled exclusively by tAA. 5. Either tODD or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH(min) and VIL(max). 8. Assumes that tRCD <= tRCD(max) and tRAD <= tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL load and 100pF. 10. Assumes that tRCD >= tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max). 11. Assumes that tRAD >= tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS >= tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle ; if tRWD >= tRWD(min), tCWD >=tCWD(min), and tAWD >= tAWD(min), or tCWD >= tCWD(min),tAWD >= tAWD(min) and tCPW >= tCPW(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of data out (at access time)is indeterminate. Rev 0.1 / Apr’01 GM71V18160C GM71VS18160CL 15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among tAA,tCAC,and tACP. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH >= tCWL, the I/O pin will remain open circuit (high impedance); if tOEH< tCWL, invalid data will be out at each I/O. 19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 20. All the VCC and VSS pins shall be supplied with the same voltages. 21. tASC, tCAH, tRCS, tWCS,tWCH,tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS. 22. tCRP,tCHR, tRCH, tACP and tCPW are determined by the later rising edge of UCAS or LCAS. 23. tCWL, tDH,tDS and tCSH should be satisfied by both UCAS and LCAS. 24. tCP is determined by that time the both UCAS and LCAS are high. 25. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 26. Please do not use tRASS timing, 10us <= tRASS <=100us. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS >=100us, then RAS precharge time should use tRPS instead of tRP. 27. H or L (H: VIH(min) <= VIN <= VIH(max), L: VIL(min) <= VIN <= VIL(max)) Rev 0.1 / Apr’01 GM71V18160C GM71VS18160CL Package Dimension Unit: Inches (mm) 42 SOJ 0.025(0.64) 0.380(9.65) MAX 0.360(9.15) MIN 0.435(11.06) MIN 0.445(11.30) MAX 0.405(10.29) MAX 0.395(10.03) MIN MIN 0.093(2.38) 1.058(26.89) MAX MIN 1.072(27.23) MAX 0.128(3.25) MIN 0.148(3.75) MAX 0.050(1.27) 0.026(0.66) MIN 0.032(0.81) MAX TYP 0.015(0.38) MIN 0.020(0.50) MAX 44(50) TSOP I 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX Rev 0.1 / Apr’01 0.016(0.40) MIN 0.024(0.60) MAX 0.004(0.12) MIN 0.008(0.21) MAX 0.820(20.82) MIN 0.830(21.08) MAX 0.012(0.30) MIN 0.017(0.45) MAX £ 0.471(11.96) MAX 0.455(11.56) MIN 0.405(10.29) MAX 0.394(10.03) MIN 0 ~ 5¡ 0.031(0.80) TYP 0.002(0.05) MIN 0.006(0.15) MAX