ETC SST32HF402-70-4C-L3K

Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
SST32HF202 / 4022Mb Flash + 2Mb SRAM, 4Mb Flash + 2Mb SRAM (x16) MCP ComboMemories
Data Sheet
FEATURES:
• MPF + SRAM ComboMemory
– SST32HF202: 128K x16 Flash + 128K x16 SRAM
– SST32HF402: 256K x16 Flash + 128K x16 SRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
– Read from or write to SRAM while
Erase/Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or SRAM Read
– Standby Current: 20 µA (typical)
• Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
• Fast Read Access Times:
– Flash: 70 and 90 ns
– SRAM: 70 and 90 ns
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time:
SST32HF202: 2 seconds (typical)
SST32HF402: 4 seconds (typical)
• Flash Automatic Erase and Program Timing
– Internal VPP Generation
• Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Conforms to Flash pinout
• Packages Available
– 48-ball LFBGA (6mm x 8mm)
– Non-Pb package available
PRODUCT DESCRIPTION
The SST32HF202/402 ComboMemory devices integrate a
128K x16 or 256K x16 CMOS flash memory bank with a
128K x16 CMOS SRAM memory bank in a Multi-Chip
Package (MCP), manufactured with SST’s proprietary, high
performance SuperFlash technology.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
14 µsec. The entire flash memory bank can be erased and
programmed word-by-word in typically 2 seconds for the
SST32HF202 and 4 seconds for the SST32HF402, when
using interface features such as Toggle Bit or Data# Polling
to indicate the completion of Program operation. To protect
against inadvertent flash write, the SST32HF202/402
devices contain on-chip hardware and software data protection schemes. The SST32HF202/402 devices offer a
guaranteed endurance of 10,000 cycles. Data retention is
rated at greater than 100 years.
The SST32HF202/402 devices consist of two independent
memory banks with respective bank enable signals. The
Flash and SRAM memory banks are superimposed in the
same memory address space. Both memory banks share
common address lines, data lines, WE# and OE#. The
memory bank selection is done by memory bank enable
signals. The SRAM bank enable signal, BES# selects the
©2002 Silicon Storage Technology, Inc.
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SRAM bank. The flash memory bank enable signal, BEF#
selects the flash memory bank. The WE# signal has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
The SST32HF202/402 provide the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs SectorErase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automatically latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
The SST32HF202/402 devices are suited for applications
that use both flash memory and SRAM memory to store
code or data. For systems requiring low power and small
form factor, the SST32HF202/402 devices significantly
improve performance and reliability, while lowering power
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
SRAM Write
consumption, when compared with multiple chip solutions.
The SST32HF202/402 inherently use less energy during
erase and program than alternative flash technologies. The
total energy consumed is a function of the applied voltage,
current, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than
alternative flash technologies.
The SRAM Write operation of the SST32HF202/402 is
controlled by WE# and BES#, both have to be low for the
system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising
edge of either BES# or WE#, whichever occurs first. The
write time is measured from the last falling edge to the first
rising edge of BES# or WE#. See Figures 3 and 4 for the
Write cycle timing diagrams.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
Flash Operation
With BEF# active, the SST32HF202 operates as 128K x16
flash memory and the SST32HF402 operates as 256K x16
flash memory. The flash memory bank is read using the
common address lines, data lines, WE# and OE#. Erase
and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are
latched during the SDP commands and during the internally-timed Erase and Program operations.
Device Operation
The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. When
BES# is low, the SRAM Bank is activated for Read and
Write operation. When BEF# is low the flash bank is activated for Read, Program or Erase operation. BES# and
BEF# cannot be at low level at the same time. If BES# and
BEF# are both asserted to low level bus contention will
result and the device may suffer permanent damage. All
address, data, and control lines are shared by SRAM Bank
and flash bank which minimizes power consumption and
loading. The device goes into standby when both bank
enables are high.
Flash Read
The Read operation of the SST32HF202/402 devices is
controlled by BEF# and OE#. Both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# and BES# are high, both banks are deselected and
only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data
bus is in high impedance state when OE# is high. Refer to
Figure 5 for further details.
SRAM Operation
Flash Erase/Program Operation
With BES# low and BEF# high, the SST32HF202/402
operate as 128K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The
SST32HF202/402 SRAM is mapped into the first 128
KWord address space. When BES# and BEF# are high,
both memory banks are deselected and the device enters
standby mode. Read and Write cycle times are equal. The
control signals UBS# and LBS# provide access to the
upper data byte and lower data byte. See Table 3 for SRAM
Read and Write data byte control modes of operation.
SDP commands are used to initiate the flash memory bank
Program and Erase operations of the SST32HF202/402.
SDP commands are loaded to the flash memory bank
using standard microprocessor write sequences. A command is loaded by asserting WE# low while keeping BEF#
low and OE# high. The address is latched on the falling
edge of WE# or BEF#, whichever occurs last. The data is
latched on the rising edge of WE# or BEF#, whichever
occurs first.
SRAM Read
Flash Word-Program Operation
The SRAM Read operation of the SST32HF202/402 is
controlled by OE# and BES#, both have to be low with
WE# high for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high. See
Figure 2 for the Read cycle timing diagram.
The flash memory bank of the SST32HF202/402 devices is
programmed on a word-by-word basis. Before Program
operations, the memory must be erased first. The Program
operation consists of three steps. The first step is the threebyte load sequence for Software Data Protection. The second step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
falling edge of either BEF# or WE#, whichever occurs last.
The data is latched on the rising edge of either BEF# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 20
µs. See Figures 6 and 7 for WE# and BEF# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid flash
Read operations are Data# Polling and Toggle Bit. During
the internal Program operation, the host is free to perform
additional tasks. Any SDP commands loaded during the
internal Program operation will be ignored.
4 for the command sequence, Figure 9 for timing diagram,
and Figure 20 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST32HF202/402 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejection is valid.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-byblock) basis. The SST32HF202/402 offer both SectorErase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle. The address
lines A16-A11, for SST32HF202, and A17-A11, for
SST32HF402, are used to determine the sector address.
The Block-Erase operation is initiated by executing a sixbyte command sequence with Block-Erase command
(50H) and block address (BA) in the last bus cycle. The
address lines A16-A15, for SST32HF202, and A17-A15, for
SST32HF402, are used to determine the block address.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. See Figures 11
and 12 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Flash Data# Polling (DQ7)
When the SST32HF202/402 flash memory banks are in
the internal Program operation, any attempt to read DQ7
will produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. Note that even though DQ7 may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles, after an interval of 1 µs. During
internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed,
DQ7 will produce a ‘1’. The Data# Polling is valid after the
rising edge of the fourth WE# (or BEF#) pulse for Program
operation. For Sector- or Block-Erase, the Data# Polling is
valid after the rising edge of the sixth WE# (or BEF#) pulse.
See Figure 8 for Data# Polling timing diagram and Figure
18 for a flowchart.
Flash Chip-Erase Operation
The SST32HF202/402 provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
Flash Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating ‘1’s
and ‘0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the toggling will
stop. The flash memory bank is then ready for the next
operation. The Toggle Bit is valid after the rising edge of the
fourth WE# (or BEF#) pulse for Program operation. For
The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
Sector- or Bank-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 9 for
Toggle Bit timing diagram and Figure 18 for a flowchart.
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program
operation is in progress.
Flash Memory Data Protection
The SST32HF202/402 flash memory bank provides both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Product Identification
The Product Identification mode identifies the devices as
the SST32HF202/402 and manufacturer as SST. This
mode may be accessed by software operations only.
The hardware device ID Read operation, which is typically used by programmers, cannot be used on this
device because of the shared lines between flash and
SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device.
Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details, see
Tables 3 and 4 for software operation, Figure 13 for the
software ID entry and Read timing diagram, and Figure 19
for the ID entry command sequence flowchart.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
Flash Software Data Protection (SDP)
The SST32HF202/402 provide the JEDEC approved software data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HF202/402 devices are shipped with the software
data protection permanently enabled. See Table 4 for the
specific software command codes. During SDP command
sequence, invalid SDP commands will abort the device to
the Read mode, within Read Cycle Time (TRC).
TABLE 1: PRODUCT IDENTIFICATION
Data
0000H
00BFH
SST32HF202
0001H
2789H
SST32HF402
0001H
2780H
Manufacturer’s ID
Device ID
T1.1 557
Product Identification Mode Exit/Reset
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software reset command is ignored during an
internal Program or Erase operation. See Table 4 for software command codes, Figure 14 for timing waveform and
Figure 19 for a flowchart.
Concurrent Read and Write Operations
The SST32HF202/402 provide the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the Flash. This allows data alteration code to be executed from SRAM, while altering the
data in Flash. The following table lists all valid states.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and
VSS, e.g., less than 1 cm away from the VDD pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm of
the VDD pin.
CONCURRENT READ/WRITE STATE TABLE
Flash
Program/Erase
Program/Erase
Address
SRAM
Read
Write
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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
AMS-A0
UBS#
LBS#
BES#
BEF#
OE#
WE#
SRAM
Control Logic
DQ15 - DQ8
DQ7 - DQ0
I/O Buffers
Address Buffers
& Latches
SuperFlash
Memory
5
4
3
2
TOP VIEW (balls facing down)
SST32HF202
SST32HF402
A13
A9
WE#
BES#
A7
A12
A8
NC
NC
NC
A14
A10
LBS#
NC
A6
A15
A11
NC
NC
A5
6
A16 USB# DQ15 VSS
5
DQ7 DQ14 DQ13 DQ6
DQ5 DQ12 VDD DQ4
DQ2 DQ10 DQ11 DQ3
DQ0 DQ8 DQ9 DQ1
1
A3
A4
A2
A1
A0
A
B
C
D
E
BEF# OE# VSS
F
G
A13
A12
A14
A15
A16 USB# DQ15 VSS
A9
A8
A10
A11
DQ7 DQ14 DQ13 DQ6
WE#
NC
LBS#
NC
DQ5 DQ12 VDD DQ4
BES#
NC
NC
NC
DQ2 DQ10 DQ11 DQ3
A7
A17
A6
A5
DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0
A
B
C
D
E
4
3
557 48-lfbga L3K P1a.1
6
TOP VIEW (balls facing down)
2
1
H
BEF# OE# VSS
F
G
557 48-lfbga L3K P1b.1
557 ILL B1.0
H
FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LFBGA
©2002 Silicon Storage Technology, Inc.
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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide flash addresses, A16-A0 for 2M and A17-A0 for 4M.
To provide SRAM addresses, A16-A0 for 2M.
DQ15-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE# or BES# and BEF# are high.
BES#
SRAM Memory Bank Enable
To activate the SRAM memory bank when BES# is low.
BEF#
Flash Memory Bank Enable
To activate the Flash memory bank when BEF# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
2.7-3.3V power supply
VDD
Power Supply
VSS
Ground
UBS#
Upper Byte Control (SRAM)
To enable DQ15-DQ8
LBS#
Lower Byte Control (SRAM)
To enable DQ7-DQ0
NC
No Connection
Unconnected Pins
T2.1 557
1. AMS = Most significant address
TABLE 3: OPERATION MODES SELECTION
Mode
BES#1 BEF#1 OE# WE# UBS# LBS#
DQ15 to DQ8
DQ7 to DQ0
Address
VIL
VIL
X2
X
X
X
X
X
X
Read
VIH
VIL
VIL
VIH
X
X
DOUT
DOUT
AIN
Program
VIH
VIL
VIH
VIL
X
X
DIN
DIN
AIN
X
VIL
VIH
VIL
X
X
X
X
Sector or Block address,
XXH for Chip-Erase
VIL
VIH
VIL
VIH
VIL
VIL
DOUT
DOUT
AIN
VIL
VIH
VIL
VIH
VIL
VIH
DOUT
High Z
AIN
VIL
VIH
VIL
VIH
VIH
VIL
High Z
DOUT
AIN
VIL
VIH
X
VIL
VIL
VIL
DIN
DIN
AIN
VIL
VIH
X
VIL
VIL
VIH
DIN
High Z
AIN
VIL
VIH
X
VIL
VIH
VIL
High Z
DIN
AIN
VIHC
VIHC
X
X
X
X
High Z
High Z
X
X
X
VIL
X
X
X
Not Allowed
Flash
Erase
SRAM
Read
Write
Standby
Flash Write Inhibit
Output Disable
High Z / DOUT High Z / DOUT
X
X
X
X
VIH
X
X
High Z / DOUT High Z / DOUT
X
X
VIH
X
X
X
X
High Z / DOUT High Z / DOUT
X
VIH
VIL
VIH
VIH
X
X
High Z
High Z
X
VIL
VIH
X
X
VIH
VIH
High Z
High Z
X
VIL
VIH
VIH
VIH
X
X
High Z
High Z
X
VIH
VIL
VIL
VIH
X
X
Product Identification
Software Mode
Manufacturer’s ID (00BFH)
Device ID3
AMSF4-A1=VIL, A0=VIH
(See Table 4)
T3.3 557
1.
2.
3.
4.
Do not apply BES#=VIL and BEF#=VIL at the same time
X can be VIL or VIH, but no other value.
Device ID for: SST32HF202 = 2789H and SST32HF402 = 2780H
AMS = Most significant flash address
©2002 Silicon Storage Technology, Inc.
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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
Addr1
Data
2nd Bus
Write Cycle
Addr1
Data
3rd Bus
Write Cycle
Addr1
4th Bus
Write Cycle
Data
Addr1
Data
Data
AAH
Word-Program
5555H
AAH
2AAAH
55H
5555H
A0H
WA2
Sector-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
Data
Addr1
Data
2AAAH
55H
SAX3
30H
50H
10H
Block-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
BAX3
Chip-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
2AAAH
55H
5555H
90H
2AAAH
55H
5555H
F0H
Entry4,5
5555H
AAH
Software ID Exit
XXH
F0H
Software ID Exit
5555H
AAH
Software ID
T4.2 557
1. Address format A14-A0 (Hex),Address A15 can be VIL or VIH, but no other value, for the Command sequence.
2. WA = Program Word address
3. SAX for Sector-Erase; uses AMS-A11 address lines
BAX for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A16 for SST32HF202 and A17 for SST32HF402
4. The device does not remain in Software Product ID mode if powered down.
5. With AMS-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,
SST32HF202 Device ID = 2789H, is read with A0 = 1,
SST32HF402 Device ID = 2780H, is read with A0 = 1.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Commercial
Extended
AC CONDITIONS
Ambient Temp
OF
TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
VDD
0°C to +70°C
2.7-3.3V
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
-20°C to +85°C
2.7-3.3V
See Figures 15 and 16
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
7
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
TABLE 5: DC OPERATING CHARACTERISTICS (VDD = VDDF
AND
VDDS = 2.7-3.3V)
Limits
Symbol
Parameter
IDD
Power Supply Current
Min
Max
Units
Test Conditions
Address input=VIL/VIH, at f=1/TRC Min,
VDD=VDD Max, all DQs open
Read
Flash
20
SRAM
mA
OE#=VIL, WE#=VIH
BEF#=VIL, BES#=VIH
20
mA
BEF#=VIH, BES#=VIL
Concurrent Operation
45
mA
BEF#=VIH, BES#=VIL
Write
Flash
25
mA
WE#=VIL
BEF#=VIL, BES#=VIH, OE#=VIH
20
mA
BEF#=VIH, BES#=VIL
SRAM
ISB
Standby VDD Current
30
µA
VDD=VDD Max, BEF#=BES#=VIHC
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
1
µA
VOUT=GND to VDD, VDD=VDD Max
0.8
V
VDD=VDD Min
ILO
Output Leakage Current
VIL
Input Low Voltage
VIH
Input High Voltage
0.7 VDD
V
VDD=VDD Max
VIHC
Input High Voltage (CMOS)
VDD-0.3
V
VDD=VDD Max
VOLF
Flash Output Low Voltage
VOHF
Flash Output High Voltage
VOLS
Output Low Voltage
VOHS
Output High Voltage
0.2
VDD-0.2
0.4
2.2
V
IOL=100 µA, VDD=VDD Min
V
IOH=-100 µA, VDD=VDD Min
V
IOL=1 mA, VDD=VDD Min
V
IOH=-500 µA, VDD=VDD Min
T5.1 557
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
TPU-READ
Parameter
1
TPU-WRITE1
Minimum
Units
Power-up to Read Operation
100
µs
Power-up to Program/Erase Operation
100
µs
T6.0 557
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE
(Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
CI/O1
I/O Pin Capacitance
VI/O = 0V
24 pF
Input Capacitance
VIN = 0V
12 pF
CIN
1
T7.0 557
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: FLASH RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
Test Method
NEND1
Endurance
10,000
Cycles
JEDEC Standard A117
TDR1
Data Retention
100
Years
JEDEC Standard A103
ILTH1
Latch Up
100 + IDD
mA
JEDEC Standard 78
T8.0 557
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
8
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
AC CHARACTERISTICS
TABLE 9: SRAM READ CYCLE TIMING PARAMETERS
Symbol
Parameter
SST32HF202/402-70
SST32HF202/402-90
Min
Min
Max
TRCS
Read Cycle Time
Address Access Time
TBES
Bank Enable Access Time
70
90
ns
TOES
Output Enable Access Time
35
45
ns
TBYES
UBS#, LBS# Access Time
90
ns
TBLZS1
BES# to Active Output
0
0
ns
Output Enable to Active Output
0
0
ns
UBS#, LBS# to Active Output
0
0
ns
TOLZS
TBYLZS1
TBHZS
1
TOHZS1
90
Units
TAAS
1
70
Max
70
70
BES# to High-Z Output
Output Disable to High-Z Output
TBYHZS1
UBS#, LBS# to High-Z Output
TOHS
Output Hold from Address Change
25
0
25
0
35
10
ns
90
ns
35
ns
35
ns
45
10
ns
ns
T9.1 557
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: SRAM WRITE CYCLE TIMING PARAMETERS
SST32HF202/402-70
SST32HF202/402-90
Symbol
Parameter
Min
Min
Max
Max
Units
TWCS
Write Cycle Time
70
90
ns
TBWS
Bank Enable to End-of-Write
60
80
ns
TAWS
Address Valid to End-of-Write
60
80
ns
TASTS
Address Set-up Time
0
0
ns
TWPS
Write Pulse Width
60
80
ns
TWRS
Write Recovery Time
0
0
ns
TBYWS
UBS#, LBS# to End-of-Write
60
TODWS
Output Disable from WE# Low
TOEWS
Output Enable from WE# High
0
0
ns
TDSS
Data Set-up Time
30
40
ns
TDHS
Data Hold from Write Time
0
0
80
30
ns
40
ns
ns
T10.1 557
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
9
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
TABLE 11: FLASH READ CYCLE TIMING PARAMETERS
SST32HF202/402-70
SST32HF202/402-90
Min
Min
Symbol
Parameter
TRC
Read Cycle Time
Max
TBE
Bank Enable Access Time
70
90
ns
TAA
Address Access Time
70
90
ns
TOE
Output Enable Access Time
45
ns
TBLZ1
BEF# Low to Active Output
0
TOLZ1
TBHZ1
TOHZ1
TOH1
OE# Low to Active Output
0
70
35
ns
0
20
OE# High to High-Z Output
20
0
Units
ns
0
BEF# High to High-Z Output
Output Hold from Address Change
Max
90
ns
30
ns
30
ns
0
ns
T11.1 557
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
Parameter
TBP
Word-Program Time
Min
Max
Units
20
µs
TAS
Address Setup Time
0
ns
TAH
Address Hold Time
30
ns
TBS
WE# and BEF# Setup Time
0
ns
TBH
WE# and BEF# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
10
ns
TBPW
BEF# Pulse Width
40
ns
TWP
WE# Pulse Width
40
ns
TWPH
WE# Pulse Width High
30
ns
TBPH
BEF# Pulse Width High
30
ns
TDS
Data Setup Time
30
ns
TDH
Data Hold Time
0
ns
TIDA
Software ID Access and Exit Time
150
ns
TSE
Sector-Erase
25
ms
TBE
Block-Erase
25
ms
TSCE
Chip-Erase
100
ms
T12.0 557
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
10
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
TRCS
ADDRESSES AMSS-0
TOHS
TAAS
TBES
BES#
TBLZS
TBHZS
TOES
OE#
TOLZS
TOHZS
TBYES
UBS#, LBS#
TBYLZS
TBYHZS
DATA VALID
DQ15-0
557 ILL F02.0
Note: WE# remains High (VIH) for the Read cycle
AMSS = Most Significant SRAM Address
FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM
TWCS
ADDRESSES AMSS-0
TASTS
TWPS
TWRS
WE#
TAWS
TBWS
BES#
TBYWS
UBS#, LBS#
TODWS
DQ15-8, DQ7-0
TDSS
TOEWS
TDHS
VALID DATA IN
NOTE 2
NOTE 2
557 ILL F03.1
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance.
If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
11
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
TWCS
ADDRESSES AMSS-0
TWPS
TWRS
WE#
TBWS
BES#
TAWS
TASTS
TBYWS
UBS#, LBS#
TDSS
DQ15-8, DQ7-0
NOTE 2
TDHS
VALID DATA IN
NOTE 2
557 ILL F04.0
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
TAA
TRC
ADDRESSES AMSF-0
TBE
BEF#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
DQ15-0
HIGH-Z
TBLZ
TOH
DATA VALID
TBHZ
HIGH-Z
DATA VALID
557 ILL F05.0
AMSF = Most Significant Flash Address
FIGURE 5: FLASH READ CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
12
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
TAH
ADDRESSES AMSF-0
2AAA
5555
ADDR
TDH
TWP
WE#
TAS
TDS
TWPH
OE#
TCH
BEF#
TCS
DQ15-0
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
557 ILL F06.0
AMSF = Most Significant Flash Address
Note: X can be VIL or VIH, but no other value
FIGURE 6: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
TAH
ADDRESSES AMSF-0
2AAA
5555
ADDR
TDH
TCP
BEF#
TAS
TDS
TCPH
OE#
TCH
WE#
TCS
DQ15-0
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
AMSF = Most Significant Flash Address
Note: X can be VIL or VIH, but no other value
557 ILL F07.0
FIGURE 7: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
13
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
ADDRESSES AMSF-0
TCE
BEF#
TOES
TOEH
OE#
TOE
WE#
DQ7
Data
Data#
Data#
Data
557 ILL F08.0
AMSF = Most Significant Flash Address
FIGURE 8: FLASH DATA# POLLING TIMING DIAGRAM
ADDRESSES AMSF-0
TBE
BEF#
TOEH
TOES
TOE
OE#
WE#
DQ6
TWO READ CYCLES
WITH SAME OUTPUTS
AMSF = Most Significant Flash Address
557 ILL F09.0
FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
14
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
TSCE
SIX-BYTE CODE FOR CHIP-ERASE
ADDRESS AMSF-0
5555
2AAA
5555
5555
2AAA
5555
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
SW0
SW1
SW2
SW3
SW4
SW5
557 ILL F10.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 12)
X can be VIL or VIH, but no other value
AMSF = Most Significant Flash Address
FIGURE 10: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM
TSE
SIX-WORD CODE FOR SECTOR-ERASE
ADDRESSES AMSF-0
5555
2AAA
5555
5555
2AAA
SAX
BEF#
OE#
TWP
WE#
DQ15-0
XXAA
SW0
XX55
SW1
XX80
XXAA
XX55
XX30
SW2
SW3
SW4
SW5
557 ILL F11.0
Note:
The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See Table 12)
X can be VIL or VIH, but no other value
SAX = Sector Address
AMSF = Most Significant Flash Address
FIGURE 11: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
15
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
TBE
SIX-WORD CODE FOR BLOCK-ERASE
5555
ADDRESSES AMSF-0
2AAA
5555
5555
2AAA
BAX
BEF#
OE#
TWP
WE#
DQ15-0
Note:
XXAA
XX55
XX80
XXAA
XX55
XX50
SW0
SW1
SW2
SW3
SW4
SW5
557 ILL F12.1
The device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See Table 12)
X can be VIL or VIH, but no other value
BAX = Block Address
AMSF = Most Significant Flash Address
FIGURE 12: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM
THREE-WORD SEQUENCE FOR
SOFTWARE ID ENTRY
5555
ADDRESS A14-0
2AAA
5555
0000
0001
BEF#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX90
00BF
SW0
SW1
SW2
MFG ID
557 ILL F13.2
Note: X can be VIL or VIH, but no other value
Device ID = 2789H for SST32HF202 and
2780H for SST32HF402
FIGURE 13: SOFTWARE ID ENTRY
AND
DEVICE ID
READ
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
16
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
THREE-WORD SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
ADDRESS A14-0
DQ15-0
XXAA
2AAA
5555
XX55
XXF0
TIDA
BEF#
OE#
TWP
WE#
T WHP
SW0
SW1
SW2
557 ILL F14.0
Note:
X can be VIL or VIH, but no other value
FIGURE 14: SOFTWARE ID EXIT AND RESET
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
17
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
557 ILL F15.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 15: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
CL
557 ILL F16.0
FIGURE 16: A TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
18
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
Start
Write data: XXAAH
Address: 5555H
Write data: XX55H
Address: 2AAAH
Write data: XXA0H
Address: 5555H
Write Word
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
557 ILL F17.0
X can be V IL or V IH , but no other value.
FIGURE 17: WORD-PROGRAM ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
19
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read word
Read DQ7
Wait TBP,
TSCE, or TBE
Read same
word
Program/Erase
Completed
No
Is DQ7 =
true data?
Yes
No
Does DQ6
match?
Program/Erase
Completed
Yes
Program/Erase
Completed
557 ILL F18.0
FIGURE 18: WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
20
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Write data: XXAAH
Address: 5555H
Write data: XXAAH
Address: 5555H
Write data: XXF0H
Address: XXXXH
Write data: XX55H
Address: 2AAAH
Write data: XX55H
Address: 2AAAH
Wait TIDA
Write data: XX90H
Address: 5555H
Write data: XXF0H
Address: 5555H
Return to normal
operation
Wait TIDA
Wait TIDA
Read Software ID
Return to normal
operation
557 ILL F19.0
X can be V IL or V IH , but no other value.
FIGURE 19: SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
21
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
Chip-Erase
Command Sequence
Sector-Erase
Command Sequence
Block-Erase
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Address: SAX
Load data: XX50H
Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
557 ILL F20.0
X can be VIL or VIH, but no other value.
FIGURE 20: ERASE COMMAND SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
22
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
Concurrent
Operation
Load SDP
Command
Sequence
Flash
Program/Erase
Initiated
Wait for End of
Write Indication
Read or Write
SRAM
End
Wait
Flash Operation
Completed
End Concurrent
Operation
557 ILL F21.0
FIGURE 21: CONCURRENT OPERATION FLOWCHART
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
23
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
PRODUCT ORDERING INFORMATION
Device
SST32HFxxx
Speed
- XXX
Suffix1
-
XX
Suffix2
-
XXXX
Package Attribute
E = non-Pb
Package Modifier
K = 48 balls
Package Type
L3 = LFBGA (6mm x 8mm x 1.4mm)
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Density
202 = 2 Mbit Flash + 2 Mbit SRAM
402 = 4 Mbit Flash + 2 Mbit SRAM
Voltage
H = 2.7-3.3V
Device Family
32 = MPF + SRAM ComboMemory
Valid combinations for SST32HF202
SST32HF202-70-4C-L3K
SST32HF202-90-4C-L3K
SST32HF202-70-4C-L3KE
SST32HF202-90-4C-L3KE
SST32HF202-70-4E-L3K
SST32HF202-90-4E-L3K
SST32HF202-70-4E-L3KE
SST32HF202-90-4E-L3KE
Valid combinations for SST32HF402
SST32HF402-70-4C-L3K
SST32HF402-90-4C-L3K
SST32HF402-70-4C-L3KE
SST32HF402-90-4C-L3KE
SST32HF402-70-4E-L3K
SST32HF402-90-4E-L3K
SST32HF402-70-4E-L3KE
SST32HF402-90-4E-L3KE
Note:
Valid combinations are those products in mass production or will be in mass production. Consult your SST
sales representative to confirm availability of valid combinations and to determine availability of new combinations.
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
24
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
PACKAGING DIAGRAMS
BOTTOM VIEW
8.00 ± 0.20
TOP VIEW
5.60
0.45 ± 0.05
(48X)
0.80
6
6
5
5
4.00
4
4
6.00 ± 0.20
3
3
2
2
1
1
0.80
H G F E D C B A
A B C D E F G H
A1 CORNER
A1 CORNER
SIDE VIEW
1.30 ± 0.10
0.12
SEATING PLANE
48-lfbga-L3K-6x8-450mic-4
0.35 ± 0.05
1mm
Note:
1. Except for total height dimension, complies with JEDEC Publication 95, MO-210,
variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
48-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 6MM
SST PACKAGE CODE: L3K
©2002 Silicon Storage Technology, Inc.
X
8MM
S71209-02-000 4/02
25
557
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402
Data Sheet
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2002 Silicon Storage Technology, Inc.
S71209-02-000 4/02
26
557