3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS Precision Edge™ PROGRAMMABLE CLOCK DIVIDER/FANOUT SY89873L FINAL BUFFER W/ INTERNAL TERMINATION FEATURES ■ Guaranteed AC performance • > 2.0GHz FMAX output toggle • > 3.0GHz FMAX input • < 800ps Tpd (matched-delay between banks) • < 15ps within-device skew • < 190ps rise/fall time ■ Low jitter design • < 1ps (rms) cycle-to-cycle jitter • < 10ps (pk-pk) total jitter ■ Unique input termination and VT pin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL) ■ Precision differential LVDS outputs ■ Matched delay: all outputs have matched delay, independent of divider setting ■ TTL/CMOS inputs for select and reset/disable ■ Two LVDS output banks (matched delay) • Bank A: Buffered copy of input clock (undivided) • Bank B: Divided output (÷2, ÷4, ÷8, ÷16), two copies ■ 3.3V power supply ■ Wide operating temperature range: –40°C to +85°C ■ Available in 16-pin (3mm × 3mm) MLF™ package Precision Edge™ DESCRIPTION This 3.3V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC- or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89873L includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to all AC- or DC-coupled differential logic standards. A VREF-AC reference is included for AC-coupled applications. The SY89873L is part of Micrel’s high-speed Precision Edge™ timing and distribution family. For 2.5V applications, consider the SY89872U. For applications that require an LVPECL output, consider the SY89871U. The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N). Refer to the Timing Diagram. APPLICATIONS ■ SONET/SDH line cards ■ Transponders ■ High-end, multiprocessor servers FUNCTIONAL BLOCK DIAGRAM TYPICAL APPLICATION Enable FF /RESET Enable MUX VREF-AC 622MHz/155.5MHz SONET Clock Generator QA /QA IN 50Ω 622MHz LVPECL IN Clock In /IN QB0 VT Divided by 2, 4, 8 or 16 50Ω /IN /QB0 QB1 OC-12 or OC-3 Clock Gen QA /QA 622MHz LVDS Clock Out QB 155.5MHz LVDS Clock Out /QB Bank B: 155.5MHz: For OC-3 line card Set to divide-by-4 /QB1 S0 Bank A: 622MHz: For OC-12 line card Set to pass-through Decoder S1 Precision Edge is a trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. Rev.: B 1 Amendment: /1 Issue Date: February 2003 Precision Edge™ SY89873L Micrel PACKAGE/ORDERING INFORMATION S0 S1 VCC GND Ordering Information 16 15 14 13 QB0 1 12 IN /QB0 2 11 QB1 /QB1 3 4 10 9 VT VREF-AC /IN Part Number Package Type Operating Range Package Marking SY89873LMI MLF-16 Industrial 873L SY89873LMITR* MLF-16 Industrial 873L *Tape and Reel QA /QA VCC /RESET, /DISABLE 5 6 7 8 16-Pin MLF™ PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 2, 3, 4 QB0, /QB0 QB1, /QB1 Differential Buffered Output Clocks: Divide by 2, 4, 8, 16. LVDS compatible. 5, 6 QA, /QA 7, 14 VCC 8 /RESET, /DISABLE 9, 12 IN, /IN 10 VREF-AC 11 VT 13 GND 15, 16 S0, S1 Differential Buffered Undivided Output Clock: LVDS compatible. Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors. TTL/CMOS Compatible Output Reset and Disable: Internal 25kΩ pull-up. Input threshold is VCC/2. Logic LOW will reset the divider select, and align Bank A and Bank B edges. In addition, when LOW, Banks A and B will be disabled. Differential Input: Internal 50Ω termination resistors to VT input. See “Input Interface Applications” section. Reference Voltage: Equal to VCC–1.4V (approx.), and used for AC-coupled applications. Maximum sink/source current is 0.5mA. See “Input Interface Applications” section. Termination Center-Tap: For CML and LVDS inputs, leave this pin floating. Otherwise, see “Input Interface Applications” section. Ground: Exposed pad is internally connected to GND and must be connected to a ground plane for proper thermal operation. Select Pins: LVTTL/CMOS logic levels. Internal 25kΩ pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is VCC/2. TRUTH TABLE /RESET /DISABLE S1 S0 Bank A Output Bank B Outputs 1 0 0 Input Clock Input Clock ÷ 2 1 0 1 Input Clock Input Clock ÷ 4 1 1 0 Input Clock Input Clock ÷ 8 1 1 1 Input Clock Input Clock ÷ 16 0 Note 1. Note 2. X X QA = LOW, /QA = On the next negative transition of the input signal. Asynchronous Reset/Disable function. See "Timing Diagram." 2 HIGH(1) QB0 = LOW, /QB0 = HIGH(2) QB1 = LOW, /QB1 = HIGH(2) Precision Edge™ SY89873L Micrel Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Supply Voltage (VCC) .................................. –0.5V to +4.0V Input Voltage (VIN) .................................. –0.5V to VCC+0.3 LVDS Output Current (IOUT) .................................... ±10mA Input Current IN, /IN (IIN) .......................................... ±50mA VREF-AC Input Sink/Source Current (IVREF-AC),Note 3 . ±2mA Lead Temperature (soldering, 10 sec.) ..................... 220°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage (VCC) ...................................... +3.3V ±10% Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance MLF™ (θJA) Still-Air ............................................................. 60°C/W 500 lfpm ........................................................... 54°C/W MLF™ (ΨJB), Note 4 Junction-to-Board ............................................ 32°C/W Note 1. Note 2. Note 3. Note 4. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Due to the limited drive capability use for input of the same package only. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) TA= –40°C to +85°C; Unless otherwise stated. Symbol Parameter Min Typ Max Units VCC Power Supply 3.0 3.3 3.6 V ICC Power Supply Current 85 115 mA RIN Differential Input Resistance IN, /IN 100 120 Ω VIH Input High Voltage IN, /IN Note 2 0.1 VCC+0.3 V VIL Input Low Voltage IN, /IN Note 2 –0.3 VCC+0.2 V VIN Input Voltage Swing Notes 2, 3 0.1 3.6 V VDIFF_IN Differential Input Voltage Swing Notes 2, 3, 4 0.2 |IIN| Input Current IN, /IN Note 2 VREF-AC Reference Voltage Note 5 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Condition No load, Max VCC 80 V 45 VCC –1.525 VCC–1.425 VCC–1.325 The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. Due to the internal termination (see “Input Buffer Structure” ) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit! See “Timing Diagram” for VIN definition. VIN(MAX) is specified when VT is floating. See Figures 1c and 1d for VDIFF definition. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin. 3 mA V Precision Edge™ SY89873L Micrel LVDS OUTPUT DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 3.3V ±10%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOUT Output Voltage Swing Notes 3, 4 250 350 450 mV VOH Output High Voltage Note 3 1.475 V VOL Output Low Voltage Note 3 0.925 VOCM Output Common Mode Voltage Note 3 1.125 1.275 V ∆VOCM Change in Common Mode Voltage –50 50 mV Max Units Note 1. Note 2. Note 3. Note 4. V The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for package product only. Measured as per Figure 1a, 100Ω across Q and /Q outputs. See Figure 1c. LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 3.3V ±10%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current Note 1. Note 2. Condition Min Typ 2.0 V 0.8 V 20 µA –300 µA –125 The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for package product only. 4 Precision Edge™ SY89873L Micrel AC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 3.3V ±10%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Output Toggle Frequency (Bank A and Bank B) Output Swing: ≥ 200mV 2.0 GHz Maximum Input Frequency Note 3 3.2 GHz Differential Propagation Delay (IN-to-Q) Input Swing < 400mV 550 660 800 ps Input Swing ≥ 400mV 500 610 750 ps Within-Device Skew (diff.) (QB0-to-QB1) Note 4 7 15 ps Within-Device Skew (diff.) (Bank A-to-Bank B) Note 4 12 30 ps Part-to-Part Skew (diff.) Note 4 250 ps trr Reset Recovery Time Note 5 Tjitter Cycle-to-Cycle Jitter Note 6 1 ps(rms) Total Jitter Note 7 10 ps(pk-pk) 190 ps tPD tSKEW tr, tf Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Typ Max 600 Rise / Fall Time (20% to 80%) 60 Units ps 110 Measured with 400mV input signal, 50% duty cycle. All outputs terminated with 100Ω between Q and /Q, unless otherwise stated. Specification for package product only. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output ÷2, ÷4, ÷8, ÷16) can accept an input frequency >3GHz, while Bank A will be slew rate limited. Skew is measured between outputs under identical transitions. See “Timing Diagram.” Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc=Tn–Tn+1, where T is the time between rising edges of the output signal. Total jitter definition: with an ideal clock input, of frequency ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. 5 Precision Edge™ SY89873L Micrel LVDS OUTPUT 50Ω ±1% VOUT 100Ω ±1% 50Ω ±1% VOH, VOL VOH, VOL GND VOCM, ∆VOCM GND Figure 1a. LVDS Differential Measurement Figure 1b. LVDS Common Mode Measurement DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING VDIFF_IN, VDIFF_OUT 700mV (Typical) VIN, VOUT 350mV (Typical) Figure 1d. Differential Swing Figure 1c. Single-Ended Swing TIMING DIAGRAM /RESET VCC/2 tRR IN /IN VIN (Swing) tPD QB VOUT (Swing) /QB QA /QA 6 Precision Edge™ SY89873L Micrel TYPICAL OPERATING CHARACTERISTICS VCC = 3.3V, VIN = 400mV, TA = 25°C, unless otherwise stated. Output Amplitude vs. Frequency Nominal Propagation Delay vs. Input Swing PROPAGATION DELAY (ps) 800 300 250 200 150 100 50 0 0 700 600 500 400 500 1000 1500 2000 2500 FREQUENCY (MHz) Nominal Propagation Delay vs. Temperature 800 PROPAGATION DELAY (ps) QA AMPLITUDE (mV) 350 700 600 500 400 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) 7 0 200 400 600 800 1000 1200 INPUT SWING (mV) Precision Edge™ SY89873L Micrel FUNCTIONAL CHARACTERISTICS Conditions: VCC = 3.3V, TA = 25°C, unless otherwise stated. QA Output @ 1.25GHz QA @ 622MHz and QB @ 155.5MHz (Divided-by-4) Output Swing (50mV/div.) /QA 622MHz QB ÷4 /QB 155MHz TIME (100ps/div.) TIME (1ns/div.) QA Output @ 2.0GHz Q Output Swing (50mV/div.) Output Swing (100mV/div.) QA /Q TIME (100ps/div.) 8 Precision Edge™ SY89873L Micrel INPUT BUFFER STRUCTURE VCC 1.86kΩ VCC 1.86kΩ 25kΩ R S0 S1 /RESET 1.86kΩ 1.86kΩ R IN 50Ω VT 50Ω GND GND /IN Figure 2a. Simplified Differential Input Stage Figure 2b. Simplified TTL/CMOS Input 9 Precision Edge™ SY89873L Micrel INPUT INTERFACE APPLICATIONS VCC = 3.3V VCC = 3.3V VCC = 3.3V VCC = 3.3V VCC = 3.3V IN IN IN LVPECL CML CML VCC = 3.3V /IN /IN /IN SY89873L SY89873L SY89873L GND VCC–2V* VT GND GND VCC NC VT NC VREF-AC VT .01µF VREF-AC 0.01µF Figure 3a. DC-Coupled CML Input Interface VCC = 3.3V VCC = 3.3V Figure 3c. DC-Coupled LVPECL Input Interface VCC = 3.3V IN IN LVPECL LVDS /IN 100Ω GND /IN SY89873L 100Ω VCC GND VREF-AC * Bypass with 0.01µF to GND Figure 3b. AC-Coupled CML Input Interface VCC = 3.3V 50Ω NC VT VREF-AC SY89873L GND NC VT NC VREF-AC 0.01µF Figure 3d. AC-Coupled LVPECL Input Interface Figure 3e. LVDS Input Interface Figure 3f. HSTL Input Interface RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY89871U 2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/Fanout Buffer w/Internal Termination www.micrel.com/product-info/products/sy89871u.shtml SY89872U 2.5V 2GHz Any Diff. In-to-LVDS Programmable Clock Divider/Fanout Buffer w/Internal Termination www.micrel.com/product-info/products/sy89872u.shtml HBW Solutions MLF™ Application Note www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf New Products and Applications www.micrel.com/product-info/products/solutions.shtml 10 Precision Edge™ SY89873L Micrel 16 LEAD MicroLeadFrame™ (MLF-16) 0.42 +0.18 –0.18 0.23 +0.07 –0.05 0.85 +0.15 –0.65 0.01 +0.04 –0.01 3.00BSC 1.60 +0.10 –0.10 0.65 +0.15 –0.65 0.42 0.20 REF. 2.75BSC PIN 1 ID +0.18 –0.18 N 16 1 1 0.50 DIA 2 2 2.75BSC 3.00BSC 3 3 1.60 +0.10 –0.10 4 4 12° max 0.5 BSC 0.42 +0.18 –0.18 SEATING PLANE 1.5 REF BOTTOM VIEW TOP VIEW CC 0.23 +0.07 –0.05 CL 4 0.01 +0.04 –0.01 SECTION "C-C" SCALE: NONE 0.5BSC 0.40 +0.05 –0.05 1. 2. 3. 4. DIMENSIONS ARE IN mm. DIE THICKNESS ALLOWABLE IS 0.305mm MAX. PACKAGE WARPAGE MAX 0.05mm. THIS DIMENSION APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.20mm AND 0.25mm FROM TIP. 5. APPLIES ONLY FOR TERMINALS FOR EVEN TERMINAL/SIDE Rev. 02 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 16-Pin MLF™ Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: Note 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. Note 2. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. TEL 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. 11 Precision Edge™ SY89873L Micrel MICREL, INC. 1849 FORTUNE DRIVE TEL + 1 (408) 944-0800 FAX SAN JOSE, CA 95131 USA + 1 (408) 944-0970 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel, Inc. © 2002 Micrel, Incorporated. 12