SAMSUNG BL8531H

BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
GENERAL DESCRIPTION
The samsung analog front end(AFE) for CCD/CIS image signal is an integrated analog signal processor for color
image signal.
The AFE converts CCD/CIS output signal to digital data. The AFE includes three-channel CDS(Correlated
Double Sampling) circuit, PGA(Programmable Gain Amplifier), and 12-bit analog to digital converter with
reference generator.
A parallel data bus provides a simple interface to 8-bit microcontroller.
APPLICATIONS
•
Color and B/W Scanner
•
Digital Copiers
•
Facsimile
•
General Purpose CCD/CIS imager
FETURES
•
12-bit 6MSPS A/D Converter
•
Integrated Triple Correlated Double Sampler
•
3-Channel 2 MSPS Color Mode
•
Analog Programmble Gain Amplifier
•
Internal Voltage Reference
•
Wide clamp level controllability for CIS sensor
•
No Missing Code Guaranteed
•
Microcontroller-Compatible Control Interface
•
Operation by Single 5V Supply
•
CMOS Low Power Dissipation
KEY SPECIFICATION
•
Resolution: 12-bit
•
Conversion Rate: 6 MHz(2 MHz*3)
•
Supply Voltage: 5 V ± 5%
•
Power Dissipation: 375 mW(Typical)
1
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
FUNCTIONAL BLOCK DIAGRAM
RED
CDS
PGA
REF
GREEN
INPUT OFFSET
REGISTER
D[11:0]
CDS
PGA
MUX
ADC
MPU
PORT
BLUE
CDS
PGA
GAIN
REGISTER
Ver 2.0 (Apr. 2002)
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties
that may result from its use. The content of this datasheet is subject to change without any notice.
2
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
CORE PIN DESCRIPTION
Name
I/O Type
I/O Pad
Pin Description
VDDA1
AP
vdda
5 V Analog Supply
VSSA1
AG
vssa
Analog Ground
VDDA2
AP
vdda
5 V Analog Supply(for ADC)
VSSA2
AG
vssa
Analog Ground(for ADC)
VBB
AG
vbba
Substarte Ground
VDDD
DP
vddd
5 V Digital Supply
VSSD
DG
vssd
Digital Ground
REFT
AB
piar50_bb
Reference Decoupling
REFB
AB
piar50_bb
Reference Decoupling
VCOM
AB
piar50_bb
Analog Common Voltage
BGR
AB
piar50_bb
Bandgap Refernce Voltage
R_VIN
AI
piar10_bb
Analog Input; Red
G_VIN
AI
piar10_bb
Analog Input; Green
B_VIN
AI
piar10_bb
Analog Input; Blue
STRTLN
DI
picc_bb
STRTLN indicates beginning of line
CDS1_CLK
DI
picc_bb
CDS Reset Clock Pulse Input
CDS2_CLK
DI
picc_bb
CDS Data Clock Pulse Input
ADCCLK
DI
picc_bb
A/D Converter Sample Clock Input
CSB
DI
picc_bb
Chip Select; Active Low
WRB
DI
picc_bb
Write Strobe; Active Low
RDB
DI
picc_bb
Read Strobe; Active Low
OEB
DI
picc_bb
Output Enable; Active Low
D[11:0]/MPU[7:0]
DB
pia_bb
Data Inputs/Outputs
AD[2:0]
DI
picc_bb
Register Select
MCTL1, MCTL2
DI
picc_bb
Channel Select in External MUX Control
EXT_MCTL
DI
picc_bb
External MUX Control; Active Low
I/O TYPE ABBR.
•
AI : Analog Input
• DI : Digital Input
•
AO : Analog Output
• DO : Analog Output
•
AP : Analog Power
•
DP : Digital Power
•
AB : Analog Bidirectional Port • DB : Digital Bidirectional Port
• AG : Analog Ground
• DG : Digital Ground
3
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
CORE PIN CONFIGURATION
BGR
REFT
VCOM REFB
VSSA2
VDDA2
VSSA1
VDDA1
EXT_MCTL
MCTL1,MCTL2
R_VIN
D[11:0]/MPU[7:0]
G_VIN
bl8531h
AD[2:0]
B_VIN
CSB
WRB
VDDD
RDB
OEB
VSSD
VBB
STRTLN
ADCCLK
CDS1_CLK CDS2_CLK
ABSOLUTE MAXIMUM RATINGS
Charateritics
Symbol
Value
Units
Supply Voltage
VDD
6.5
V
Analog Input Voltage
AIN
VSS to VDD
V
Digital Input Voltage
CLK
VSS to VDD
V
VOH, VOL
VSS to VDD
V
VRT/VRB
VSS to VDD
V
Storage Temperature Range
Tstg
-45 to 150
°C
Operating Temperature Range
Topr
0 to 70
°C
Digital Output Voltage
Reference Voltage
NOTES:
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to
ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with
the other values kept within the following operating conditions and function operation under any of these conditions is not
implied.
2. All voltages are measured with respect to VSS unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model)
4
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
ANALOG SPECIFICATIONS
(VDDA = 5V, VDDD = 5V, ADCCLK = 6MHz, CDS1_CLK = 2MHz, CDS2_CLK = 2MHz, PGA Gain = 1
unless otherwise noted)
Characteristics
Symbol
Resolution
Signal-to-Noise & Distortion Ratio
Min
Typ
Max
12
SNDR
Unit
Comment
Bits
60
dB
6
6
MSPS
MSPS
Conversion Rate
3-Channel with CDS
1-Channel with CDS
Differential Nonlinearity
DNL
±1
LSB
Integral Nonlinearity
INL
±2
LSB
Unipolar Offset Error
1.0
%FSR
Gain Error
2.0
%FSR
4.0
Vp-p
Pf
V
V
Anlog Input
Full-Scale Input
Input Capacitance
Reference Top
Reference Bottom
0.06
8
3.5
1.5
5V ±5%
Power Supply
Analog Voltage
Digital Voltage
Analog Current
Digital Current
VDDA
VDDD
IDDA
IDDD
Power Consumption
Temperature Range
0
5
5
65
10
V
V
mA
mA
375
mW
70
5V ±5%
°C
5
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
DIGITAL SPECIFICATIONS
(VDDA = 5V, VDDD = 5V, ADCCLK = 6MHz, CDS1_CLK = 2MHz, CDS2_CLK = 2MHz, CL = 20pF
unless otherwise noted)
Characteristics
6
Symbol
Min
High Level Input Voltage
VIH
3.0
Low Level Input Voltage
VIL
High Level Input Current
IIH
10
mA
Low Level Input Current
IIL
10
mA
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
Typ
Max
Unit
Comment
V
0.8
4.5
0.5
V
V
IOH = 0.5mA
V
IOL = -0.5mA
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
TIMING SPECIFICATIONS
(VDDA = 5V, VDDD = 5V unless otherwise noted)
Characteristics
Symbol
Min
Typ
Max
Unit
3-Channel Conversion Rate
500
ns
1-Channel Conversion Rate
166
ns
CDSCLK1 Pulse Width
tC1CLK
60
ns
CDSCLK2 Pulse Width
tC2CLK
70
ns
CDSCLK2B Pulse Width
tC2CLKB
70
ns
CDSCLK1 Falling to CDSCLK2 Rising
tC1C2A
5
ns
CDSCLK2 Falling to CDSCLK1 Rising
tC2C1A
5
ns
ADCCLK Pulse Width
tADCLK
70
ns
CDSCLK2 Rising to ADCCLK Rising
tC2ADA
70
ns
CDSCLK2 Falling to ADCCLK Falling
tC2ADB
5
ns
ADCCLK Rising to CDS2CLK Falling
tADC2A
5
ns
STRTLN Rising, Falling Setup & Hold
tS, tH
15
ns
ADC Output Delay
tADDT
20
ns
Register Address Setup Time
tAS
15
ns
Register Address Hold Time
tAH
15
ns
Data Hold Time
tDH
15
ns
Register Chip Select Setup Time
tCSS
15
ns
Register Chip Select Hold Time
tCSH
15
ns
Register Read Pulse Width
tPWR
50
ns
Write Pulse Width
tPWW
25
ns
Register Read To Data Valid
tDD
40
ns
Output Enable High to Tri-State
tHZ
10
ns
Tri-State to Data Valid
tDEV
15
ns
Aperture Delay
tAD
2
ns
Latency for 1 Channel mode
4
ADCCL
K Cycles
* Aperture delay is a timing measurement between the sampling clocks and CDS. It is measured from the falling
edge of the CDS2_CLK input to when the input signal is held for data conversion
7
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
TIMING DIAGRAM
3-Channel CDS Mode
Analog
Input
R0,G0,B0
R1,G1,B1
R2,G2,B2
tC2C1A
tC1C2A
tC1CLK
CDS1_CLK
tC2ADA
tC2CLKB
tADC2A
CDS2_CLK
tADCLK
ADCCLK
tH
STRTLN
tS
3-Channel SHA Mode
Analog
Input
R0,G0,B0
R1,G1,B1
tADC2A
tC2ADA
R2,G2,B2
tC2CLKB
CDS2_CLK
tADCLK
ADCCLK
tH
STRTLN
tS
8
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
1-Channel CDS Mode
Analog
Input
tC1C2A
tC1CLK
tC2C1A
CDS1_CLK
tC2CLK
CDS2_CLK
tC2ADA
tC2ADB
tADCLK
ADCCLK
9
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
TIMING DIGRAM
1-Channel SHA Mode
Analog
Input
R0,G0,B0
R1,G1,B1
R2,G2,B2
tC2CLK
CDS2_CLK
tC2ADA
tC2ADB
tADCLK
ADCCLK
ADC Timing
ADC Input
A(n+1)
A(n)
ADCCLK
tADDT
ADCOUT
10
A(n-3)[11:0]
A(n-2)[11:0]
A(n-1)[11:0]
A(n)[11:0]
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
Write Timing
OEB
CSB
tAS
tAH
AD[2:0]
tCSH
tCSS
WRB
tPWW
tDH
tDD
MPU[7:0]
11
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
TIMING DIGRAM
Read (1) Timing
CSB
tAS
tAH
AD[2:0]
tCSS
tPWR
tCSH
RDB
tDH
tDD
MPU[7:0]
'Read(1)' means microcontroller reads MPU[7:0]
CSB should keep 'High' to read.
Read (2) Timing
ADCCLK
tADDT
D[11:0]
tHZ
OEB
12
tDEV
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
FUNCTIONAL DESCRIPTION
1) 3-Channel Operation with CDS
This mode enables simultaneous sampling of a triple output CCD. The CCD waveforms are ac coupled to the
VINR, VING and VINB pins where they are automatically biased at an appropriate voltage using the on-chip
clamp. The internal CDSs take two samples of the incoming pixel data; the first samples are taken during the
reset time while the second samples are taken during data portion of the input pixels. When STRTLN is low, the
internal circuitry is reset on the next rising edge of ADCCLK; the multiplexer is switched to red channel.
2) 3-Channel SHA Operation
This mode enables simultaneous sampling of a triple output CIS or something like that. The CDS functions are
replaced with the sample and hold amplifiers. The input waveforms are either dc coupled or dc restored to
the VINR, VING and VINB pins. The input reference voltage in this mode will be defined by clamp level control
register.
When STRTLN is low, the internal circuitry is reset on the next rising edge of ADCCLK; the multiplexer is
switched to red channel.
3) 1-Channel Operation with CDS
This mode enables single channel or monochrome sampling. The CCD waveforms are ac coupled to the analog
input pin where they are automatically biased at an appropriate voltage using the on-chip clamp.
Bit2 and bit3 in configuration register select the desired input among red, green and blue.
4) 1-Channel SHA Operation
This mode enables single-channel or monochrome sampling. The CDS function is replaced with the sample and
hold amplifier.
The input waveforms are either dc coupled or dc restored to the analog input pin. The input reference voltage in
this mode will be defined by clamp level control register.
Bit2 and bit2 in configuration register select the desired input among red, green and blue.
13
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
MAIN BLOCK DESCRIPTION
1) Programmable Gain Amplifier
The analog programmable gain can accommodate a wide range of input voltage spans. The transfer function
of the PGA is as follows.
H(X) = 1/6*X + 5/6,
where the range of X is 0 to 31.
Thus, the minimum gain value is equal to 5/6, and the maximum gain value is equal to 6. The transfer function
has linearity in linear scale. The overall gain is equal to analog gain multiplied by digital gain. So, the
multiplier should be required in back end of AFE.
16
6
14
5
GAIN [dB]
10
4
8
3
6
4
2
GAIN [Liner]
12
2
1
30
28
26
24
22
20
18
16
14
12
8
6
4
2
0
-2
10
0
0
PGA Gain Setting
There is a gain boosting block before 12-bit ADC, which can muliply PGA's output signal by 1.5 (3.5dB) or pass it.
This is controled by gain mode of configuration register.
14
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
BLOCK DIAGRAM
VDDA1 VSSA1
VDDA2
VSSA2
VDDD
VSSD
VBB
BGR
REFT VCOM
REFB
MCTL2
RED
MCTL1
R_VIN
CDS
PGA
EXT_MCTL
CLAMP
R_OFFSET[7:0]
R_CLAMP[3:0]; For only SHA mode
R_GAIN[4:0]
REF
GREEN
G_VIN
CDS
MUX
&
G1.5
PGA
CLAMP
12
ADC
12
8
G_OFFSET[7:0]
G_CLAMP[3:0]; For only SHA mode
G_GAIN[4:0]
D[11:0]
/MPU[7:0]
GAIN
MODE
BLUE
B_VIN
CDS
CLAMP
PGA
R_OFFSET[7:0]
B_OFFSET[7:0]
B_CLAMP[3:0]; For only SHA mode
B_GAIN[4:0]
CSB
Configuration
Register
OEB
RDB
R_OFFSET[7:0]
G_OFFSET[7:0]
B_OFFSET[7:0]
Input Offset
Register
(R,G,B)
8
MPU
PORT
WRB
AD[2]
AD[1]
R_CLAMP[3:0], R_GAIN[4:0]
G_CLAMP[3:0], G_GAIN[4:0]
B_CLAMP[3:0], B_GAIN[4:0]
CDS1_CLK
CDS2_CLK
STRTLN
Gain & Clamp
Level Register
(R,G,B)
AD[0]
ADCCLK
15
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
Table: MPU Port Map Format
A2
A1
A0
Register
0
0
0
Configuration Register
0
0
1
Input Offset register
0
1
0
PGA Gain Control Register
0
1
1
CIS Clamp Control Register
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
2) Register Overview
The MPU port map is accessed through pins A0, A1 and A2. See MPU port map format.(previous page)
Configuration Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Clamp
mode
select1
Clamp
mode
select0
PGA Gain
External
Color1
Color0
Single
CDS
mode
Reference
Channel
Enable
Single Channel Color Pointer
Bit3
Bit2
Color
0
0
Red
0
1
Green
1
0
Blue
1
1
Reserved
Clamp Mode Selection
16
Bit7
Bit6
Clamp Mode
0
0
Line Clamp
0
1
Pixel Clamp
1
0
No Clamp
1
1
Reserved
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
Input Offset Register
MSB
Bit 7
LSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PGA Gain Control Register
MSB
LSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
PGA4
PGA3
PGA2
PGA1
PGA0
CIS Clamp Control Register
MSB
Bit 7
LSB
Bit 6
Bit 5
Reserved
Reserved
Reserved
* CCCn: CIS Clamp Control n
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
CCC3
CCC2
CCC1
CCC0
MULTIPLEXER CONTROL MODE
EXT_MCTL = "LOW"
MCTL2
MCTL1
Color
0
0
Red
0
1
Green
1
0
Blue
1
1
Reserved
17
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
OVERRALL TRANSFER FUNCTION
The overall transfer function can be calculated as follows.
if gain mode = 0,
ADCout = [(Vin+Input_Offset)* PGA_Gain]/(2*REF)*4096,
if gain mode = 1,
ADCout = [(Vin+Input_Offset)* PGA_Gain * 1.5]/(2*REF)*4096,
where REF is equal to (REFT-REFB) and Input _Offset means the DAC value of the input offset register. The
analog offset range of the input offset register is varied between 150mV and -150 mV. The 8-bit data format for
the input offset register is straight binary coding. Thus, an all 'zeros' data word corresponds to -150 mV. An all
'ones' data word corresponds to 150 mV.
To maximize the dynamic range of the ADC input, it is necessary to program the input offset register code to
move the ADC code corresponding to the black level towards 'zero'.
In case of processing CIS signal, 4-bit of the gain & clamp control register are allocated to control CIS clamp
level. Like the input offset register, the 4-bit data format is straight binary coding. An all 'zeros' data word
corresponds to 0.1 V and an all 'ones' data word corresponds to 1.5 V.
INPUT COUPLING CAPACITOR
Because of the DC offset present at the output of CCD, some kind of DC restoration is required. In case of
CDS enable mode, to simplify input level shifting, a DC decoupling capacitor is used in conjuction with the
internal input circuitry.
The capacitor charging or discharging depends on the clamping time, the analog input resistance of the AFE
and the output resistance of the circuit driving the coupling capacitor.
The clamping time is typically (n*T), where n is the number of periods CDSCLK1 is asserted and T is the period
of assertion. CDSCLK2 should not be asserted during clamping time. And, STRTLN must be low in line clamp
mode for clamping operation. The analog input resistance of the AFE is equal to 1 kΩ. The recommended input
coupling capacitor is more than 0.01uF. Thus, to extend the clamping time, the time a transport motor moves the
scanner carriage can be available, for example.
18
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
POWER-ON INITIALIZATION
Write to configuration register
Set CDS or SHA operation
Set 3 or 1 channel mode
Set color pointer
Set clamp mode
CALIBRATION
Decide clamp level for SHA mode
(Refer to next page)
Set PGA gain
(Input offset = 0mV)
Scan dark line
Compute pixel offsets
Write to PGA gain register
Set to gain of one(00001)
Set input offset
Write to input offset register
Set to 0mV(10000000)
Set odd/even offset in back end
YES
YES
Set another
color
Set another
color
NO
NO
Set gain/offset bus size
in back end
Set external pixel offset
in back end
Scan white line
Compute pixel gains
in back end
YES
Adjust PGA gain
NO
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AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
CLAMP LEVEL DECISION FOR EACH INPUT
*
Assume that PGA gain = 1
*
This flow chart is not fixed, but recommended.
User can modify this algorithm.
Write CIS clamp control register
Set to (111)
Decrease CIS clamp control
register by 1
Scan clamp level input
NO
[Repeatedly, scan clamp level.
Average ADC output]
ADC output > 0
YES
Scan dark line
[MIN(ADC output) = Minimum value of all pixels]
YES
MIN(ADC output)
> 204
NO
YES
[(100mV)/(4V) * 4096 - 1 = 102]
MIN(ADC output)
> 102
NO
MIN(ADC output)
>0
Increase CIS
clamp control
register by 1
NO
Decrease CIS
clamp control
register by 1
Scan dark line
YES
Increase CIS
clamp control
register by 1
NO
MIN(ADC output)
> 102
YES
Increase CIS
clamp control
register by 1
Go to calibration
20
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
CORE EVALUATION GUIDE
0.1u
0.1u
BGR
VSSA2
VDDA2
R_VIN
0.1u
VCOM REFB
EXT_MCTL
MCTL1,MCTL2
VSSA1
VDDA1
D[11:0]
bl8531h
G_VIN
B_VIN
REFT
0.1u
AD[2:0]
VDDD
CSB
VSSD
WRB
VBB
RDB
CDS1_CLK CDS2_CLK
STRTLN
OEB
ADCCLK
TIMING GENERATOR
MPU INTERFACE
MUX
DSP ASIC
MUX
Externally forced digital input/output
21
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
PACKAGE CONFIGURATION
The digital pins should be well decoupled to the analog ground plane.
50
0.1u 0.1u 0.1u
50
50
10u
0.1u
0.1u
RDB
WRB
OEB
ADCCLK
CDS2_CLK
R_VIN
CDS1_CLK
STRTLN
VDDD
VSSD
BGR
REFB
VCOM
50
REFT
0.01u
CSB
AD[2]
0.01u
G_VIN
AD[1]
B_VIN
AD[0]
50
0.01u
BL8531H
IBIAS
50
AFE85
VDDA1
EXT_MCTL
0.1u
VSSA1
MCTL1
48 QFP
VBB
D[11]
NC
D[10]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
NC
ITEST
VDDO
D[8]
VSSO
STBY
VSSA2
D[9]
VDDA2
SPEEDUP
D[0]
10u
MCTL2
0.1u
10u
:Analog Ground
:Digital Ground
22
D[7]
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
PACKAGE PIN DESCRIPTION
Pin No.
Pin Name
I/O Type
Description
1
NC
-
2
VDDA2
AP
Analog Power for A/D Converter
3
VSSA2
AG
Analog Ground for A/D Converter
4
VSSO
DG
Output Buffer Ground
5
VDDO
DP
Output Buffer Power
6
D[0]/MPU[0]
DB
Digital Output LSB/Register Input LSB
7
D[1]/MPU[1]
DB
Digital Output/Register Input
8
D[2]/MPU[2]
DB
Digital Output/Register Input
9
D[3]/MPU[3]
DB
Digital Output/Register Input
10
D[4]/MPU[4]
DB
Digital Output/Register Input
11
D[5]/MPU[5]
DB
Digital Output/Register Input
12
D[6]/MPU[6]
DB
Digital Output/Register Input
13
D[7]/MPU[7]
DB
Digital Output/Register Input MSB
14
D[8]
DB
Digital Output
15
D[9]
DB
Digital Output
16
D[10]
DB
Digital Output
17
D[11]
DB
Digital Output MSB
18
MCTL1
DI
Color Pointer for MUX Control
19
EXT_MUX
DI
MUX Control Mode Selection
Low : by MCTL1, MCTL2
High : by Configuration Register
20
MCTL2
DI
Color Pointer for MUX Control
21
AD[0]
DI
Register Selection Pin
22
AD[1]
DI
Register Selection Pin
23
AD[2]
DI
Register Selection Pin
24
CSB
DI
Chip Selection (Active Low)
Not Connected
23
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
PACKAGE PIN DESCRIPTION (Continued)
24
Pin No.
Pin Name
I/O Type
Description
25
RDB
DI
Read Strobe (Active Low)
26
WRB
DI
Write Strobe (Active Low)
27
OEB
DI
Output Enable (Active Low)
28
ADCCLK
DI
A/D Converter Clock Input
29
CDS2_CLK
DI
CDS Data Clock Input
30
CDS1_CLK
DI
CDS Reset Clock Input
31
STRTLN
DI
Start Line (Active Low)
32
VDDD
DP
Digital Power
33
VSSD
DG
Digital Ground
34
BGR
AB
Bandgap Reference Voltage
35
VCOM
AB
Reference Middle Voltage
36
REFT
AB
Reference Top Voltage
37
REFB
AB
Reference Bottom Voltage
38
R_VIN
AI
Red Analog Input
39
G_VIN
AI
Green Analog Input
40
B_VIN
AI
Blue Analog Input
41
IBIAS
AB
Analog Test Pin (Floating)
42
VDDA1
AP
Analog Power
43
VSSA1
AG
Analog Ground
44
VBB
AG
Analog Ground
45
NC
-
Not Connected
46
SPEEDUP
DI
Test Pin ( Set to Low)
47
STBY
DI
Stand By (Power Down)
Low = Normal
High = Power Save
48
ITEST
AB
Analog Test Pin (Floating)
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
USER GUIDE
CONFIGURATION
It is necessary that output signal of analog front end be shading-compensated by back end logic block including
subtracter and multiplier.
Shading-Compensation Block
Memory
CCD/CIS
Subtracter
Multiplier
AFE
Controller
Output Bus Controls
CSB
0
0
0
0
1
1
WRB
0
1
1
1
x
x
RDB
1
x
0
x
x
x
OEB
1
0
x
1
0
1
MPU Output
Z
ADC Output
Z
DOUT
MPU Input
X
x: Don't Care X: Unknown (Not recommended)
Z: High Impedance
25
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
PHANTOM CELL INFORMATION
R MIN
G MIN
VBB
VSSA1
B MIN
VDDA1
VCOM
REFT
REFB
VBB
VSSA1
VDDA1
IBIAS
BGR
 Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design
methods.
The term "External" implies that the pins should be assigned externally like power pins.
The term "External/internal" implies that the applications of these pins depend on the user.
CDS2_CLK
CDS1_CLK
VSSD
VSSD
VDDD
VDDD
bl8531h
12-bit 6 MSPS AFE
for Image Processor
VDDA2
VSSA2
ADCCLK
STRTLN
ITEST
STBY
SPEEDUP
VDDO
VSSO
MCTL2
MCTL1
26
OEB
WRB
RDB
CSB
AD[2]
AD[1]
AD[0]
DO[11]
DO[10]
DO[9]
DO[8]
DO[7]
DO[6]
DO[5]
DO[4]
DO[3]
DO[2]
DO[1]
DO[0]
EXT_MCTL
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
Pin Name
Pin Usage
Pin Layout Guide
VDDA1
External
- Maintain the large width of lines as far as the pads.
VSSA1
External
- Place the port positions to minimize the length of power lines.
VDDA2
External
- Do not merge the analog powers with other power from other
VSSA2
External
VDDD
External
VSSD
External
VDDO
External
VSSO
External
VBB
External
R_VIN
External/Internal
- Do not overlap with digital lines.
G_VIN
External/Internal
- Maintain the shortest path to pads.
B_VIN
External/Internal
ADCCLK
External/Internal
CDS1_CLK
External/Internal
CDS2_CLK
External/Internal
REFT
External/Internal
- Maintain the larger width and the shorter length as far as the pads.
REFB
External/Internal
- Separate from all other digital lines.
VCOM
External/Internal
BGR
External/Internal
IBIAS
External/Internal
- Test pins
ITEST
External/Internal
- SPEEDUP = set to "LOW"
STBY
External/Internal
SPEEDUP
External/Internal
STRTLN
External/Internal
- Separated from the analog clean signals if possible.
EXT_MCTL
External/Internal
- Do not exceed the length by 1,000um.
MCTL1,2
External/Internal
OEB
External/Internal
WRB
External/Internal
RDB
External/Internal
CSB
External/Internal
AD[2:0]
External/Internal
D[11:0]
External/Internal
blocks.
- Use good power and ground source on board.
- Separate from all other analog signals
27
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
FEEDBACK REQUEST
It should be quite helpful to our AFE core development if you specify your system requirements on AFE in the
following characteristic checking table and fill out the additional questions.
We appreciate your interest in our products. Thank you very much.
Characteristics
Symbol
Min
Typ
Max
Resolution
Signal-to-Noise & Distortion Ratio
Unit
Comment
Bits
SNDR
dB
Conversion Rate
3-Channel with CDS
1-Channel with CDS
MSPS
MSPS
Differential Nonlinearity
DNL
LSB
Integral Nonlinearity
INL
LSB
Unipolar Offset Error
%FSR
Gain Error
%FSR
Anlog Input
Vp-p
Full-Scale Input
Power Supply
Analog Voltage
Digital Voltage
VDDA
VDDD
V
V
Power Consumption
mW
Temperature Range
°C
 What do you want to choose as power supply voltages? For example, the analog VDD needs to be 5V. The
digital VDD can be 3.3V/5V.
 Which modes of AFE do you use for overall system ? (Refer to page 9)
For example: 3channel operation with CDS / 3channel SHI(CIS) operation
1channel operation with CDS / 1channel SHI(CIS) operation
 Would you define the gain range and input offset range ?
 Could you explain external/internal pin configurations as required?
 Should the bus interface be compatible with TTL ?
 When STRTLN is low, the internal circuit is reset on the rising edge of ADCCLK.
Which channel is multiplexer switched to on the next rising edge of ADCCLK, after STRTLN goes high?
 If possible, present other requirements below.
28
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
HISTORY CARD
Version
Date
Modified Items
ver 1.0
98.11
Original version published (preliminary)
ver 1.1
99.1
Release the formal data sheet
ver 2.0
02.4.16
Comments
Change the data sheet format, phantom information added
29
AFE FOR CCD/CIS SIGNAL PROCESSOR
BL8531H
NOTES
30