AFE FOR CCD/CIS SIGNAL PROCESSOR BW1222L FEATURES GENERAL DESCRIPTION The samsung analog front end(AFE) for CCD/CIS • 10-bit 6MSPS A/D Converter image • Integrated Triple Correlated Double signal is an integrated analog signal Sampler processor for color image signal. The AFE converts CCD/CIS output signal to digital • 3-Channel 2 MSPS Color Mode data. • Analog Programmble Gain Amplifier The AFE CDS(Correlated includes Double three-channel Sampler) circuit, PGA(Programmable Gain Amplifier), and 10-bit analog to digital converter with reference generator. • Internal Voltage Reference • Wide clamp level controllability for CIS signal A parallel data bus provides a simple interface to • No Missing Code Guaranteed 8-bit microcontroller. • Microcontroller-Compatible Control Interface • Operation by 3.3V Power Supply • CMOS Low Power Dissipation APPLICATIONS KEY SPECIFICATION • Color and B/W Scanner • Digital Copiers • Resolution: 10-bit • Facsimile • Conversion Rate: 6 MHz(2 MHz*3) • General Purpose CCD/CIS imager • Supply Voltage: 3.3 V ± 5% • Power Dissipation: 250 mW(Typical) FUNCTIONAL BLOCK DIAGRAM RED CDS PGA REF GREEN D[9:0] CDS PGA INPUT OFFSET MUX ADC REGISTER MPU PORT BLUE CDS PGA GAIN REGISTER Ver 1.4 (Oct., 1998) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD VDDA1, VDDA2 AP vdda Analog Supply VSSA1, VSSA2 AG vssa Analog Ground VBB AG vbba Analog Bulk REFT AB pia_bb Reference Decoupling REFB AB pia_bb Reference Decoupling VCOM AB pia_bb Analog Common Voltage R_VIN AI piar10_bb Analog Input; Red G_VIN AI piar10_bb Analog Input; Green B_VIN AI piar10_bb Analog Input; Blue STRTLN DI picc_bb STRTLN indicates beginning of line CDS1_CLK DI picc_bb CDS Reset Clock Pulse Input CDS2_CLK DI picc_bb CDS Data Clock Pulse Input ADCCLK DI picc_bb A/D Converter Sample Clock Input VDDA3 DP vddd Digital Supply (2 pins;VDDA3, VDDA4) VSSA3 DG vssd Digital Ground (2 pins;VSSA3, VSSA4) CSB DI picc_bb Chip Select; Active Low WRB DI picc_bb Write Strobe; Active Low RDB DI picc_bb Read Strobe; Active Low OEB DI picc_bb Output Enable; Active Low D[9:0] DB poa_bb Data Inputs/Outputs AD[2:0] DI picc_bb Register Select TEST_S1, TEST_S2 DI picc_bb Channel Select in Test Mode TEST_CTL DI picc_bb Test Mode Control; Active Low TEST_OUT AO poa_bb Test Mode Output MCTL1, MCTL2 DI picc_bb Channel Select in External MUX Control EXT_MCTL DI picc_bb External MUX Control; Active Low DESCRIPTION I/O TYPE ABBR. · · · · · · AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AP : Analog Power AG : Analog Ground SEC ASIC · · · · DP : DG : AB : DB : 2/21 Digital Power Digital Ground Analog Bidirectional Port Digital Bidirectional Port MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR CORE PIN CONFIGURATION REFT VCOM REFB VDDA1,VDDA2 VSSA1,VSSA2,VBBA 2 2 3 R_VIN 2 bw1222l G_VIN 10 3 R_VIN B_VIN TEST_OUT TEST_CTL TEST_S1,TESTS2 EXT_MCTL MCTL1,MCTL2 D[9:0] AD[2:0] CSB WRB RDB OEB 2 2 VSSA3,VSSA4 VDDA3,VDDA4 STRTLN CDS1_CLK CDS2_CLK ADCCLK ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Value Unit Supply Voltage VDD 4.5 V Analog Input Voltage AIN VSS to VDD V Digital Input Voltage CLK VSS to VDD V VRT/VRB VSS to VDD V Reference Voltage Storage Temperature Range Tstg -45 to 150 ºC Operating Temperature Range Topr 0 to 70 ºC NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model) SEC ASIC 3/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR ANALOG SPECIFICATIONS(VDDA1, VDDA2=3.3V, VDDA3=3.3V, ADCCLK=6MHz, CDS1_CLK=2MHz,CDS2_CLK=2MHz, PGA Gain=1 unless otherwise noted) Characteristics Symbol Resolution Signal-to-Noise & Distortion Ratio Min Typ Max 10 SNDR DNL Integral Nonlinearity INL 46 49 dB 6 6 MSPS MSPS ±1 LSB ±2 LSB Unipolar Offset Error 0.8 %FSR Gain Error 1.6 %FSR Anlog Input Full-Scale Input Input Capacitance Reference Top Reference Bottom Power Supply Analog Voltage Digital Voltage Analog Current Digital Current 0.06 2.0 Vp-p pF V V 3.45 3.45 V V mA mA 8 2.1 1.1 VDDA VDDD IDDA IDDD 3.15 3.15 3.3 3.3 70 5 Power Consumption 250 Temperature Range Comment Bits Conversion Rate 3-Channel with CDS 1-Channel with CDS Differential Nonlinearity Unit 3.3V±5% 3.3V±5% mW 0 70 ºC DIGITAL SPECIFICATIONS(VDDA1, VDDA2=3.3V, VDDA3=3.3V, ADCCLK=6MHz, CDS1_CLK=2MHz, CDS2_CLK=2MHz, CL=20pF unless otherwise noted) Characteristics Symbol Min High Level Input Voltage VIH 2.0 Low Level Input Voltage VIL High Level Input Current IIH 10 µΑ Low Level Input Current IIL 10 µΑ High Level Output Voltage VoH Low Level Output Voltage VOL SEC ASIC Typ Max Unit Comment V 0.8 2.4 0.4 4/21 V V IoH = 0.5mA V IoL = -0.5mA MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING SPECIFICATIONS Characteristics (VDDA=3.3V, VDDD=3.3V unless otherwise noted) Symbol Min Typ Max Unit 3-Channel Conversion Rate 500 ns 1-Channel Conversion Rate 166 ns CDS1_CLK Pulse Width tC1CLK 60 ns CDS2_CLK Pulse Width tC2CLK 70 ns CDS2_CLK2 Pulse Width tC2CLKB 70 ns CDS1_CLK Falling to CDS2_CLK2Rising tC1C2A 5 ns CDS2_CLK Falling to CDS1_CLK Rising tC2C1A 5 ns ADCCLK Pulse Width tADCLK 70 ns CDS2_CLK Rising to ADCCLK Rising tC2ADA 70 ns CDS2_CLK Falling to ADCCLK Falling tC2ADB 5 ns ADCCLK Rising to CDS2CLK Falling tADC2A 5 ns STRTLN Rising, Falling Setup & Hold tS, tH 15 ns ADC Output Delay tADDT 20 ns Register Address Setup Time tAS 15 ns Register Address Hold Time tAH 15 ns Data Hold Time tDH 15 ns Register Chip Select Setup Time tCSS 15 ns Register Chip Select Hold Time tCSH 15 ns Register Read Pulse Width tPWR 50 ns Write Pulse Width tPWW 25 ns Register Read To Data Valid tDD 40 ns Output Enable High to Tri-State tHZ 10 ns Tri-State to Data Valid tDEV 15 ns Aperture Delay tAD 2 ns Latency for 1 Channel mode 3.5 ADCCLK Cycles * Aperture delay is a timing measurement between the sampling clocks and CDS. It is measured from the falling edge of the CDS2_CLK input to when the input signal is held for data conversion SEC ASIC 5/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING DIAGRAM 3-CHANNEL CDS MODE Analog Input R0,G0,B0 tC1C2A R1,G1,B1 R2,G2,B2 tC2C1A tC1CLK CDS1_CLK tC2ADA tADC2A tC2CLKB CDS2_CLK tADCLK ADCCLK tH STRTLN tS 3-CHANNEL SHA MODE Analog Input R0,G0,B0 tC2ADA R1,G1,B1 R2,G2,B2 tADC2A tC2CLKB CDS2_CLK tADCLK ADCCLK tH STRTLN tS 1-CHANNEL CDS MODE Analog Input tC1CLK tC1C2A tC2C1A CDS1_CLK tC2CLK CDS2_CLK tC2ADA tADCLK tC2ADB ADCCLK tH STRTLN tS SEC ASIC 6/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING DIAGRAM 1-CHANNEL SHA MODE Analog Input R0,G0,B0 R1,G1,B1 R2,G2,B2 tC2CLK CDS2_CLK tC2ADA tADCLK tC2ADB ADCCLK ADC TIMING A(n) ADC Input A(n+1) ADCCLK tADDT ADCOUT A(n-2)[9:0] A(n-1)[9:0] A(n)[9:0] WRITE TIMING OEB CSB tAS tAH AD[2:0] tCSS WRB tCSH tPWW tDD tDH D[7:0] SEC ASIC 7/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING DIAGRAM READ(1) TIMING CSB tAS tAH AD[2:0] tCSS tPWR RDB tCSH tDH tDD D[7:0] 'Read(1)' means microcontroller reads D[7:0]/MPU[7:0]. READ(2) TIMING ADCCLK tADDT D[9:0] tHZ tDEV OEB CSB should keep 'High' to read. SEC ASIC 8/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR FUNCTIONAL DESCRIPTION 1) 3-Channel Operation with CDS 4) 1-Channel SHA Operation This mode enables simultaneous sampling of a This mode enables single-channel or monochrome triple output CCD. The CCD waveforms are ac sampling. The CDS function is replaced coupled to the VINR, VING and VINB pins where sample and hold amplifier. The input waveforms they are automatically biased at an appropriate are either dc coupled or dc restored to the analog voltage using the on-chip clamp. The internal input pin. The input reference voltage in this mode CDSs take two samples of the incoming pixel will be defined by clamp level control register. data; the first samples are taken during the reset Bit2 and bit2 in configuration register select the time while the second samples are taken during desired input among red, green and blue. with the data portion of the input pixels. When STRTLN is low, the internal circuitry is reset on the next rising edge of ADCCLK; the multiplexer is switched to red channel. MAIN BLOCK DESCRIPTION 2) 3-Channel SHA Operation 1) Programmable Gain Amplifier This mode enables simultaneous sampling of a The analog programmable gain can accommodate triple output CIS or something like that. The CDS a wide range of input voltage spans. The transfer functions are replaced with the sample and hold function of the PGA is as follows. amplifiers. The input waveforms are either dc H(X) = 1/6*X + 5/6, coupled or dc restored to the VINR, VING and where the range of X is 0 to 31. VINB pins. The input reference voltage in this Thus, the minimum gain value is equal to 5/6, and mode will be defined by clamp level control the maximum gain value is equal to 6. The register. transfer function has linearity in linear scale. The When STRTLN is low, the internal circuitry is overall gain is equal to analog gain reset on the next rising edge of ADCCLK; the by digital gain. So, the multiplier should be multiplexer is switched to red channel. required in back end of AFE. 3) 1-Channel Operation with CDS 2) REGISTER OVERVIEW This mode enables single channel or monochrome The MPU port map is accessed through pins A0, sampling. The CCD waveforms are ac coupled to A1 and A2. See MPU port map format.(next page) multiplied the analog input pin where they are automatically biased at an appropriate voltage using the on-chip clamp. Bit2 and bit3 in configuration register select the desired input among red, green and blue. SEC ASIC 9/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR VSSA1, 2 VDDA1, 2 VSSA3 VDDA3 REFT VCOM REFB MCTL2 RED R_VIN MCTL1 CDS CLAMP PGA EXT_MCTL + TEST_S2 R_OFFSET[7:0] R_CLAMP[2:0]; For only SHA mode REF R_GAIN[4:0] TEST_S1 TEST_CTL TEST_OUT GREEN G_VIN CDS CLAMP MUX PGA 10 ADC 10 D[9:0]/ MPU[7:0] + G_OFFSET[7:0] G_CLAMP[2:0]; For only SHA mode G_GAIN[4:0] BLUE B_VIN CDS CLAMP CSB PGA + Configuration B_OFFSET[7:0] OEB Register B_CLAMP[2:0]; For only SHA mode RDB B_GAIN[4:0] R_OFFSET[7:0] Input Offset G_OFFSET[7:0] Register B_OFFSET[7:0] (R,G,B) 8 MPU PORT WRB AD[2] AD[1] R_CLAMP[2:0], R_GAIN[4:0] Gain & Clamp Level Register (R,G,B) G_CLAMP[2:0], G_GAIN[4:0] AD[0] B_CLAMP[2:0], B_GAIN[4:0] CDS1_CLK CDS2_CLK STRTLN ADCCLK BLOCK DIAGRAM Table: MPU Port Map Format A2 A1 A0 0 0 0 Configuration Register 0 0 1 Red Input Offset register 0 1 0 Green Input Offset Register 0 1 1 Blue Input Offset Register 1 0 0 Red Gain & CIS Clamp Control Register 1 0 1 Green Gain & CIS Clamp Control Register 1 1 0 Blue Gain & CIS Clamp Control Register 1 1 1 Reserved SEC ASIC Register 10/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR Configuration Register Bit 7 Bit 6 Clamp Clamp mode mode select1 select0 Bit 5 Bit 4 Bit 3 Bit 2 Color1 Color0 (Single (Single Channel) Channel) External Set to 0 Reference Bit 1 Bit 0 Single CDS Channel Enable Single Channel Color Pointer Bit3 Bit2 Color 0 0 Red 0 1 Green 1 0 Blue 1 1 Reserved Clamp Mode Selection Bit7 Bit6 Clamp Mode 0 0 Line Clamp 0 1 Pixel Clamp 1 0 No Clamp 1 1 Reserved Input Offset Register MSB Bit 7 LSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Gain & CIS Clamp Control Register MSB LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CCC2 CCC1 CCC0 PGA4 PGA3 PGA2 PGA1 PGA0 * CCCn: CIS Clamp Control n EXTERNAL MULTIPLEXER CONTROL MODE EXT_MCTL = "LOW" MCTL2 SEC ASIC Color MCTL1 0 0 Red 0 1 Green 1 0 Blue 1 1 Reserved 11/21 MIXED AFE FOR CCD/CIS SIGNAL PROCESSOR BW1222L INPUT COUPLING CAPACITOR OVERALL TRANSFER FUNCTION The overall transfer function can be calculated as Because of the DC offset present at the output of follows. CCD, some kind of DC restoration is required. In ADCout=[(Vin+Input_Offset)* PGA_Gain]/(2*REF)*1024 case of CDS enable mode, to simplify input level , shifting, a DC decoupling capacitor is used in where REF is equal to (REFT-REFB) and Input _Offset means the DAC value of the input offset register. The analog offset range of the input offset register is varied between 150mV and -150 mV. The 8-bit data format for the input offset register is straight binary coding. Thus, an all 'zeros' data word corresponds to -150 mV. An all 'ones' data word corresponds to 150 mV. To maximize the dynamic range of the ADC input, it is necessary to program the input offset register code to move the ADC code corresponding to the black level towards 'zero'. In case of processing CIS signal, 3bits of the gain & clamp control register are allocated to control CIS clamp level. Like the input offset register, the 3-bit data format is straight binary coding. An all 'zeros' data word corresponds to 0.1 V and an all 'ones' data word corresponds to 1.5 V. SEC ASIC conjuction with the internal input circuitry. The capacitor charging or discharging depends on the clamping time, the analog input resistance of the AFE and the output resistance of the circuit driving the coupling capacitor. The clamping time is typically (n*T), where n is the number of periods CDSCLK1 is asserted and T is the period of assertion. CDSCLK2 should not be asserted during clamping time. And, STRTLN must be low in line clamp mode for clamping operation. The analog input resistance of the AFE is equal to 1 kΩ. The recommended input coupling capacitor is more than 0.01uF. Thus, to extend the clamping time, the time a transport motor moves the scanner carriage can be available, for example. 12/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR TEST MODE FOR EACH PGA OUTPUT (Optional) It is possible to test each PGA output that is connected to next ADC block by external control pins. So, each PGA output can be shown with an external test pin. Test mode control(TEST_CTL) pin should go 'LOW' to operate AFE in test mode. Color Pointer for Test Mode TEST_S2 TEST_S1 Color 0 0 Red 0 1 Green 1 0 Blue 1 1 Reserved R PGA G ADC B TEST MUX <TEST_CTL> <TEST_S2> <TEST_S1> <TEST_OUT> SEC ASIC 13/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR POWER-ON INITIALIZATION CALIBRATION Decide clamp level for SHA mode (Refer to next page) Set PGA gain (Input offset = 0 mV) Write to configuration register Set CDS or SHA operation Set 3 or 1 channel mode Set color pointer Set clamp mode Scan dark line Compute pixel offsets Write to PGA gain register Set to gain of one(00001) Set input offset Write to input offset register Set to 0mV(10000000) Set odd/even offset in back end YES YES Set another color Set another color NO NO Set gain/offset bus size in back end Set external pixel offset in back end Scan white line Compute pixel gains in back end YES Adjust PGA gain NO SEC ASIC 14/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR CIS CLAMP LEVEL DECISION FOR EACH INPUT *Assume that PGA gain = 1. The user can modify this alogorithm as required in overall system Write CIS clamp control register Set to (111) Decrease CIS clamp control register by 1 [Repeatedly, scan clamp level. Scan clamp level input NO Average ADC output] ADC output > 0 YES Scan dark line [MIN(ADC output) = Minimum value of all pixels] YES MIN(ADC output) > 104 NO Increase CIS clamp control register by 1 YES MIN(ADC output) > 52 [(100mV)/(2V) * 1024 -1 = 52] NO MIN(ADC output) > 0 NO Decrease CIS clamp control register by 1. Scan dark line YES Increase CIS clamp control register by 1 NO MIN(ADC output) > 52 YES Increase CIS clamp control register by 1 Go to calibration SEC ASIC 15/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR CORE EVALUATION GUIDE 0.1u 0.1u 0.1u VDDA1,VDDA2 VSSA1,VSSA2,VBBA REFT 2 VCOM REFB 2 3 R_VIN 2 bw1222l G_VIN 10 3 R_VIN B_VIN 2 VSSA3,VSSA4 2 CDS1_CLK CDS2_CLK ADCCLK TEST_OUT TEST_CTL TEST_S1,TESTS2 EXT_MCTL MCTL1,MCTL2 D[9:0] AD[2:0] CSB WRB RDB OEB VDDA3,VDDA4 STRTLN TIMING GENERATOR MPU INTERFACE MUX DSP ASIC MUX Externally forced digital input/output SEC ASIC 16/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR PACKAGE CONFIGURATION The digital pins should be well decoupled to the analog ground plane. 10u 50 0.1u 0.1u 50 50 10u 0.1u 0.1u 0.01u R E F B 50 R E F T V C O M N C V S S A 3 V S S A 3 V D D A 3 V D D A 3 S T R T L N R_VIN 0.01u C D S 1 _ C L K C D S 2 _ C L K A D C C L K O E B W R B R D B C S B AD[2] AD[1] G_VIN 50 AD[0] B_VIN MCTL2 IBIAS 0.01u 50 10u 0.1u VDDA1 MCTL1 VDDA1 EXT_MCTL NC VSSA1 BW1222L VSSA1 NC TEST_CTL VBBA NC TEST_S2 NC TEST_S1 NC INDEX2 NC INDEX1 SPEEDUP T STBY E S ITEST T _ O U T SEC ASIC D[9] D[8] V D D A 2 V D D A 2 V S S A 2 V S S A 2 V S S A 4 V S S A 4 V D D A 4 V D D A 4 0.1u 0.1u 10u 10u 17/21 D[7] D [ 0 ] D [ 1 ] D [ 2 ] D [ 3 ] D [ 4 ] D [ 5 ] D [ 6 ] MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR PACKAGE PIN DESCRIPTION PIN NO. PIN NAME I/O TYPE DESCRIPTION 1 TEST_OUT AO Analog Output in Test Mode 2 VDDA2 AP Analog Power for A/D Converter 3 VDDA2 AP Analog Power for A/D Converter 4 VSSA2 AG Analog Ground for A/D Converter 5 VSSA2 AG Analog Ground for A/D Converter 6 VSSA4 DG Output Buffer Ground 7 VSSA4 DG Output Buffer Ground 8 VDDA4 DP Output Buffer Power 9 VDDA4 DP Output Buffer Power 10 D[0] DB Digital Output (LSB) 11 D[1] DB Digital Output 12 D[2] DB Digital Output 13 D[3] DB Digital Output 14 D[4] DB Digital Output 15 D[5] DB Digital Output 16 D[6] DB Digital Output 17 D[7] DB Digital Output 18 D[8] DB Digital Output 19 D[9] DB Digital Output (MSB) 20 INDEX1 - Index Resistor(+) 21 INDEX2 - Index Resistor(-) 22 TEST_S1 DI Color Pointer in Test Mode 23 TEST_S2 DI Color Pointer in Test Mode 24 TEST_CTL DI Test Mode Control (Active Low) 25 NC - Not Connected 26 NC - Not Connected 27 EXT_MCTL DI MUX Control Mode Selection(Active Low) 28 MCTL1 DI Color Pointer for MUX Control 29 MCTL2 DI Color Pointer for MUX Control 30 AD[0] DI Register Selection Pin 31 AD[1] DI Register Selection Pin 32 AD[2] DI Register Selection Pin SEC ASIC 18/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR PACKAGE PIN DESCRIPTION PIN NO PIN NAME I/O TYPE DESCRIPTION 33 CSB DI Chip Selection (Active Low) 34 RDB DI Read Strobe (Active Low) 35 WRB DI Write Strobe (Active Low) 36 OEB DI Output Enable (Active Low) 37 ADCCLK DI A/D Converter Clock Input 38 CDS2_CLK DI CDS Data Clock Input 39 CDS1_CLK DI CDS Reset Clock Input 40 STRTLN DI Start Line (Active Low) 41 VDDA3 DP Digital Power 42 VDDA3 DP Digital Power 43 VSSA3 DG Digital Ground 44 VSSA3 DG Digital Ground 45 NC - Not Connected 46 VCOM AB Reference Middle Voltage 47 REFT AB Reference Top Voltage 48 REFB AB Reference Bottom Voltage 49 R_VIN AI Red Analog Input 50 G_VIN AI Green Analog Input 51 B_VIN AI Blue Analog Input 52 IBIAS AB Current Bias Control for CDS & PGA 53 VDDA1 AP Analog Power 54 VDDA1 AP Analog Power 55 VSSA1 AG Analog Ground 56 VSSA1 AG Analog Ground 57 VBBA AG Analog Ground 58 NC - Not Connected 59 NC - Not Connected 60 NC - Not Connected 61 NC - Not Connected 62 SPEEDUP AI Speed-Up Selection for A/D Converter 63 STBY AI Power Down Mode for A/D Converter 64 ITEST AB Current Bias Control for A/D Converter SEC ASIC 19/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR USER GUIDE SYSTEM CONFIGURATION It is necessary that output signal of analog front end be shading-compensated by back end logic block including subtracter and multiplier. (Shading-Compensation Block) Memory Subtracter Multiplier AFE CCD/CIS Controller (Output Bus Controls) CSB 0 0 0 0 1 1 WRB 0 1 1 1 x x RDB 1 x 0 x x x OEB 1 0 x 1 0 1 DOUT MPU Input x: Don't Care X MPU Output Z ADC Output Z X: Unknown (Not recommended) Z: High Impedance SEC ASIC 20/21 MIXED BW1222L AFE FOR CCD/CIS SIGNAL PROCESSOR FEEDBACK REQUEST Specification Characteristics Symbol Min Typ Resolution Signal-to-Noise & Distortion Ratio Max Unit Bits SNDR dB Conversion Rate 3-Channel with CDS 1-Channel with CDS MSPS MSPS Differential Nonlinearity DNL LSB Integral Nonlinearity INL LSB Unipolar Offset Error %FSR Gain Error %FSR Anlog Input Full-Scale Input Power Supply Analog Voltage Digital Voltage Comment Vp-p VDDA VDDD V V Power Consumption mW Temperature Range ºC - What do you want to choose as power supply voltages? For example, the analog VDD needs to be 3V. The digital VDD can be 3.3V/5V. - Which modes of AFE do you use for overall system ? (Refer to page 9) - Would you define the gain range and input offset range ? - Could you explain external/internal pin configurations as required? - Should the bus interface be compatible with TTL ? - If possible, present other requirements below. SEC ASIC 21/21 MIXED AFE FOR CCD/CIS SIGNAL PROCESSOR BW1222L HISTORY CARD Version Date ver 1.0 Modified Items Comments Original version published (preliminary) ver 1.1 ver 1.2 ver 1.3 ver 1.4 1998.10 Release the formal datasheet SEC ASIC MIXED