TOSHIBA TLCS-90 TMP90 TMP90PH02 CMOS 8–Bit Microcontrollers achieved by using a general EPROM programmer with an adapter socket. The function of this device is exactly same as the TMP90CH02 and TMP90C802A by programming to the internal PROM. The differenes between TMP90PH02 and TMP90C802A are the internal RAM size, and the internal PROM size. The following are the memory map of TMP90PH02 and TMP90C802A. TMP90PH02P/TMP90PH02M 1. Outline and Characteristics The TMP90PH02 is a system evaluation LSI having a built in One-Time PROM for TMP90CH02. A programming and verification for internal PROM is Parts No. TMP90PH02P TMP90PH02M ROM OTP 16384 x 8bit RAM 512 x 8bit Package Adapter Socket No. 40-DIP BM1158 40-SOP BM1159 The information contained here is subject to change without notice. The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA. TOSHIBA CORPORATION 1/14 TMP90PH02 Figure 1. TMP90PH02 Block Diagram 2/14 TOSHIBA CORPORATION TMP90PH02 2. Pin Assignment and Functions The assignment of input/output pins, their names and functions are described below. 2.1 Pin Assignment Figure 2.1 (1) shows pin assignment of the TMP90PH02. Figure 2.1 (1). Pin Assignment TOSHIBA CORPORATION 3/14 TMP90PH02 2.2 Pin Names and Functions The TMP90PH02P has MCU mode and PROM mode. (1) MCU Mode (The TMP90PH02 and the TMP90C802A are pin compatible). Table 2.2 Pin Names and Functions Pin Name No. of pins P00 ~ P07 /D0 ~ D7 8 P10 ~ P17 /A0 ~ A7 8 P20 ~ P27 /A8 ~ A 15 8 P31 /RxD 1 I/O 3 states I/O 3 states I/O Output I/O Output Input P32 /TxD /RTS /SCLK 1 Output P33 /TxD 1 Output P35 /RD 1 Output P36 /WR 1 Output P37 /WAIT TO1 Function Port 0: 8-bit I/O port that allows selection of input/output on byte basis Data Bus: Also functions as 8-bit bidirectional data bus for external memory Port 1: 8-bit I/O port that allows selection on byte basis Addrress Bus: The lower 8 bits address bus for external memory Port 2: 8-bit I/O port that allows selection on byte basis Addrress Bus: The uppper 8 bits address bus for external memory Port 31: 1-bit input port Receives serial data Port 32: 1-bit output port 1 Input Output Serial clock output Port 33: 1-bit output port Transmits serial data Port 35: 1-bit output port Read: Generates strobe signal for reading external memory Port 36: 1-bit output port Writes: Generates strobe signal for writing external memory Port 37: 1-bit input port Wait: Input pin for connecting slow speed memory or peripheral LSI Timer Output 1: Output of Timer 0 or 1 Port 80: 1-bit input port P80 /INTO 1 Input Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable) Port 81: 1-bit input port P81 /INT1 /TI4 Interrupt request pin 1: Interrupt request pin (Rising/falling edge is programmable) 1 Input Timer input 2: Counter/capture trigger signal for Timer 2 Non-maskable interrupt request pin: Falling edge interrupt request pin 4/14 NMI 1 Input CLK 1 Output Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is Pulled up internally during resetting. EA 1 Input Connects with VCC pin . RESET 1 Input Reset: Initializes the TMP90PH02 (Built-in pull-up resistor) X1/X2 2 Input/ Output Pin for quartz crystal or ceramic resonator (1 ~ 16.0MHz) VCC 1 – Power supply (+5V) VSS (GND) 1 – Ground (0V) TOSHIBA CORPORATION TMP90PH02 2) PROM Mode Table 2.2.2 Pin Function Name No. of pins I/O A7 ~ A0 8 Input A12 ~ A8 5 Input A15 ~ A13 3 Input Function Pin Name (MCU mode) Address Input P17 ~ P10 P24 ~ P20 Be fixed to “L” level. P27 ~ P25 Data Input/Output P07 ~ P00 D7 ~ D0 8 I/0 OE 1 Input Output Enable Input P35 CE 1 Input Chip Enable Input P36 VPP 1 Power Supply 12.5V/5V (Programming Power Supply) EA VCC 1 Power Supply 5V VSS 1 Power Supply 0V Pin Name No. of pins I/O Pin Setting P31 1 Input Be fixed level. P32 ~ P34 3 Output Open P37 1 Input Be fixed level. P80 , P81 2 Input Be fixed to “H” level. NMI 1 Input Be fixed to level. RESET 1 Input Be fixed to “L” level. CLK 1 Input Be fixed to “L” level. X1 1 Input X2 1 Output TOSHIBA CORPORATION Resonator connection pin 5/14 TMP90PH02 3. Operation 3.1 MCU Mode The TMP90PH02 is the OTP version of the TMP90CH02 that is replaced an internal ROM from Mask ROM to EPROM. The function of TMP90PH02 is exactly same as that of TMP90C802A. Refer to the TMP90CH02 except the functions which are not described this section. The following is an explanation of the hardware configuration and operation in the relation to the TMP90PH02. The TMP90PH02 has an MCU mode and a PROM mode. (1) Mode Setting and Function The MCU mode is set by opening the CLK pin (Output status). In the MCU mode, the operation is the same as that of TMP90CH02. (2) Memory Map Figure 3.1 shows the memory map of TMP90PH02, and the accessing area by the respective addressing mode. Figure 3.1. TMP90PH02 Memory Map 6/14 TOSHIBA CORPORATION TMP90PH02 3.2 PROM Mode (1) Mode Setting and Function PROM mode is set by setting the RESET and CLK pins to the “L” level. The programming and verification for the internal PROM is achieved by using a general PROM programmer with the adaptor socket. The device selection (ROM Type) should be “27256” with following conditions. size : 256Kbit (32K x 8-bit) VPP: 12.5V TPW: 1ms Figure 3.2 shows the setting of pins in PROM mode. Figure 3.2. PROM Mode Pin Setting (2) Programming Flow Chart The programming mode is set by applying 12.5V (programming voltage) to the VPP pin when the following pins are set as follows, (Vcc : 6.0V) *These conditions can be : “L” level) obtained by using adaptor (RESET (CLK : “L” level) socket. After the address and data have been fixed, a data on the Data Bus is programmed when the CE pin is set to “Low” (1ms plus is required). General Programming procedure of an EPROM programmer is as follows, TOSHIBA CORPORATION • Write a data to a specified address for 1ms. • Verify the data. If the read-out data does not match the expected data, another writing is performed until the correct data is written (Max. 25 times). After the correct data is written, an additional writing is performed by using three times longer programming pulse width (1ms x programming times), or using three times more programming pulse number. Then, verify the data and increment the address. The verification for all data is done under the condition of Vpp = Vcc = 5V after all data were written. Figure 3.3 shows the programming flow chart. 7/14 TMP90PH02 Figure 3.1. TMP90PH02 Memory Map (3) The Security Bit The TMP90PH02 has the Security Bit in PROM cell. If the Sercuity Bit is programmed to “0”, the content of the PROM is disable to read in PROM mode. How to Program the Security Bit. 1) Connect A15 pins to VCC. [Otherwise connect them to GND to program PROM] 2) Set programming address to 0000H. 3) To program the Security Bit, set D0 to “0”. 4) Set D2 ~ D7 to “1” respectively. The following table shows the 8-bit data to program The Security Bit. Table 3.1 Data to Program Bit to Program The Security Bit PROM (0000H ~ 3FFFH) 8/14 D0 ~ D7 A0 ~ A13 A14, A15 FEH All “0” A14 = “0” A15 = “1” – – All “0” TOSHIBA CORPORATION TMP90PH02 4. Electrical Characteristics TMP90PH02P/TMP90PH02M 4.1 Absolute Maximum Ratings Symbol VCC Parameter Supply voltage VIN Input voltage PD Power dissipation (Ta = 85°C) Rating Unit -0.5 ~ + 7 V -0.5 ~ VCC + 0.5 V 250 mW 260 °C TSTG Storage temperature -65 ~ 150 °C TOPR Operating temperature -40 ~ 85 °C TSOLDER Soldering temperature (10s) 4.2 DC Characteristics VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) TA = -20 ~ 70° (1 ~ 16MHz) Symbol Parameter Min Max Unit Test Conditions -0.3 0.8 V – VIL Input Low Voltage (P0) VIL1 P1, P2, P3, P8 -0.3 0.3VCC V – VIL2 RESET, INT0, NMI -0.3 0.25VCC V – VIL3 EA -0.3 0.3 V – VIL4 X1 -0.3 0.2VCC V – VIH Input Low Voltage (D0 ~ D7) 2.2 VCC + 0.3 V – VIH1 P3, P5, P6, P7, P8 0.7VCC VCC + 0.3 V – VIH2 RESET, INT0, NMI 0.75VCC VCC + 0.3 V – VIH4 X1 0.8VCC VCC + 0.3 V – VOL Output Low Voltage – 0.45 V IOL = 1.6mA VOH VOH1 VOH2 Output High Voltage 2.4 0.75VCC 0.9VCC – V V V IOH = -400µA IOH = -100µA IOH = -20µA IDAR Darlington Drive Current (8 I/O pins) -1.0 -3.5 mA VEXT = 1.5V REXT = 1.1kΩ µA 0.0 ≤ Vin ≤ VCC ILI Input Leakage Current 0.02 (Typ) ±5 ILO Output Leakage Current 0.05 (Typ) ± 10 µA 0.2 ≤ Vin ≤ VCC - 0.2 ICC Operating Current (RUN) Idle 1 Idle 2 17 (Typ) 1.5 (Typ) 6 (Typ) 30 5 15 mA mA mA tosc = 10MHz (60% Up @ 16.0MHz) STOP (TA = -20 ~ 70°C) STOP (TA = 0 ~ 50°C) 0.2 (Typ) 50 10 µA µA 0.2 ≤ Vin ≤ VCC - 0.2 VSTOP Power Down Voltage (@STOP) 2 RAM BACK UP 6 KΩ VIL2 = 0.2VCC, VIH2 = 0.8VCC RRST RESET Pull Up Register 50 150 KΩ CIO Pin Capacitance – 10 pF VTH Schmitt width RESET, NMI, INT0 0.4 1.0 (Typ) V – testfreq = 1MHz – Note: IDAR is guaranteed for a total of up to 8 optional ports. TOSHIBA CORPORATION 9/14 TMP90PH02 4.3 AC Characteristics VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70°C (1 ~ 16MHz) Variable Symbol 12.5MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max 62.5 1000 80 – 62.5 – ns tOSC OSC. Period = x tCYC CLK Period 4x 4x 320 – 250 – ns tWL CLK Low width 2x - 40 – 120 – 85 – ns tWH CLK High width 2x - 40 – 120 – 85 – ns tAC Address Setup to RD, WR x - 45 – 35 – 18 – ns tRR RD Low width 2.5x - 40 – 160 – 117 – ns tCA Address Hold Time After RD, WR 0.5x - 30 – 20 – 12 – ns tAD Address to Valid Data In – 3.5x - 95 – 185 – 123 ns tRD RD to Valid Data In – 2.5x - 80 – 120 – 76 ns tHR Input Data Hold After RD 0 – 0 – 0 – ns tWW WR Low width tDW Data Setup to WR tWD 2.5x - 40 – 160 – 117 – ns 2x - 50 – 110 – 75 – ns Data Hold After WR 20 70 20 70 20 70 ns tCWA RD, WR to Valid WAIT – 1.5x - 100 – 20 – 13 ns tAWA Address to Valid WAIT – 2.5x - 130 – 70 – 26 ns tWAS WAIT Setup to CLK 50 – 50 – 50 – ns tWAH WAIT Hold After CLK 0 – 0 – 0 – ns tRV RD/WR Recovery Time 1.5x - 35 – 85 – 59 – ns tCPW CLK to Port Data Output – x + 200 – 280 – 262 ns tPRC Port Data Setup to CLK 200 – 200 – 200 – ns tCPR Port Data Hold After CLK 100 – 100 – 100 – ns tCHCL RD/WR Hold After CLK x - 40 – 40 – 23 – ns tCLC RD/WR Setup to CLK 1.5x - 25 – 95 – 69 – ns tCLHA Address Hold After CLK 1.5x - 80 – 40 – 14 – ns tACL Address Setup to CLK 2.5x - 80 – 120 – 77 – ns tCLD Data Setup to CLK x - 50 – 30 – 13 – ns • AC output level High 2.2V/Low 0.8V • AC input level High 2.4V/Low 0.45V (D0 – D7) High 0.8VCC/Low 0.2VCC (excluding D0 – D7) 10/14 TOSHIBA CORPORATION TMP90PH02 4.4 Zero - Cross Characteristics VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) TA = -20 ~ 70°C (1 ~ 16MHz) Symbol Parameter VZX Zero-cross detection input AZX Zero-cross accuracy FZX Zero-cross detection input frequency Condition Min Max Unit VAC p - p AC coupling C = 0.1µF 1 1.8 50/60Hz sine wave – 135 mV – 0.04 1 kHz 4.5 Serial Channel Timing - I/O Interface Mode VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70°C (1 ~ 16MHz) Variable Symbol 10MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max tSCY Serial Port Clock Cycle Time 8x – 640 – 500 – ns tOSS Output Data Setup SCLK Rising Edge 6x - 150 – 330 – 225 – ns tOHS Output Data Hold After SCLK Rising Edge 2x - 80 – 40 – 45 – ns tHSR Input Data Hold After SCLK Rising Edge 0 – 0 – 0 – ns tSRD SCLK Rising Edge to Input DATA Valid – 6x - 150 – 330 – 225 ns 4.6 8-bit Event Counter VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70°C (1 ~ 16MHz) Variable Symbol 10MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max 8x + 100 – 740 – 600 – ns tVCK TI2 clock cycle tVCKL TI2 Low clock pulse width 4x + 40 – 360 – 290 – ns tVCKH TI2 High clock pulse width 4x + 40 – 360 – 290 – ns 4.7 Interrupt Operation VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70°C (1 ~ 16MHz) Variable Symbol 10MHz Clock 16MHz Clock Parameter Unit Min Max Min Max Min Max 4x – 320 – 250 – ns 4x – 320 – 250 – ns 8x + 100 – 740 – 600 – ns 8x + 100 – 740 – 600 – ns NMI, INT0 Low level pulse width tINTAL tINTAH NMI, INT0 High level pulse width INT1, INT2 Low level pulse width tINTBL INT1, INT2 High level pulse width tINTBH TOSHIBA CORPORATION 11/14 TMP90PH02 4.8 Read Operation (PROM Mode) DC Characteristic, AC Characterisc TA = -40 ~ 85°C Vcc = 5V ± 10% Symbol Parameter VPP VIH1 VIL1 VPP Read Voltage Input High Voltage (A0 ~ A15, CE, OE) Input Low Voltage (A ~ A15, CE, OE) tACC Address to Output Delay Condition Min Max Unit – – – 4.5 0.7 x VCC -0.3 5.5 Vcc + 0.3 0.3 x VCC V V V CL = 50PF – 2.25TCYC + α ns TCYC = 400ns (10MHz Clock) α = 200ns 4.9 Programming Operation (PROM Mode) DC Characteristic, AC Characteristic TA = 25 ± 5°C Vcc = 6V ± 0.25V Symbol Parameter VPP VIH VIL VIH1 VIL1 ICC IPP Programming Voltage Input High Voltage (D0 ~ D7) Input Low Voltage (D0 ~ D7) Input High Voltage (A0 ~ A15, CE, OE) Input Low Voltage (A0 ~ A15, CE, OE) VCC Supply Current VPP Supply Current tPW CE Programming Pulse Width Condition Min Typ Max Unit – – – – – fOSC = 10MHz VPP = 13.00V 12.25 0.2VCC + 1.1 -0.3 0.7VCC -0.3 – – 12.50 12.75 VCC + 0.3 0.2VCC - 0.1 VCC + 0.3 0.3VCC 50 50 V V V V V mA mA CL = 50PF 0.95 1.00 1.05 ms 4.10 I/O Interface Mode Timing 12/14 TOSHIBA CORPORATION TMP90PH02 4.11 Timing Chart 4.12 Read Operation Timing Chart (PROM Mode) TOSHIBA CORPORATION 13/14 TMP90PH02 4.13 Programming Operation Timing Chart (PROM Mode) 14/14 TOSHIBA CORPORATION