ETC 74LVT16244MEAX

Revised July 2001
74LVT16244 • 74LVTH16244
Low Voltage16-Bit Buffer/Line Driver
with 3-STATE Outputs
General Description
Features
The LVT16244 and LVTH16244 contain sixteen non-inverting buffers with 3-STATE outputs designed to be employed
as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorted together
for 8-bit or 16-bit operation.
■ Input and output interface capability to systems at
5V VCC
The LVTH16244 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT16244 and
LVTH16244 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16244),
also available without bushold feature (74LVT16244).
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs source/sink −32 mA/+64 mA
■ Functionally compatible with the 74 series 16244
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human-body model >2000V
Machine model >200V
Charged-drive model >1000V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
74LVT16244GX
(Note 1)
Package
Number
BGA54A
(Preliminary)
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
74LVT16244MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16244MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16244GX
(Note 1)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
74LVTH16244MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16244MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: BGA package available in Tape and Reel only.
Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation
DS500151
www.fairchildsemi.com
74LVT16244 • 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs
March 1999
74LVT16244 • 74LVTH16244
Connection Diagrams
Pin Descriptions
Pin Names
Pin Assignment for SSOP and TSSOP
Description
OEn
Output Enable Inputs (Active LOW)
I0–I15
Inputs
O0–O15
Outputs
NC
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
O0
NC
OE1
OE2
NC
I0
B
O2
O1
NC
NC
I1
I2
C
O4
O3
VCC
VCC
I3
I4
D
O6
O5
GND
GND
I5
I6
E
O8
O7
GND
GND
I7
I8
F
O10
O9
GND
GND
I9
I10
I12
G
O12
O11
VCC
VCC
I11
H
O14
O13
NC
NC
I13
I14
J
O15
NC
OE4
OE3
NC
I15
Truth Table
Inputs
Pin Assignment for FBGA
Outputs
OE1
I0–I3
L
L
L
L
H
H
H
X
Inputs
I4–I7
L
L
L
L
H
H
X
Inputs
Logic Diagram
Z
Outputs
OE2
H
(Top Thru View)
O0–O3
O4–O7
Z
Outputs
OE3
I8–I11
L
L
L
L
H
H
H
X
Inputs
O8–O11
Z
Outputs
OE4
I12–I15
L
L
L
L
H
H
H
X
Z
O12–O15
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance
Functional Description
The LVT16244 and LVTH16244 contain sixteen non-inverting buffers with 3-STATE outputs. The device is nibble
(4-bits) controlled with each nibble functioning identically,
but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation.
www.fairchildsemi.com
2
Symbol
Parameter
Value
Conditions
Units
VCC
Supply Voltage
−0.5 to +4.6
VI
DC Input Voltage
−0.5 to +7.0
VO
Output Voltage
−0.5 to +7.0
Output in 3-STATE
−0.5 to +7.0
Output in HIGH or LOW State (Note 4)
V
V
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
IO
DC Output Current
64
VO > VCC Output at HIGH State
128
VO > VCC Output at LOW State
mA
ICC
DC Supply Current per Supply Pin
±64
mA
IGND
DC Ground Current per Ground Pin
±128
mA
TSTG
Storage Temperature
−65 to +150
°C
Recommended Operating Conditions
Symbol
Parameter
Min
Max
2.7
3.6
V
0
5.5
V
HIGH Level Output Current
−32
mA
LOW Level Output Current
64
mA
VCC
Supply Voltage
VI
Input Voltage
IOH
IOL
TA
Free Air Operating Temperature
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
Units
−40
+85
°C
0
10
ns/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
TA = −40°C to +85°C
VCC
Parameter
(V)
Min
Input Clamp Diode Voltage
VIH
Input HIGH Voltage
2.7–3.6
VIL
Input LOW Voltage
2.7–3.6
VOH
Output HIGH Voltage
2.7–3.6
VCC − 0.2
2.7
2.4
3.0
2.0
VOL
II(HOLD)
2.7
Output LOW Voltage
Bushold Input Minimum Drive
II(OD)
Bushold Input Over-Drive
(Note 5)
Current to Change State
II
Input Current
Data Pins
IOFF
Power Off Leakage Current
IPU/PD
Power Up/Down
3-STATE Current
0.8
Conditions
V
II = −18 mA
V
VO ≤ 0.1V or
V
VO ≥ VCC − 0.1V
V
IOH = −8 mA
IOH = −100 µA
IOH = −32 mA
0.2
IOL = 100 µA
2.7
0.5
IOL = 24 mA
3.0
0.4
3.0
0.5
IOL = 32 mA
3.0
0.55
IOL = 64 mA
75
500
µA
−500
3.6
10
3.6
±1
−5
3.6
V
µA
−75
3.0
Control Pins
2.0
Units
2.7
3.0
(Note 5)
Max
−1.2
VIK
IOL = 16 mA
VI = 0.8V
VI = 2.0V
(Note 6)
(Note 7)
VI = 5.5V
µA
VI = 0V or VCC
VI = 0V
VI = V CC
1
0
±100
µA
0V ≤ VI or VO ≤ 5.5V
0 – 1.5V
±100
µA
−5
µA
VO = 0.5V
VO = 0.5V to 3.0V
VI = GND or VCC
IOZL
3-STATE Output Leakage Current
3.6
IOZH
3-STATE Output Leakage Current
3.6
5
µA
VO = 3.0V
IOZH+
3-STATE Output Leakage Current
3.6
10
µA
VCC < VO ≤ 5.5V
3
www.fairchildsemi.com
74LVT16244 • 74LVTH16244
Absolute Maximum Ratings(Note 3)
74LVT16244 • 74LVTH16244
DC Electrical Characteristics
Symbol
(Continued)
TA = −40°C to +85°C
VCC
Parameter
(V)
Min
Units
Conditions
Max
ICCH
Power Supply Current
3.6
0.19
mA
ICCL
Power Supply Current
3.6
5.0
mA
Outputs High
Outputs Low
ICCZ
Power Supply Current
3.6
0.19
mA
Outputs Disabled
ICCZ+
Power Supply Current
3.6
0.19
mA
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
∆ICC
Increase in Power Supply Current
3.6
0.2
mA
One Input at VCC − 0.6V
Other Inputs at VCC or GND
(Note 8)
Note 5: Applies to bushold versions only (LVTH16244).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol
Parameter
(Note 9)
TA = 25°C
VCC
(V)
Min
Typ
Max
Conditions
Units
CL = 50 pF, RL = 500Ω
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
V
(Note 10)
VOLV
Quiet Output Minimum Dynamic VOL
3.3
−0.8
V
(Note 10)
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = −40°C to +85°C
Symbol
tPLH
CL = 50 pF, RL = 500Ω
Parameter
VCC = 3.3V ± 0.3V
Propagation Delay Data to Output
tPHL
tPZH
Output Enable Time
tPZL
tPHZ
Output Disable Time
tPLZ
tOSHL
Output to Output Skew
tOSLH
(Note 11)
Units
VCC = 2.7V
Min
Max
Min
Max
1.2
3.5
1.2
3.9
1.2
3.5
1.2
3.9
1.2
4.0
1.2
5.0
1.2
5.0
1.2
6.5
2.0
4.7
2.0
5.2
1.5
4.2
1.5
4.4
1.0
1.0
ns
ns
ns
ns
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance
Symbol
(Note 12)
Typical
Units
CIN
Input Capacitance
Parameter
VCC = 0V, VI = 0V or VCC
Conditions
4
pF
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
8
pF
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
www.fairchildsemi.com
4
74LVT16244 • 74LVTH16244
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
5
www.fairchildsemi.com
74LVT16244 • 74LVTH16244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
www.fairchildsemi.com
6
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
www.fairchildsemi.com
7
www.fairchildsemi.com
74LVT16244 • 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)