HY531000A 1Mx1, Fast Page mode DESCRIPTION This family is a 1M bit dynamic RAM organized 1,048,576 x 1-bit configuration with Fast Page mode CMOS DRAMs. Fast Page mode offers high speed of random access memory within the same row. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70 or 80ns) and power consumption (Normal or Low power). Hyundai’s advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. FEATURES Ÿ Fast Page Mode operation Ÿ Read-modify-write Capability Ÿ TTL compatible inputs and outputs Ÿ /CAS-before-/RAS, /RAS-only, Hidden and Self refresh capability Ÿ Max. Active power dissipation Ÿ JEDEC standard pinout Ÿ 20/26-pin SOJ (300mil) Ÿ Single power supply of 5V ± 10% Ÿ Early Write or output enable controlled write Ÿ Fast access time and cycle time Speed Power Speed tRAC tCAC tPC 60 467mW 60 60ns 15ns 40ns 70 412mW 70 70ns 20ns 40ns 80 357mW 80 80ns 20ns 45ns Ÿ Refresh cycle Part number Refresh Normal L-part HY531000A 512 8ms 64ms ORDERING INFORMATION Part Name Refresh HY531000AJ 512 HY531000ALJ 512 Power Package 20/26Pin SOJ L-part 20/26Pin SOJ *L : Low power This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Hyundai Semiconductor Rev.10 / Jan.98 1 HY531000A FUNCTIONAL BLOCK DIAGRAM D Q Data Input Buffer Data Output Buffer OE WE CAS CAS Clock Generator A0 Cloumn Predecoder (10) A1 10 Column Decoder A3 A4 A5 A6 Address Buffer A2 Sense Amp I/O Gate Refresh Controller Refresh Counter (9) Row Decoder A7 A8 A9 RAS Memory Array 1,048,576 x 1 9 Row Predecoder (10) RAS Clock Generator Substrate Bias Generator 1Mx1,FP DRAM Rev.10 / Jan.98 2 VCC VSS HY531000A PIN CONFIGURATION (Marking Side) D 1 26 VSS WE 2 25 D RAS 3 24 CAS NC 4 23 NC 5 22 NC A9 A0 9 18 A8 A1 10 17 A7 A2 11 16 A6 A3 12 15 A5 Vcc 13 14 A4 20/26 Pin Plastic SOJ (300mil) PIN DESCRIPTION Pin Name Parameter /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable /OE Output Enable A0~A9 Address Input D Data Input Q Data Output Vcc Power (5V) Vss Ground 1Mx1,FP DRAM Rev.10 / Jan.98 3 HY531000A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Rating Unit TA Ambient Temperature 0 to 70 °C TSTG Storage Temperature -55 to 150 °C VIN, VOUT Voltage on Any Pin relative to VSS -1.0 to 7.0 V VCC Voltage on VCC relative to VSS -1.0 to 7.0 V IOS Short Circuit Output Current 50 mA PD Power Dissipation 0.9 W TSOLDER Soldering Temperature Ÿ Time 260 Ÿ 10 °C Ÿ sec Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to 70°C ) Symbol Parameter Min Typ Max UNIT VCC Power Supply Voltage 4.5 5.0 5.5 V VIH Input High Voltage 2.4 - VCC+1.0 V VIL Input Low Voltage -1.0 - 0.8 V Note : All voltages are referenced to VSS. DC OPERATING CHARACTERISTICS Symbol Parameter Test condition Min Max Unit ILI Input Leakage Current (Any input) VSS ≤ VIN ≤ VCC All other pins not under test = VSS -10 10 µA ILO Output Leakage Current (Any input) VSS ≤ VOUT ≤ VCC /RAS & /CAS at VIH -10 10 µA VOL Output Low Voltage IOL = 4.2mA - 0.4 V VOH Output High Voltage IOH = -5.0mA 2.4 - V 1Mx1,FP DRAM Rev.10 / Jan.98 4 HY531000A DC CHARACTERISTICS (TA = 0°C to 70°C , VCC = 5V ± 10%, VSS = 0V, unless otherwise noted.) Symbol Parameter Test condition Speed Max. Unit 60 70 80 85 75 65 mA 2 mA ICC1 Operating Current /RAS, /CAS Cycling tRC = tRC(min) ICC2 TTL Standby Current /RAS, /CAS ≥ VIH(min) Other inputs ≥ VSS ICC3 /RAS-only Refresh Current /RAS Cycling,/CAS = VIH tRC = tRC(min) 60 70 80 85 75 65 mA ICC4 Fast Page mode Current /CAS Cycling, /RAS = VIL tPC = tPC(min) 60 70 80 70 55 45 mA ICC5 CMOS Standby Current /RAS = /CAS ≥ VCC - 0.2V L-part 1 200 mA µA ICC6 /CAS-before-/RAS Refresh Current /RAS & /CAS = 0.2V tRC = tRC(min.) 60 70 80 85 75 65 mA ICC7 Battery Back-up Current (L-part) tRAS ≤ 300ns 300 tRAS ≤ 1us 400 tRC=125µs /CAS = CBR cycling or 0.2V /OE & /WE = VCC - 0.2V Address = Vcc-0.2V or 0.2V D = Vcc-0.2, 0.2V or Open Q = open µA Note 1. ICC1, ICC3, ICC4, ICC6 and Icc7 depend on output loading and cycle rates. 2. Specified values are obtained with output unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one cycle time tPC. 4. Only tRAS(max) = 1µs is applied to refresh of battery backup but tRAS(max) = 10µs is to applied to normal functional operation. 5. Icc5(max.), Icc7 are applied to L-part only. 1Mx1,FP DRAM Rev.10 / Jan.98 5 HY531000A AC CHARACTERISTICS (TA = 0 °C to 70 °C, VCC = 5V ± 10% , VSS = 0V, unless otherwise noted.) 70ns 60ns Symbol 80ns Parameter Unit Min Max Min Max Min Max Note tRC Random read or write cycle time 110 - 130 - 150 - ns tRWC Read-modify-write cycle time 130 - 155 - 175 - ns tPC Fast Page mode cycle time 40 - 40 - 45 - ns tPRWC Fast Page mode read-modify-write cycle time 60 - 65 - 70 - ns tRAC Access time from /RAS - 60 - 70 - 80 ns 4,9,10 tCAC Access time from /CAS - 15 - 20 - 20 ns 4,9 tAA Access time from column address - 30 - 35 - 40 ns 4,10 tCPA Access time from /CAS precharge - 35 - 35 - 40 ns 4, tCLZ /CAS to output low impedance 0 - 0 - 0 - ns 4 tOFF Output Buffer Turn-off Dealy Time 0 20 0 20 0 20 ns 4 tT Transition time(rise and fall) 3 50 3 50 3 50 ns 3 tRP /RAS precharge time 40 - 50 - 60 - ns tRAS /RAS pulse width 60 10K 70 10K 80 10K ns tRASP /RAS pulse width(Fast Page Mode) 60 100K 70 100K 80 100K ns tRSH /RAS hold time 15 - 20 - 20 - ns tCSH /CAS hold time 60 - 70 - 80 - ns tCAS /CAS pulse width 15 10K 15 10K 20 10K ns tRCD /RAS to /CAS delay time 20 45 20 50 20 60 ns 9 tRAD /RAS to column address delay time 15 30 15 35 15 40 ns 10 tCRP /CAS to /RAS precharge time 5 - 5 - 5 - ns 15 tCP /CAS precharge time 10 - 10 - 10 - ns 17 tASR Row address set-up time 0 - 0 - 0 - ns tRAH Row address hold time 10 - 10 - 10 - ns tASC Column address set-up time 0 - 0 - 0 - ns tCAH Column address hold time 15 - 15 - 15 - ns tAR Column address hold time from /CAS 45 - 50 - 55 - ns tRAL Column address to /RAS lead time 25 - 30 - 35 - ns tRCS Read command set-up time 0 - 0 - 0 - ns tRCH Read command hold time referenced to /CAS 0 - 0 - 0 - ns 6 tRRH Read command hold time referenced to /RAS 0 - 0 - 0 - ns 6 tWCH Write command hold time 15 - 15 - 15 - ns tWCR Write command hold time from /RAS 45 - 50 - 55 - ns tWP Write command pulse width 10 - 15 - 15 - ns tRWL Write command to /RAS lead time 15 - 20 - 20 - ns 1Mx1,FP DRAM Rev.10 / Jan.98 6 13 HY531000A AC CHARACTERISTICS Continued 70ns 60ns Symbol 80ns Parameter Unit Min Max Min Max Min Max Note tCWL Write command to /CAS lead time 15 - 20 - 20 - ns tDS Data-in set-up time 0 - 0 - 0 - ns 7 tDH Data-in hold time 15 - 15 - 15 - ns 7 Refresh period(512 cycles) 8 - 8 - 8 - ms 11 Refresh period(L-part) 64 - 64 - 64 - ms 11 tWCS Write command set-up time 0 - 0 - 0 - ns 8 tCWD /CAS to /WE delay time 15 - 20 - 20 - ns 8 tRWD /RAS to /WE delay time 60 - 70 - 80 - ns 8 tAWD Column address to /WE delay time 30 - 35 - 40 - ns 8 tCSR /CAS set-up time(CBR cycle) 5 - 5 - 5 - ns tCHR /CAS hold time(CBR cycle) 15 - 15 - 15 - ns tRPC /RAS to /CAS precharge time 0 - 0 - 0 - ns tCPT /CAS precharge time(CBR counter test) 40 - 40 - 40 - ns tCPWD /WE delay time from /CAS precharge 30 - 35 - 40 - ns tRHCP /RAS hold time from /CAS precharge 30 - 35 - 35 - ns tREF 1Mx1,FP DRAM Rev.10 / Jan.98 7 8 HY531000A NOTE 1. An initial pause of 200µs is required after power-up followed by 8 /RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of 8 /RAS-only refresh cycles are required. 2. AC measurements assume tT=5ns 3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.). 4. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 100pF. 5. tOFF(max.) defines the time at which the output achieves in early write cycles and to /WE leading edge in ReadModify-Write cycles. 6. Either tRCH or tRRH must be satisfied for a read cycle. 7. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in read-modify-write cycles. 8. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min), and tCPWD ≥ tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 9. Operation within the tRCD(max.) limit insures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD(max.) limit insures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 11.tREF(max.)=64ms is applied to L-parts only.(HY531000ALS and HY531000ALJ) CAPACITANCE (TA = 25°C, VCC = 5V ± 10%, VSS = 0V and f=1MHz, unless otherwise noted.) Symbol Parameter Typ. Max Unit CIN1 Input Capacitance (A0~A9) - 5 pF CIN2 Input Capacitance (/RAS, /CAS, /WE) - 7 pF COUT Data Output Capacitance (Q) - 7 pF 1Mx1,FP DRAM Rev.10 / Jan.98 8