ETC 71M6542G

71M6541D/F/G 和 71M6542F/G
电表 IC
数据资料
概述
特性
71M6541D/71M6541F/71M6541G/71M6542F/71M6542G
是
TeridianTM 的第 4 代高集成度单相电表 SoC,包括:8051 兼容 MPU、
带有数字补偿的低功耗实时时钟(RTC)、闪存存储器和 LCD 驱动器。
采用我们的单转换器技术(Single Converter Technology®),内置一路
22 位 Σ-Δ ADC 数字温度传感器、三路或四路模拟输入、数字温度补
偿、精密电压基准和 32 位计算引擎(CE),只需少数外部元件即可支
持各种电表设计。
• 2000:1 电流范围内,精度高达 0.1%
71M6541/2 支持 Teridian 71M6x01 系列隔离传感器的接口选项,有
效降低 BOM 成本、提高抗电磁干扰能力,进而增强系统可靠性。其
它特性包括:SPI 接口、先进的电源管理、超低功耗有效工作和电池
供电模式、3/5KB 公用 RAM 和 32/64/128KB 闪存存储器(电表工作期
间可现场编程程序和/或数据)、每个 SEG 驱动端能够驱动六段 LCD。
较高的处理和采样速率结合差分输入级,提供强大的计量功能,理想
用于住宅表设计。
完整的软件开发工具、演示程序以及参考设计有助于加速计量产品的
开发和认证,以满足 ANSI、IEC 等全球范围的电表计量标准。
NEUTRAL
Shunt
Note:
This system is referenced to LINE
Shunt
LINE
NEUTRAL
• 一路电流输入可选择增益 1 或 8,支持分流器
• 高速 Wh/VARh 脉冲输出,可编程脉冲宽度
• 32KB 闪存、3KB RAM (71M6541D)
• 64KB 闪存、5KB RAM (71M6541F/42F)
• 128KB 闪存、5KB RAM (71M6541G/42G)
• 多达四路脉冲输出,带有脉冲计数
• 四象限表计
• 数字温度补偿:
-
计量补偿
-
高 精 度 RTC , 用 于 晶 振 自 动 温 度 补 偿 的
TOU 功能,支持所有功率模式
• 独立 32 位计算引擎
TERIDIAN
71M6xx1
MUX and ADC
TERIDIAN
WAKE-UP
71M6541D/F
REGULATOR
• 闪存加密
BATTERY
VBAT
VA
VBAT_RTC
IBP
IBN
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
AMR
IR
TX
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
RAM
COMPUTE
ENGINE
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
ICE
8888.8888
• LCD 驱动器:
- 每引脚驱动 6 段/多达 56 个引脚
• 5V LCD 驱动器,带有 DAC
I2C or µWire
EEPROM
• 多达 51 个多功能 DIO 引脚
11/5/2010
Teridian 和 Single Converter Technology 分别是 Maxim Integrated Products, Inc.的商标和
MICROWIRE 是 National Semiconductor Corp.的注册商标。
• 8 位 MPU (80515),高达 5 MIPS
PULSES,
DIO
XOUT
注册商标。
• 在系统编程
• 掉电模式下的全速 MPU 时钟
LCD DISPLAY
32 kHz
SPI INTERFACE
掉电模式(BRN)
LCD 模式(LCD)
休眠模式(SLP)
• 休眠模式电流损耗仅为 1μA
PWR MODE
CONTROL
Pulse
Transformer
• 三种备份电池供电模式:
• 引脚事件唤醒和定时器唤醒
V3P3A V3P3SYS GNDA GNDD
IAP
IAN
• 相位补偿(±10°)
-
POWER SUPPLY
LINE
Resistor Divider
• 两路电流传感器输入,可选择差分模式
• 46-64Hz 电网频率范围,采用相同校准
LOAD
LINE
• 优于 IEC 62053/ANSI C12.20 标准要求
• 硬件看门狗定时器(WDT)
• I2C/MICROWIRE® EEPROM 接口
• SPI 接口,具有闪存编程能力
• 两个 UART 用于 IR 和 AMR
• 带有调制功能的 IR LED 驱动器
• 工业级温度范围
• 64
引 脚 (71M6541D/F/G) 和 100
(71M6542F/G)无铅(Pb) LQFP 封装
Rev 2
引 脚
1
71M6541D/F/G 和 71M6542F/G 数据资料
目录
1
2
3
2
引言 ..................................................................................................................................................... 10
硬件说明 .............................................................................................................................................. 11
2.1 硬件概述 ..................................................................................................................................... 11
2.2 模拟前端(AFE) ........................................................................................................................... 12
2.2.1 信号输入引脚 ................................................................................................................. 14
2.2.2 输入复用器 ..................................................................................................................... 15
2.2.3 延迟补偿......................................................................................................................... 19
2.2.4 ADC 前置放大器............................................................................................................. 20
2.2.5 A/D 转换器(ADC) ........................................................................................................... 20
2.2.6 FIR 滤波器...................................................................................................................... 20
2.2.7 电压基准......................................................................................................................... 20
2.2.8 71M6x01 隔离传感器接口(远端传感器接口) .................................................................. 22
2.3 数字计算引擎(CE) ...................................................................................................................... 24
2.3.1 CE 程序存储器 ............................................................................................................... 24
2.3.2 CE 数据存储器 ............................................................................................................... 24
2.3.3 CE 与 MPU 通信............................................................................................................. 25
2.3.4 电表公式......................................................................................................................... 25
2.3.5 实时监测器(RTM) ........................................................................................................... 25
2.3.6 脉冲发生器 ..................................................................................................................... 27
2.3.7 CE 功能概述 ................................................................................................................... 28
2.4 80515 MPU 核 ............................................................................................................................ 31
2.4.1 存储器架构和寻址 .......................................................................................................... 31
2.4.2 特殊功能寄存器(SFR) .................................................................................................... 33
2.4.3 通用 80515 特殊功能寄存器 ........................................................................................... 34
2.4.4 指令集 ............................................................................................................................ 36
2.4.5 UART ............................................................................................................................. 36
2.4.6 定时器和计数器 .............................................................................................................. 39
2.4.7 WD 定时器(软件看门狗定时器) ...................................................................................... 40
2.4.8 中断 ................................................................................................................................ 40
2.5 片上资源 ..................................................................................................................................... 48
2.5.1 物理存储器 ..................................................................................................................... 48
2.5.2 振荡器 ............................................................................................................................ 50
2.5.3 PLL 和内部时钟 .............................................................................................................. 50
2.5.4 实时时钟(RTC) ............................................................................................................... 51
2.5.5 71M654x 温度传感器 ..................................................................................................... 56
2.5.6 71M654x 电池监测器 ..................................................................................................... 57
2.5.7 UART 和光接口 .............................................................................................................. 58
2.5.8 数字 I/O 和 LCD 段驱动器 .............................................................................................. 59
2.5.9 EEPROM 接口 ............................................................................................................... 70
2.5.10 SPI 从机端口 .................................................................................................................. 73
2.5.11 硬件看门狗定时器 .......................................................................................................... 78
2.5.12 测试端口(TMUXOUT 和 TMUX2OUT 引脚) ................................................................... 78
功能说明 .............................................................................................................................................. 80
3.1 工作原理 ..................................................................................................................................... 80
3.2 电池供电模式 ............................................................................................................................. 81
3.2.1 BRN 模式 ....................................................................................................................... 83
3.2.2 LCD 模式 ........................................................................................................................ 83
3.2.3 SLP 模式 ........................................................................................................................ 84
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
故障和复位操作 .......................................................................................................................... 85
3.3.1 掉电事件......................................................................................................................... 85
3.3.2 低电池电压下的 IC ......................................................................................................... 86
3.3.3 复位序列......................................................................................................................... 86
3.3.4 看门狗定时器复位 .......................................................................................................... 86
3.4 唤醒操作 ..................................................................................................................................... 87
3.4.1 硬件唤醒事件 ................................................................................................................. 87
3.4.2 定时器唤醒 ..................................................................................................................... 90
3.5 数据流和 MPU/CE 通信 .............................................................................................................. 91
应用信息 .............................................................................................................................................. 92
4.1 连接 5V 器件............................................................................................................................... 92
4.2 直接连接传感器 .......................................................................................................................... 92
4.3 使用本地传感器的 71M6541D/F/G............................................................................................. 93
4.4 使用 71M6x01 和电流分流器的 71M6541D/F/G ........................................................................ 94
4.5 使用本地传感器的 71M6542F/G ................................................................................................ 95
4.6 使用 71M6x01 和电流分流器的 71M6542F/G ............................................................................ 96
4.7 计量温度补偿 ............................................................................................................................. 97
4.7.1 高精度电压基准 .............................................................................................................. 97
4.7.2 71M654x 的温度系数 ..................................................................................................... 97
4.7.3 VREF 温度补偿,使用本地传感器 ................................................................................. 98
4.7.4 VREF 温度补偿,使用远端传感器 ................................................................................. 99
4.8 连接 I2C EEPROM ................................................................................................................... 100
4.9 连接 3 线 EEPROM .................................................................................................................. 101
4.10 UART0 (TX/RX) ....................................................................................................................... 101
4.11 光接口(UART1) ........................................................................................................................ 101
4.12 连接复位引脚 ........................................................................................................................... 102
4.13 连接仿真器端口 ........................................................................................................................ 102
4.14 闪存编程 ................................................................................................................................... 104
4.14.1 通过 ICE 端口编程闪存 ................................................................................................ 104
4.14.2 通过 SPI 端口编程闪存................................................................................................. 104
4.15 MPU 固件库 ............................................................................................................................. 104
4.16 晶振 .......................................................................................................................................... 104
4.17 电表校准 ................................................................................................................................... 104
固件接口 ............................................................................................................................................ 105
5.1 I/O RAM 映射—按功能排序...................................................................................................... 105
5.2 I/O RAM 映射—按字母排序...................................................................................................... 111
5.3 CE 接口说明 ............................................................................................................................. 125
5.3.1 CE 程序 ........................................................................................................................ 125
5.3.2 CE 数据格式 ................................................................................................................. 125
5.3.3 常量 .............................................................................................................................. 125
5.3.4 环境 .............................................................................................................................. 126
5.3.5 CE 计算 ........................................................................................................................ 126
5.3.6 CE 前端数据(原始数据) ................................................................................................ 127
5.3.7 FCE 状态和控制 ........................................................................................................... 127
5.3.8 CE 传递变量 ................................................................................................................. 129
5.3.9 脉冲发生器 ................................................................................................................... 132
5.3.10 其它 CE 参数 ................................................................................................................ 134
5.3.11 CE 校准参数 ................................................................................................................. 135
5.3.12 CE 流程图 .................................................................................................................... 136
电气规格 ............................................................................................................................................ 138
3.3
4
5
6
Rev 2
3
71M6541D/F/G 和 71M6542F/G 数据资料
绝对最大额定值 ........................................................................................................................ 138
推荐外部元件 ........................................................................................................................... 139
推荐工作条件 ........................................................................................................................... 139
性能指标 ................................................................................................................................... 140
6.4.1 输入逻辑电平 ............................................................................................................... 140
6.4.2 输出逻辑电平 ............................................................................................................... 140
6.4.3 电池监测器 ................................................................................................................... 141
6.4.4 温度监测器 ................................................................................................................... 141
6.4.5 电源电流....................................................................................................................... 142
6.4.6 V3P3D 开关.................................................................................................................. 143
6.4.7 内部电源故障比较器 .................................................................................................... 143
6.4.8 2.5V 稳压器—系统电源 ................................................................................................ 143
6.4.9 2.5V 稳压器—电池供电 ................................................................................................ 144
6.4.10 晶振 .............................................................................................................................. 144
6.4.11 锁相环(PLL) ................................................................................................................. 144
6.4.12 LCD 驱动器 .................................................................................................................. 145
6.4.13 VLCD 发生器 ................................................................................................................ 146
6.4.14 VREF ........................................................................................................................... 148
6.4.15 ADC 转换器 .................................................................................................................. 149
6.4.16 IAP-IAN 前置放大器 ..................................................................................................... 150
6.5 时序规格 ................................................................................................................................... 151
6.5.1 闪存 .............................................................................................................................. 151
6.5.2 SPI 从机 ....................................................................................................................... 151
6.5.3 EEPROM 接口 ............................................................................................................. 151
6.5.4 RESET 引脚 ................................................................................................................. 152
6.5.5 RTC.............................................................................................................................. 152
6.6 封装图 ...................................................................................................................................... 153
6.6.1 64 引脚 LQFP 封装图 ................................................................................................... 153
6.6.2 100 引脚 LQFP 封装图 ................................................................................................. 154
6.7 封装标识 ................................................................................................................................... 155
6.8 引脚图 ...................................................................................................................................... 156
6.8.1 71M6541D/F/G LQFP-64 封装引脚排列 ...................................................................... 156
6.8.2 71M6542F/G LQFP-100 封装引脚排列 ........................................................................ 157
6.9 引脚说明 ................................................................................................................................... 158
6.9.1 电源和接地引脚 ............................................................................................................ 158
6.9.2 模拟电路引脚 ............................................................................................................... 159
6.9.3 数字电路引脚 ............................................................................................................... 160
6.9.4 I/O 等效电路 ................................................................................................................. 162
7
定购信息 ............................................................................................................................................ 163
7.1 71M6541D/F/G 和 71M6542F/G .............................................................................................. 163
8
相关信息 ............................................................................................................................................ 163
9
联络信息 ............................................................................................................................................ 163
附录 A:缩写符号 ..................................................................................................................................... 164
附录 B:修订历史 ..................................................................................................................................... 165
6.1
6.2
6.3
6.4
4
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
图
图 1. IC 功能框图 ................................................................................................................................................... 9
图 2. 71M6541D/F/G AFE 方框图(本地传感器) ................................................................................................... 12
图 3. 71M6541D/F/G AFE 方框图(带 71M6x01) .................................................................................................. 13
图 4. 71M6542F/G AFE 方框图(本地传感器) ....................................................................................................... 13
图 5. 71M6542F/G AFE 方框图(带 71M6x01) ..................................................................................................... 14
图 6. 复用帧状态(MUX_DIV[3:0] = 3) .................................................................................................................. 17
图 7. 复用帧状态(MUX_DIV[3:0] = 4) .................................................................................................................. 17
图 8. 斩波放大器通用拓扑 ................................................................................................................................... 21
图 9. CROSS 信号,CHOP_E = 00 ..................................................................................................................... 21
图 10. RTM 时序 .................................................................................................................................................. 26
图 11. ADC MUX、CE 和 RTM 串行传输时序关系 .............................................................................................. 26
图 12. 脉冲发生器 FIFO 时序 ............................................................................................................................... 28
图 13. 累积间隔 ................................................................................................................................................... 29
图 14. 复用周期内采样(MUX_DIV[3:0] = 3) ......................................................................................................... 30
图 15. 复用周期内采样(MUX_DIV[3:0] = 4) ......................................................................................................... 30
图 16. 中断结构 ................................................................................................................................................... 47
图 17. 自动温度补偿 ............................................................................................................................................ 54
图 18. 光接口 ....................................................................................................................................................... 58
图 19. 光接口(UART1) ......................................................................................................................................... 59
图 20. 连接外部负载至 DIO 引脚 ......................................................................................................................... 60
图 21. LCD 波形................................................................................................................................................... 68
图 22. 3 线接口:写命令,HiZ=0 ........................................................................................................................ 72
图 23. 3 线接口:写命令,HiZ=1 ........................................................................................................................ 72
图 24. 3 线接口:读命令 ...................................................................................................................................... 72
图 25. 3 线接口:写命令,CNT=0 ....................................................................................................................... 73
图 26. 3 线接口:写命令,HiZ=1,WFR=1......................................................................................................... 73
图 27. PI 从机端口—典型的多字节读、写操作 .................................................................................................... 75
图 28. 电压、电流、瞬时能量和累积能量 ............................................................................................................ 80
图 29. Operation 工作模式状态图 ........................................................................................................................ 81
图 30. MPU/CE 数据流 ........................................................................................................................................ 91
图 31. 电阻分压(电压检测)................................................................................................................................... 92
图 32. 单端输入 CT (电流检测) ............................................................................................................................ 92
图 33. 差分输入 CT (电流检测) ............................................................................................................................ 92
图 34. 差分输入锰铜分流器(电流检测)................................................................................................................. 92
图 35. 71M6541D/F/G (本地传感器) .................................................................................................................... 93
图 36. 71M6541D/F/G (71M6x01 远端传感器) .................................................................................................... 94
图 37. 71M6542F/G (本地传感器) ....................................................................................................................... 95
图 38. 71M6542F/G (71M6x01 远端传感器) ........................................................................................................ 96
图 39. I 2C EEPROM 连接 .................................................................................................................................. 101
图 40. UART0 连接 ............................................................................................................................................ 101
图 41. 光元件连接 .............................................................................................................................................. 102
图 42. RESET 引脚外部电路:按钮(左侧)、生产电路(右侧).............................................................................. 102
图 43. 仿真器接口的外部电路 ............................................................................................................................ 103
图 44. CE 数据流:复用器和 ADC ..................................................................................................................... 136
图 45. CE 数据流:缩放、增益控制、中间变量 ................................................................................................ 136
图 46. CE 数据流:平方、求和运算级 ............................................................................................................... 137
图 47. 64 引脚 LQFP 封装 ................................................................................................................................. 153
图 48. 100 引脚 LQFP 封装图 ............................................................................................................................ 154
图 49. 封装标识(示例) ........................................................................................................................................ 155
图 50. 71M6541D/F/G (LQFP-64 封装)引脚排列 ............................................................................................... 156
图 51. 71M6542F/G (LQFP-100 封装)引脚排列 ................................................................................................ 157
图 52. I/O 等效电路 ............................................................................................................................................ 162
Rev 2
5
71M6541D/F/G 和 71M6542F/G 数据资料
表
表 1. 本地传感器所要求的 CE 代码和设置 .................................................................................................. 15
表 2. CE 代码和设置(71M6x01 隔离传感器) ................................................................................................ 16
表 3. ADC 输入配置 .................................................................................................................................... 17
表 4. 复用器和 ADC 配置位 ........................................................................................................................ 19
表 5. RCMD[4:0]位 ...................................................................................................................................... 22
表 6. 远程接口读命令 ................................................................................................................................. 23
表 7. 用于远端传感器的 I/O RAM 控制位 .................................................................................................... 23
表 8. 复用器输入选择 .................................................................................................................................. 25
表 9. CKMPU 时钟频率 ............................................................................................................................... 31
表 10. 存储器映射 ........................................................................................................................................ 32
表 11. 内部数据存储器映射 ......................................................................................................................... 33
表 12. 特殊功能寄存器映射 ......................................................................................................................... 33
表 13. 通用 80515 SFR—地址和复位值 ...................................................................................................... 34
表 14. PSW 位功能(SFR 0xD0) ...................................................................................................................... 35
表 15. 端口寄存器(SEGDIO0-15) ................................................................................................................ 36
表 16. 展宽存储周期宽度 ............................................................................................................................ 36
表 17. 波特率发生器 ................................................................................................................................... 37
表 18. UART 模式 ........................................................................................................................................ 37
表 19. S0CON (UART0)寄存器(SFR 0x98) .................................................................................................. 38
表 20. S1CON (UART1)寄存器(SFR 0x9B) .................................................................................................. 38
表 21. PCON 寄存器位说明(SFR 0x87) ...................................................................................................... 39
表 22. 定时器/计数器模式说明.................................................................................................................... 39
表 23. 定时器/计数器模式组合..................................................................................................................... 39
表 24. TMOD 寄存器位说明 (SFR 0x89)...................................................................................................... 40
表 25. TCON 寄存器位功能(SFR 0x88) ....................................................................................................... 40
表 26. IEN0 位功能(SFR 0xA8) .................................................................................................................... 41
表 27. The IEN1 位功能 (SFR 0xB8) ........................................................................................................... 41
表 28. IEN2 位功能(SFR 0x9A) .................................................................................................................... 42
表 29. TCON 位功能(SFR 0x88) .................................................................................................................. 42
表 30. T2CON 位功能(SFR 0xC8) ............................................................................................................... 42
表 31. IRCON 位功能(SFR 0xC0) ................................................................................................................ 42
表 32. 外部 MPU 中断.................................................................................................................................. 44
表 33. 中断使能和标识位 ............................................................................................................................ 44
表 34. 中断优先级组 .................................................................................................................................... 45
表 35. 中断优先级 ........................................................................................................................................ 45
表 36. 中断优先级寄存器(IP0 和 IP1) ........................................................................................................... 45
表 37. 中断轮询排序 .................................................................................................................................... 46
表 38. 中断向量 ........................................................................................................................................... 46
表 39. 闪存访问 ........................................................................................................................................... 48
表 40. 闪存加密 ........................................................................................................................................... 49
表 41. 时钟系统汇总 .................................................................................................................................... 51
表 42. RTC 控制寄存器 ............................................................................................................................... 52
表 43. 用于 RTC 温度补偿的 I/O RAM 寄存器 ............................................................................................. 53
表 44. NV RAM 温度表结构 ......................................................................................................................... 54
表 45. 用于 RTC 中断的 I/O RAM 寄存器 .................................................................................................... 55
表 46. 用于温度和电池测量的 I/O RAM 寄存器 .......................................................................................... 56
表 47. 通过 DIO_Rn[2:0]位的能够选择的资源 ............................................................................................. 59
6
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
表 48. SEGDIO0 至 SEGDIO14 数据/方向寄存器(71M6541D/F/G) ............................................................ 61
表 49. SEGDIO19 至 SEGDIO27 数据/方向寄存器(71M6541D/F/G) .......................................................... 62
表 50. SEGDIO36-39 至 SEGDIO44-45 数据/方向寄存器(71M6541D/F/G) ............................................... 62
表 51. SEGDIO51 和 SEGDIO55 数据/方向寄存器(71M6541D/F/G) .......................................................... 62
表 52. SEGDIO0 至 SEGDIO15 数据/方向寄存器(71M6542F/G)................................................................ 63
表 53. SEGDIO16 至 SEGDIO31 数据/方向寄存器(71M6542F/G).............................................................. 64
表 54. SEGDIO32 至 SEGDIO45 数据/方向寄存器(71M6542F/G).............................................................. 64
表 55. SEGDIO51 至 SEGDIO55 数据/方向寄存器(71M6542F/G).............................................................. 64
表 56. LCD_VMODE[1:0]配置 .................................................................................................................... 65
表 57. LCD 配置.......................................................................................................................................... 67
表 58. SEG46 至 SEG50 的 71M6541D/F/G LCD 数据寄存器 .................................................................... 69
表 59. SEG46 至 SEG50 的 71M6542F/G LCD 数据寄存器 ....................................................................... 70
表 60. 2 线接口对应的 EECTRL 位 ............................................................................................................... 71
表 61. 3 线接口对应的 EECTRL 位 ............................................................................................................... 71
表 62. SPI 操作字段 ..................................................................................................................................... 74
表 63. SPI 命令时序 ..................................................................................................................................... 75
表 64. SPI 寄存器 ........................................................................................................................................ 76
表 65. TMUX[5:0]选择 ................................................................................................................................. 79
表 66. TMUX2[4:0]选择 ............................................................................................................................... 79
表 67. 电路功能 ........................................................................................................................................... 82
表 68. VSTAT[2:0] (SFR 0xF9[2:0]) .............................................................................................................. 85
表 69. 唤醒使能和标识位 ............................................................................................................................. 87
表 70. 唤醒位 ............................................................................................................................................... 89
表 71. WAKE 标识清除事件......................................................................................................................... 90
表 72. GAIN_ADJn 补偿通道 ....................................................................................................................... 98
表 73. GAIN_ADJn 补偿通道 ..................................................................................................................... 100
表 74. I/O RAM 映射—按功能排序,基本配置 .......................................................................................... 105
表 75. I/O RAM 映射—按功能排序 ............................................................................................................ 107
表 76. I/O RAM 映射—按功能排序 ............................................................................................................ 111
表 77. 标准 CE 代码................................................................................................................................... 125
表 78. CE EQU 公式和单元输入映射 ......................................................................................................... 126
表 79. CE 原始数据访问地址 ..................................................................................................................... 127
表 80. CESTATUS 寄存器 ........................................................................................................................... 127
表 81. CESTATUS (CE RAM 0x80)位定义.................................................................................................... 128
表 82. CECONFIG 寄存器 .......................................................................................................................... 128
表 83. CECONFIG (CE RAM 0x20)位定义................................................................................................... 128
表 84. 跌落门限和增益调节控制 ................................................................................................................ 129
表 85. CE 传递变量(本地传感器) ............................................................................................................... 130
表 86. CE 传递变量(隔离传感器) ............................................................................................................... 130
表 87: CE 能量测量变量(使用本地传感器)................................................................................................. 131
表 88. CE 能量测量变量(隔离传感器) ........................................................................................................ 131
表 89. 其它传递变量 .................................................................................................................................. 132
表 90. CE 脉冲发生参数 ............................................................................................................................ 133
表 91. 用于噪声抑制和代码版本的 CE 参数 .............................................................................................. 134
表 92. CE 校准参数.................................................................................................................................... 135
表 93. 绝对最大额定值 .............................................................................................................................. 138
表 94. 推荐外部元件 .................................................................................................................................. 139
表 95. 推荐工作条件 .................................................................................................................................. 139
Rev 2
7
71M6541D/F/G 和 71M6542F/G 数据资料
表 96. 输入逻辑电平 .................................................................................................................................. 140
表 97. 输出逻辑电平 .................................................................................................................................. 140
表 98. 电池监测器技术指标(TEMP_BAT= 1) .............................................................................................. 141
表 99. 温度监测器 ..................................................................................................................................... 141
表 100. 电源电流指标 ................................................................................................................................ 142
表 101. V3P3D 开关技术指标 .................................................................................................................... 143
表 102. 内部电源故障比较器技术指标 ...................................................................................................... 143
表 103. 2.5V 稳压器技术指标 .................................................................................................................... 143
表 104. 低功耗稳压器技术指标.................................................................................................................. 144
表 105. 晶振指标 ....................................................................................................................................... 144
表 106. PLL 技术指标 ................................................................................................................................ 144
表 107. LCD 驱动器技术指标 .................................................................................................................... 145
表 108. LCD 驱动器技术指标 .................................................................................................................... 146
表 109. VREF 技术指标 ............................................................................................................................. 148
表 110. ADC 转换器技术指标 .................................................................................................................... 149
表 111. 前置放大器技术指标 ..................................................................................................................... 150
表 112. 闪存时序指标 ................................................................................................................................ 151
表 113. SPI 从机指标 ................................................................................................................................. 151
表 114. EEPROM 接口时序 ....................................................................................................................... 151
表 115. RESET 引脚时序 .......................................................................................................................... 152
表 116. RTC 的日期范围 ........................................................................................................................... 152
表 117. 71M6541 封装标识 ....................................................................................................................... 155
表 118. 71M6542 封装标识 ....................................................................................................................... 155
表 119. 电源和接地引脚 ............................................................................................................................ 158
表 120. 模拟电路引脚 ................................................................................................................................ 159
表 121. 数字电路引脚 ................................................................................................................................ 160
表 122. 定购信息 ....................................................................................................................................... 163
8
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
V3P3A
VREF
IAP
IAN
IBP
IBN
VLCD
GNDA GNDD
V3P3SYS
∆Σ
AD CONVERTER
VBIAS
MUX
and
PREAMP
VBIAS
VLCD
Voltage
Boost
FIR
V3P3A
-
V3P3D
+
VREF
VA
VB*
VREF
VBAT
MUX
MUX CTRL
CROSS
Voltage
Regulator
CK32
XIN
XOUT
MCK
PLL
RTCLK (32KHz)
Oscillator
DIV
ADC
CK32
32KHz
32 KHz
4.9 MHZ
CKADC
VDD
CKFIR
4.9 MHz
22
2.5V to logic
CLOCK GEN
CK_4X
MUX
LCD_GEN
CKMPU_2x
MUX_SYNC
WPULSE
VARPULSE
CKCE
< 4.9MHz
LCD DRIVER
RTM
32-bit Compute
Engine
TEST
MODE
CEDATA
32 0x000...0x2FF
CE CONTROL
0x0000...0x13FF
COM0..5
6
SPI
TEST
VLC2
VLC1
VLC0
MEMORY SHARE
MPU RAM
3/5 KB
CE
STRT
SEG Pins
8
PROG
0x000...0x3FF
SEGDIO Pins
DIGITAL I/O
16
XFER BUSY
EEPROM
INTERFACE
CKMPU
< 4.9MHz
2
VARPULSE
I/O RAM
CE_BUSY
WPULSE
PB
VBAT_RTC
RTC
RTCLK
SDCK
RX
MPU
(80515)
UART0
SDOUT
Non-Volatile
CONFIGURATION
RAM
SDIN
TX
OPT_RX/
SEGDIO55
OPTICAL
INTERFACE
CONFIGURATION
RAM
(I/O RAM)
DATA
0x0000...0xFFFF
0x2000...0x20FF
8
OPT_TX/
SEGDIO51/
WPULSE/
VARPULSE
PROGRAM
0x0000...0xFFFF
VBIAS
8
MEMORY
SHARE
0x0000…
0xFFFF
16
CONFIGURATION
PARAMETERS
MPU_RSTZ
CKMPU_2x
RTM
FAULTZ
3
VSTAT
* 71M6542F/G only
EMULATOR
PORT
WAKE
TEMP
SENSOR
FLASH
32/64/128 KB
8
POWER FAULT
DETECTION
RESET
BAT
TEST
TEST MUX
TEST MUX
2
E_RXTX
E_TCLK
E_RST
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
ICE_E
10/11/2011
图 1. IC 功能框图
Rev 2
9
71M6541D/F/G 和 71M6542F/G 数据资料
1
引言
本数据资料介绍了 71M6541D (32KB)、71M6541F (64KB)、71M6541G (128KB)、71M6542F (64KB)和
71M6542G (128KB)第四代 Teridian 单相计量 SoC。以下讨论适用于全部的器件特性或性能时,我们将用
“71M654x”表示;讨论内容仅适用于特定型号的特性或性能时,将标明相应型号。本数据资料还介绍了
配套的 71M6x01 隔离电流传感器器件的基本信息。关于 71M6x01 传感器的更多完整内容,请参见
71M6xxx 的数据资料。
本文介绍了使用本地电流传感器以及配合 71M6x01 隔离电流传感器时,71M654x 的使用方法。利用
71M654x 和 71M6x01 芯片组,可以使用非隔离传感器和隔离分流器构建低成本的单相和两相电能表(使用
分流器),获得这类传感器技术前所未及的性能。71M654x SoC 还支持一个本地连接分流器与一个本地连
接电流变压器(CT)配置,或者是双 CT 配置。
为方便阅读,通常采用超级链接,链接到本文相关的参考图、表格和章节。本文中的所有超级链接均以蓝
色突出显示。本文使用了大量的超级链接,提供详细的参考章节,以增强每一部分的细节描述。为进一步
方便阅读,将文章制作成书签 PDF 格式。
建议读者参考本文第 163 页第 8 章“相关信息”部分列出的文件。
10
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
2
硬件说明
2.1
硬件概述
Teridian 71M6541D/F/G 和 71M6542F/G 单芯片计量 IC 集成了实现固态住宅电表所需的全部功能模块,包
括:
•
•
•
•
•
•
•
•
•
•
•
•
•
模拟前端(AFE),具有 22 位二阶 Σ-Δ ADC
独立的 32 位 DSP 数字计算引擎(CE),实现计量功能
8051 兼容微处理器(MPU),每个时钟周期执行一条指令(80515)
精密电压基准(VREF)
用于数字温度补偿的温度传感器:
- 计量数字温度补偿(MPU)
- RTC 自动数字温度补偿,在任意工作模式下均可使用
LCD 驱动器
RAM 和闪存
实时时钟(RTC)
多种 I/O 引脚
电源故障中断
过零中断
可选的电流传感器接口,用于本地连接传感器及远端传感器(即使用带有检流电阻的 71M6x01 配套 IC)
支持锰铜分流器和电流变压器
器件支持锰铜分流器和电流变压器(CT)电流传感器。锰铜分流器可直接连接至 71M654x 器件,或采用配套
的 71M6x01 隔离 IC 进行隔离,以构成各种单相/分相(71M6541D/F/G)或两相(71M6542F/G)电表配置。采
用低成本、小尺寸脉冲变压器隔离 71M6x01 远端传感器与 71M654x。71M654x 执行与 71M6x01 的双向
数字通信,并通过隔离脉冲变压器为 71M6x01 供电。隔离(远端)分流传感器连接至 71M6x01 的差分输入。
71M6x01 配套隔离器包括:
•
•
•
•
•
•
•
数字隔离通信接口
模拟前端(AFE)
精密电压基准(VREF)
温度传感器(用于数字温度补偿)
全差分分流传感器输入
前置放大器,用于优化分流传感器性能
隔离电源电路,从 71M654x 发送的脉冲获取直流电源
典型应用中,71M654x 的 32 位计算引擎(CE)顺序处理模拟输入引脚的电压输入,以及从外部 71M6x01 远
端传感器获得的采样,并进行计算,测量有功能量(Wh)和无功能量(VARh),以及四象限表计的 A2h 和 V2h。
然后 MPU 存取这些测量值,进一步处理并通过 MPU 的外围器件输出。
除了高级测量功能外,时钟电路允许 71M6541D/F/G 和 71M6542F/G 分时计价(TOU),用于多费率电表以
及防时标窃电或其它篡改事件。测量信息可以显示在工作在低温环境的 3.3V LCD,片上电荷泵用于驱动
5V LCD。灵活的 LCD 段显示功能便于整合现有的定制 LCD。通过软件调节 LCD 段和 DIO 引脚,以满足
各种不同需求。
除了带有温度微调的超高精度电压基准外,片上数字温度补偿机制还包括温度传感器和相关控制,用于修
正温度对测量值和 RTC 精度的影响,以满足 ANSI 和 IEC 标准的要求。与温度相关的外部元件,例如晶振、
电阻分流器、电流变压器(CT)及其相应的信号调理电路,定义其温度特性并编程其修正因子,使得电表在
整个工业温度范围内达到高精度计量的要求。
Rev 2
11
71M6541D/F/G 和 71M6542F/G 数据资料
可利用两个内部 UART 其中之一支持红外 LED,提供内部驱动和检测配置,亦可作为标准 UART 使用。可
选择 38kHz 调制输出。这种灵活性方便了利用 IR 接口实现 AMR 电表的设计,图 1 所示为 IC 方框图。
2.2
模拟前端(AFE)
AFE 作为数据采集系统,由 MPU 控制。使用本地连接的传感器时,如图 2 所示,模拟输入信号(IAP-IAN、
VA、IBP-IBN 和 VB)复用至 ADC 输入并进行采样,采样数据经 FIR 滤波后储存在 CE RAM 中,由 CE 进
行后续处理。MPU 也可以访问 CE 的 RAM 区。
图 6 所示为对应于图 2 的复用器时序,图 35 所示为对应于图 2 的电表配置。
VREF
ILINE
ILINE
IAP
CT
Local
or
Shunt
MUX
VREF
∆Σ ADC
CONVERTER
VREF
IAN
VADC
FIR
CE RAM
22
VADC10 (VA)
IN*
IBP
CT
IBN
71M6541D/F
*IN = Optional Neutral Current
11/5/2010
图 2. 71M6541D/F/G AFE 方框图(本地传感器)
12
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
图 3 所示为 71M6541D/F/G 复用器接口,带有一个本地分流传感器和一个远端电阻分流传感器。如图 3 所
示,远端隔离分流传感器通过 71M6x01 连接,该电流通道的采样不会切换至复用器,而是通过数字隔离接
口直接传送至 71M6541D/F/G,并直接储存在 CE RAM。
图 6 所示为对应于图 3 的复用器时序;图 36 所示为对应于图 3 的电表配置。
VREF
ILINE
IAP
Local
Shunt
∆Σ ADC
CONVERTER
MUX
VREF
VREF
IAN
FIR
VADC
VADC10 (VA)
22
CE RAM
IN*
INP
SP
Remote
Shunt
IBP
71M6x01
SN
IBN
Digital
Isolation
Interface
22
INN
71M6541D/F
11/5/2010
* IN = Optional Neutral Current
图 3. 71M6541D/F/G AFE 方框图(带 71M6x01)
图 4 所示为连接了本地传感器的 71M6542F/G AFE。模式输入信号(IAP-IAN、VA、IBP-IBN 和 VB)复用至
ADC 输入并进行采样,采样数据经 FIR 滤波后储存在 CE RAM 中,由 CE 进行后续处理。MPU 也可以访
问 CE 的 RAM 区。
图 7 所示为对应于图 4 的复用器时序;图 37 所示为对应于图 4 的电表配置。
VREF
IA
IA
IAP
CT
Local
or
Shunt
MUX
VREF
∆Σ ADC
CONVERTER
VREF
IAN
VADC
FIR
CE RAM
22
VADC10 (VA)
VADC9 (VB)
IB
IBP
CT
IBN
71M6542F
11/5/2010
图 4. 71M6542F/G AFE 方框图(本地传感器)
图 5 所示为 71M6542F/G 复用器接口,带有一个本地传感器和一个远端电阻分流传感器。如图 5 所示,远
端隔离分流传感器通过 71M6x01 连接,该电流通道的采样不会切换至复用器,而是通过数字隔离接口直接
传输至 71M6542F/G,并直接储存在 CE RAM。
Rev 2
13
71M6541D/F/G 和 71M6542F/G 数据资料
图 6 所示为对应于图 5 的复用器时序;图 38 所示为对应于图 5 的电表配置。
VREF
IA
IAP
Local
Shunt
∆Σ ADC
CONVERTER
MUX
VREF
VREF
IAN
FIR
VADC
VADC10 (VA)
22
VADC9 (VB)
CE RAM
IB
INP
Remote
Shunt
SP
IBP
71M6x01
SN
IBN
Digital
Isolation
Interface
22
INN
71M6542F
11/5/2010
图 5. 71M6542F/G AFE 方框图(带 71M6x01)
2.2.1
信号输入引脚
71M6541D/F/G 具有 5 路 ADC 输入;71M6542F/G 具有 6 路 ADC 输入。
IAP-IAN 和 IBP-IBN 用作电流传感器输入。这 4 路电流传感器输入可配置为 4 路单端输入,或者配对构成 2
路差分输入。为获得最佳性能,建议将电流传感器输入配置为差分输入(即:IAP-IAN 和 IBP-IBN)。第 1 路
差分输入(IAP-IAN)具有前置放大器,增益可选择 1 或 8,用于直接连接分流电阻传感器,还可使用电流变
压器(CT)。剩下的一路差分对(IBP-IBN)可用于 CT 或连接远端 71M6x01 隔离电流传感器,使用低成本脉冲
变压器为分流电阻传感器提供隔离。
71M6541D/F/G (VA)的其余输入为单端配置,在单相电表应用中按照式 0 或式 1 (见第 25 页 2.3.4 节表计公
式表计公式)检测电网电压。71M6542F/G 具有一路附加的单端电压检测输入(VB),支持式 2 对应的 2 相应
用。这些单端输入以 V3P3A 引脚为参考。
所有模拟信号均以电压方式测量。使用分流传感器时,通过测量分流器两端的电压降测量电流。参见图 3,
分流传感器直接连接至 71M654x (称为“本地”分流传感器),或通过隔离 71M6x01 连接(称为“远端”分流传感
器)。使用电流变压器(CT)时,通过连接至 CT 次级线圈的负载电阻的电压测量电流。同时,通过电阻分压
检测电网电压。VA 和 VB 引脚(VB 仅在 71M6542F/G 中提供)为单端,其公共回路为 V3P3A 引脚。
引脚 IAP-IAN 可独立设置为差分或单端,由 DIFFA_E (I/O RAM 0x210C[4])控制位决定。然而,对于大多数
应用,IAP-IAN 配置为差分输入,结合外部相应的信号调整电路连接至 IAP-IAN (参见第 92 页的 4.2 直接连
接传感器)。
利用 I/O RAM 控制位 PRE_E (I/O RAM 0x2704[5])激活固定增益为 8 的前置放大器,可增强 IAP-IAN 引脚的
性能。PRE_E = 1 时,IAP-IAN 配置为 8x 增益的前置放大器输入,放大器输出送至复用器。使用低灵敏度
电流传感器时,例如锰铜分流器,8x 放大器非常有用。PRE_E 置位时,IAP-IAN 输入信号幅度峰值限制在
250/8 = 31.25mV。
14
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
对于使用两个锰铜分流传感器的 71M654x (图 3),通过置位 DIFFA_E 控制位,将 IAP-IAN 引脚配置成差分
模式,连接至本地分流器。同时,通过置位 RMT_E 控制位(I/O RAM 0x2709[3]),将 IBP-IBN 引脚重新配置
为数字平衡对,用于 Teridian 71M6x01 隔离传感器接口的通信。71M6x01 通过低成本脉冲变压器,利用
双向数据流与 71M654x 进行数据交换。71M654x 还通过隔离变压器为 71M6x01 供电。本章末尾对这一类
型的接口进行了更深入的说明(参见第 2.2.8 节 71M6x01 隔离传感器接口(远端传感器接口))。
如图 2 所示,为了使用电流变压器(CT),将 RMT_E 控制位复位,从而使 IBP-IBN 引脚配置成本地模拟输入。
IAP-IAN 引脚不能配置成远端传感器接口。
2.2.2
输入复用器
使用本地传感器工作时,输入复用器将来自模拟输入引脚的输入信号依次施加到 ADC 的输入(见图 2 和图
4)。一个完整的采样过程称为一个复用帧。71M6541D/F/G 复用器的每个复用帧可选择最多三路输入信号
(IAP-IAN、VA 和 IBP-IBN),由 I/O RAM 控制字段 MUX_DIV[3:0] (I/O RAM 0x2100[7:4])控制(见图 6)。
71M6542F/G 复用器增加了 VB 信号,共支持四路输入(见图 7)。复用器总是从状态 1 开始,然后继续,直
到转换完成 MUX_DIV[3:0]决定的所有状态。
71M6541D/F/G 和 71M6542F/G 均需要针对特定应用编写的 CE 代码。此外,每个 CE 代码都需要特定的
AFE 和 MUX 设置才能正常工作。表 1 列出了与图 2 和图 4 中本地传感器配置相对应的 CE 代码和设置。表
2 列出了与图 3 和图 5 中使用本地/71M6x01/远端传感器配置相对应的 CE 代码和设置。
表 1. 本地传感器所要求的 CE 代码和设置
I/O RAM
助记符
I/O RAM
位置
71M6541D/F/G
(十六进制)
FIR_LEN[1:0]
ADC_DIV
PLL_FAST
MUX_DIV[3:0]
MUX0_SEL[3:0]
MUX1_SEL[3:0]
MUX2_SEL[3:0]
MUX3_SEL[3:0]
RMT_E
DIFFA_E
DIFFB_E
EQU[2:0]
210C[2:1]
2200[5]
2200[4]
2100[7:4]
2105[3:0]
2105[7:4]
2104[3:0]
2104[7:4]
2709[3]
210C[4]
210C[5]
2106[7:5]
CE 代码
公式
----
1
1
1
3
0
A
2
1
0
1
1
0或1
CE41A01
0或1
1 个分流器和 1 个
CT 或 2 个 CT
电流传感器类型
对应电路图
--
图2
71M6542F/G
(十六进制)
Eq. 0 or 1
Eq. 2
1
2
1
0
1
1
3
4
0
0
A
A
2
2
1
9
0
0
1
1
1
1
2
0或1
CE41A01
CE41A04
2
0或1
1 个分流器和 1
1 个分流器和 1
个 CT 或 2 个
个 CT 或 2 个
CT
CT
图4
图4
注:
TERIDIAN 定期更新 CE 代码。关于最新的 CE 代码和相关设置,请联系当地的 TERIDIAN 代表处。本表给出的配置由
MPU 示例代码在初始化期间设置。
Rev 2
15
71M6541D/F/G 和 71M6542F/G 数据资料
表 2. CE 代码和设置(71M6x01 隔离传感器)
I/O RAM
助记符
FIR_LEN[1:0]
ADC_DIV
PLL_FAST
MUX_DIV[3:0]
MUX0_SEL[3:0]
MUX1_SEL[3:0]
MUX2_SEL[3:0]1
MUX3_SEL[3:0]1
RMT_E
DIFFA_E
DIFFB_E
EQU[2:0]
I/O RAM
位置
210C[2:1]
2200[5]
2200[4]
2100[7:4]
2105[3:0]
2105[7:4]
2104[3:0]
2104[7:4]
2709[3]
210C[4]
210C[5]
2106[7:5]
CE 代码
--
公式
--
电流传感器类型
--
对应电路图
--
71M6541D/F/G
71M6542F/G
(十六进制)
(十六进制)
1
1
1
1
1
1
3
3
0
0
A
A
1
9
1
1
1
1
1
1
0
0
0或1
0、1 或 2
CE41B0162012
CE41B0166013
0, 1
0、1 和 2
1 个本地分流器和 1 个本地分流器和
一个远端分离器
一个远端分离器
图3
图5
注:
1. 尽管没有使用,须将其置为 1 (CE 将忽略采样数据)
2. 带 71M6201 远端传感器(200A)的 71M654x
3. 带 71M6601 远端传感器(60A)的 71M654x
Teridian 定期更新 CE 代码。关于最新的 CE 代码和相关设置,请联系当地的 TERIDIAN 代表处。
本表中给出的配置由 MPU 示例代码在初始化期间设置。
如果使用表 1 和表 2 列出的 I/O RAM 助记符设置与对应的 CE 代码不匹配,则会产生负面影响,
MPU 不会选中。请联系当地的 TERIDIAN 代表处获取与之对应的正确 CE 代码和 AFE/MUX 设
置。
对于基本的单相电表,IAP-IAN 电流输入配置为差分模式,而 VA 引脚为单端输入,通常通过电阻分压器连
接到相电压。IBP-IBN 差分输入可选择用于检测零线电流。这种配置意味着复用器将三路输入之和加至
ADC,复用器时序如图 6 所示。这种配置下,采样 IAP-IAN、IBP-IBN 和 VA,额外的转换时隙(即时隙 2)
为可选的零线电流,如果不需要,则可省略测量零线电流的电流传感器。
对于标准防窃电应用,零线电流回路需要安装电流传感器,两路电流输入可配置为差分模式,使用 IAPIAN 和 IBP-IBN 输入对。这意味着复用器将三路输入加至 ADC。在这类应用中,系统设计通过 IAP-IAN 和
IBP-IBN 使用两个本地电流传感器,如图 2 所示,配置为差分输入。或者,IAP-IAN 对配置为差分输入并连
接至本地电流分流器,配置 IBP-IBN 连接隔离的 71M6x01 远端传感器(即 RMT_E = 1),如图 3 所示。VA
引脚通常通过电阻分压器连接至相电压。对于这种配置,复用帧如图 6 所示,时隙 2 不使用,并被 CE 忽
略,因为对应于远端传感器(IBP-IBN)的采样不通过复用器,将直接储存在 CE RAM 中。在复用帧的后半部
分对远端电流传感器采样,并且知道它与 VA 电压的准确采样间隔,以进行正确的延迟补偿。
71M6542F 支持第二相电压(加至 VB 引脚)的计量,非常适合具有两个电压和两个电流传感器的应用,例如,
按照式 2 进行计量的 2 相电表(P = VA*IA+VB*IB)。图 7 所示为利用本地连接传感器处理四路输入(图 3)的
复用器时序。使用一个本地和一个远端传感器(图 5)时,复用器时序与图 7 相同。
16
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
对于图 6 和图 7 所示复用器时序,帧持续时间为 13 个 CK32 周期(其中 CK32 = 32768Hz),因此,采样率
为 32768Hz / 13 = 2520.6Hz。
表 3 汇总了各种 AFE 输入配置。
Multiplexer Frame
Settle
MUX_DIV[3:0] = 3 Conversions
CK32
MUX STATE S
Fig. 2:
Fig. 3:
Fig. 5:
0
IA
IA
IA
1
VA
VA
VA
2
IB
Not Used
VB
S
0
CROSS
MUX_SYNC
11/5/2010
图 6. 复用帧状态(MUX_DIV[3:0] = 3)
Multiplexer Frame
Settle
MUX_DIV = 4 Conversions
CK32
MUX STATE S
Fig. 4:
0
1
2
3
IA
VA
IB
VB
S
0
CROSS
MUX_SYNC
11/5/2010
图 7. 复用帧状态(MUX_DIV[3:0] = 4)
表 3. ADC 输入配置
Rev 2
引脚
ADC
通道
IAP
ADC0
IAN
ADC1
IBP
ADC2
IBN
ADC3
VA
ADC10
VB
ADC9
所需设置
注释
必须通过 DIFFA_E = 1 (I/O RAM 0x210C[4])选择差分模式,
DIFFA_E = 1 ADC 结果储存在 CE RAM 单元 ADC0 (CE RAM 0x0),不会影
响 ADC1 (CE RAM 0x1)。
对 于 本 地 连 接 的 传 感 器 ( 图 2 和 图 4) , 必 须 通 过 置 位
DIFFB_E (I/O RAM 0x210C[5]启用差分输入。
DIFFB_E = 1
对 于 远 端 连 接 的 分 流 器传 感 器 ( 图 3 和 图 5) , 必 须 置 位
or
RMT_E (I/O RAM 0x2709[3])。
RMT_E = 1
无论何种情况,ADC 结果均储存在 CE RAM 单元 ADC2 (CE
RAM 0x2),不会影响 ADC3 (CE RAM 0x3)。
仅限单端模式。ADC 结果储存在 RAM 单元 ADC10 (CE RAM
-0xA)。
仅限单端模式(71M6542F)。ADC 结果储存在 RAM 单元
-ADC9 (CE RAM 0x9)。
17
71M6541D/F/G 和 71M6542F/G 数据资料
复用器切换、FIR 启动以及选择 ADC 基准电压(使用内部 CROSS 信号,参见第 2.2.7 节电压基准)由内部
MUX_CTRL 电路控制。此外,MUX_CTRL 控制每次 CE 代码的执行。从概念上讲,MUX_CTRL 由 PLL
模块的 32768 Hz 时钟 CK32 驱动。下面是 MUX_CTRL 电路管理寄存器:
•
•
•
•
CHOP_E[1:0] (I/O RAM 0x2106[3:2])
MUX_DIV[3:0] (I/O RAM 0x2100[7:4])
FIR_LEN[1:0] (I/O RAM 0x210C[2:1])
ADC_DIV (I/O RAM 0x2200[5])
每个复用器状态的持续时间取决于 FIR 处理的 ADC 采样通道数量,由 FIR_LEN[1:0] (I/O RAM 0x210C[2:1]
控制字段决定。每个复用器状态从 32kHz 时钟 CK32 的上升沿开始。
建议在更改 ADC 配置时将 MUX_DIV[3:0] (I/O RAM 0x2200[2:0])设置为 0,虽然不是必须要求,这样做有
助于将 ADC 输入之间瞬间短路引起的系统瞬变降至最小,特别是在更改 DIFFn_E 控制位(I/O RAM
0x210C[5:4])的情况下。设置该配置位后,MUX_DIV[3:0]应设置在所需要的数值。
此外,可将 ADC 配置为工作在½速率(32768*75 = 2.46MHz)。该模式下,ADC 放大器的偏置电流减小,
总 体 系 统 功 耗 降 低 。 ADC_DIV (I/O RAM 0x2200[5]) 位 选 择 全 速 或 半 速 运 行 。 半 速 运 行 时 , 如 果
FIR_LEN[1:0]设为 01 (288),每次转换需要 4 个 XTAL 周期,MUX_DIV[3:0] = 3 时采样速率为 2520Hz。
注意,为了工作在低功耗模式,需要采用相应的 CE 代码。
CK32 周期中每个时隙的持续时间取决于 FIR_LEN[1:0]、ADC_DIV 和 PLL_FAST。
Time_Slot_Duration (PLL_FAST = 1) = (FIR_LEN[1:0]+1) * (ADC_DIV+1)
Time_Slot_Duration (PLL_FAST = 0) = 3*(FIR_LEN[1:0]+1) * (ADC_DIV+1)
CK32 周期中复用帧的持续时间为:
MUX_Frame_Duration = 3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV[3:0]
CK_FIR 周期中复用帧的持续时间为:
MUX frame duration (CK_FIR cycles) =
[3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV] * (48+PLL_FAST*102)
可通过 MUXx_SEL 控制字段(I/O RAM 0x2100 至 0x2105)编程 ADC 转换时序。如上所述,71M6541D/F/G 中
有三个 ADC 时隙,71M6542F/G 中有四个 ADC 时隙,由 MUX_DIV[3:0] (I/O RAM 0x2100[7:4])设置。表达
式 MUXx_SEL[3:0] = n 中,“x”指复用帧时隙数量,n 指相应的 ADC 输入编号或 ADC 序号(即 ADC0 至
ADC10,或简单的 0 至 10 十进制数)。由此,在 71M654x 器件共有 11 个有效的 ADC 序号。例如,如果
MUX0_SEL[3:0] = 0,那么 ADC0,对应于来自于 IAP-IAN 输入(配置为差分输入)的采样,定位在复用帧的
时隙 0。关于相应的 MUXx_SEL[3:0]设置及适用于特定 CE 代码的其它设置,请参见表 1 和表 2。
注意,启用远程传感器接口时,即使对应于远端传感器电流(IBP-IBN)的采样不通过复用器,也必须采用未
使用的有效 ADC 序号写 MUX2_SEL[3:0]和 MUX3_SEL[3:0]控制字。通常情况下,采用 ADC1 (见表 2)。按
照这种方式,71M6541D/F/G 或 71M6542F/G 中未使用的 ADC1 序号被作为复用帧中的占位符,以生成正
确的复用帧时序和正确的采样率。储存在 CE RAM 0x1 中的结果数据未定义,CE 代码忽略。同时,数字隔
离接口负责自动将远端接口电流(IBP-IBN)的采样储存在 CE RAM 0x2。
18
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
CE 代码中的延迟补偿和其它功能要求 MUX_DIV[3:0]、MUXx_SEL[3:0]、RMT_E、FIR_LEN[1:0] 、
ADC_DIV 和 PLL_FAST 的 设 置 对 于 给 定 的 CE 代 码 是 固 定 的 。 关 于 71M6541D/F/G 和
71M6542F/G 的合理设置,请参见表 1 和表 2。
表 4 汇总了用于配置复用器、信号引脚和 ADC 的 I/O RAM 寄存器。所有列出的寄存器在复位及从电池模
式唤醒后清零,可进行读、写操作。
表 4. 复用器和 ADC 配置位
名称
位置
说明
MUX0_SEL[3:0]
2105[3:0]
选择在时隙 0 期间转换 ADC 输入。
MUX1_SEL[3:0]
2105[7:4]
选择在时隙 1 期间转换 ADC 输入。
MUX2_SEL[3:0]
2104[3:0]
选择在时隙 2 期间转换 ADC 输入。
MUX3_SEL[3:0]
2104[7:4]
选择在时隙 3 期间转换 ADC 输入。
MUX4_SEL[3:0]
2103[3:0]
选择在时隙 4 期间转换 ADC 输入。
MUX5_SEL[3:0]
2103[7:4]
选择在时隙 5 期间转换 ADC 输入。
MUX6_SEL[3:0]
2102[3:0]
选择在时隙 6 期间转换 ADC 输入。
MUX7_SEL[3:0]
2102[7:0]
选择在时隙 7 期间转换 ADC 输入。
MUX8_SEL[3:0]
2101[3:0]
选择在时隙 8 期间转换 ADC 输入。
MUX9_SEL[3:0]
2101[7:0]
选择在时隙 9 期间转换 ADC 输入。
MUX10_SEL[3:0]
ADC_DIV
MUX_DIV[3:0]
2100[3:0]
2200[5]
2100[7:4]
选择在时隙 10 期间转换 ADC 输入。
控制 ADC 和 FIR 时钟速率。
每个复用帧中 ADC 时隙的数量(最大 = 11)。
PLL_FAST
FIR_LEN[1:0]
DIFFA_E
2200[4]
210C[1]
210C[4]
控制 PLL 和 MCK 速率。
决定 ADC 抽样 FIR 滤波器中的 ADC 周期数。
使能模拟输入引脚 IAP-IAN 的差分配置。
DIFFB_E
210C[5]
使能模拟输入引脚 IBP-IBN 的差分配置。
RMT_E
2709[3]
使能远程传感器接口,将引脚 IBP-IBN 转换为数字平衡差分对,与
71M6x01 传感器通信。
PRE_E
2704[5]
使能 8x 前置放大器。
关于这些 I/O RAM 位置的详细信息,请参见从第 111 页开始的表 76。
2.2.3
延迟补偿
测量单相能量(即 Wh 和 VARh)时,必须对该相电压和电流同步采样。否则,会产生相位差 Ф,进而引入误
差。
φ=
t delay
T
⋅ 360 o = t delay ⋅ f ⋅ 360 o
式中,f 为输入信号的频率,T = 1/f,tdelay 为电流和电压之间的采样延迟。
传统上,采样是通过控制每相的两个 A/D 转换器(一个用于电压,另一个用于电流)同时采样实现的。而
Teridian 的单转换器技术利用其 CE 的 32 位信号处理能力,实现了“固定延迟”全通滤波器。全通滤波器
修正采用单路复用 A/D 转换器引起的电压和对应电流采样之间的转换时间差。
“固定延迟”全通滤波器提供 360° - θ 宽频带延迟,它与给定相的电压和电流之间的采样时间差精确匹配。
该数字滤波器不影响信号幅值,但提供精确受控的相位响应。
Rev 2
19
71M6541D/F/G 和 71M6542F/G 数据资料
推荐 ADC 复用序列首先采样电流,随后采样对应相的电压,由此,电压比电流延迟一个相位角 Ф。CE 内
执行的延迟补偿首先将电流采样延迟一个完整的采样间隔(即 360°),然后使电压采样通过全通滤波器,由
此将电压采样延迟 360o - θ,造成电流与对应电压之间的相位误差为 θ – Ф,从而将电压样本与对应的电流
样本对齐。剩余相位误差可忽略不计,100Hz 时,误差通常小于±1.5 毫度,所以不会引起能量测量误差。
使用远程传感器时,CE 执行与上述相同的延迟补偿,将每个电压采样与对应的电流采样对齐。即使远程电
流采样不通过 71M654x 复用器,如果按照表 1 和表 2 对 MUXn_SEL[3:0]时隙分配字段编程,它与对应电
压的定时关系也是固定且精确可知的。
2.2.4
ADC前置放大器
ADC 前置放大器为低噪声差分放大器,固定增益 8 仅可用于 IAP-IAN 传感器输入引脚。通过置位 PRE_E =
1 (I/O RAM 0x2704[5])使能 8 倍增益。禁用时,前置放大器的电源电流< 10nA,增益为单位增益。正确设置
PRE_E 和 DIFFA_E (I/O RAM 0x210C[4])位,无论是否选择差分模式,均可使用前置放大器。为获得最佳性
能,建议使用差分模式。为节约功率,根据 ADC_DIV 控制位(I/O RAM 0x2200[5])调节前置放大器和 ADC
的偏置电流。
2.2.5
A/D转换器(ADC)
利用 2 阶 Σ-Δ A/D 转换器量化输入电压和电流。ADC 分辨率(包括符号位)为 21 位(FIR_LEN[1:0] = 1,I/O
RAM 0x210C[2:1])或 22 位(FIR_LEN[1:0] = 2)。ADC 时钟由 CKADC 驱动。
如上所述, 由 MUX_CTRL 内部电路控制每次 ADC 转换的启动。ADC 转换结束时,FIR 滤波器输出数据储
存至 CE RAM,地址由复用器选项决定。该数据以 LSB 对齐并左移 9 位存储。
2.2.6
FIR滤波器
有限冲击响应滤波器是 ADC 的一部分,针对复用器进行优化,使 ADC 输出达到所要求的分辨率。每次
ADC 转换结束时,输出数据储存至固定的 CE RAM 地址,由表 1 和表 2 所示复用器选项决定地址。
2.2.7
电压基准
带隙基准为 ADC 提供基准电压,基准幅值为斩波稳定,可由 MPU 利用 I/O RAM 控制字段 CHOP_E[1:0]
(I/O RAM 0x2106[3:2])使能或禁用斩波电路。CHOP_E[1:0]字段中的两位使能 MPU,将斩波电路置于标准
模式或反相模式,或者自动切换模式(推荐)。斩波电路在复用周期之间切换时,VREF 的直流失调被自动调
整为零,因此,斩波电路必须配置为其中一种自动切换模式。
电压基准(VREF)的后级放大器通常存在长期失调电压,通过斩波电路可以自动消除失调电压的影响,提供
稳定的 VREF。71M654x 和 71M6x01 均具有斩波电路,用于各自的 VREF 电压基准。
斩波放大器的典型拓扑如图 8 所示。CROSS 信号为内部信号,不能通过引脚或寄存器进行直接操作。
20
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
A
Vinp
B
A
Vinn
B
A
+
G
-
Voutp
B
A
Voutn
B
CROSS
图 8. 斩波放大器通用拓扑
假设在放大器正极输入上有一个偏移电压 Voff。由 CROSS (内部信号)控制所有开关处于 A 位置时,输出
电压为:
Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff
通过施加反相 CROSS 信号将所有开关处于 B 位置时,输出电压为:
Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff,或者
Voutp – Voutn = G (Vinp – Vinn) - G Voff
因此,CROSS 切换时,例如每个复用周期之后,输出偏移表现为正、负交替,从而消除漂移,不受极性或
幅值影响。
CROSS 为高电平时,放大器输入连接反转。维持放大器增益的总体极性,将输入失调反相。通过交替反转
连接,对放大器失调取平均,结果为零。这样就消除了电压基准中常见的长期失调。CHOP_E[1:0] (I/O
RAM 0x2106[3:2])控制字段使能 CROSS 功能。CROSS 信号反转电压基准中的放大器连接,以抵消失调的
影响。在复用序列的最后一个转换状态之后的第一个 CK32 上升沿,复用器在开始新帧之前额外等待一个
CK32 周期。该周期开始时,根据 CHOP_E[1:0]字段更新 CROSS 数值。额外的 CK32 周期使斩波 VREF
有时间达到稳定。在此期间,MUXSYNC 保持为高电平。MUXSYNC 的前沿启动一次 CE 程序的运行,开
始时读取四个 RTM 字。
CHOP_E[1:0]有四个状态:正极、反相,以及两种自动切换状态。正极状态下,CHOP_E[1:0] = 01,
CROSS 保持为低电平;反相状态下,CHOP_E[1:0] = 10,CROSS 保持为高电平。
图 9. CROSS 信号,CHOP_E = 00
图 9 所示为 CHOP_E[1:0] = 00 时两个累积间隔的 CROSS 信号。第一个间隔末尾,CROSS 为高电平;第
二个间隔末尾,CROSS 为低电平。CHOP_E[1:0] = 00 时,不需要 MPU 控制斩波器。
在第二个自动切换状态,CHOP_E[1:0] = 11,CROSS 在累积间隔的最后一个复用周期结束时不切换。
低功耗电压基准用于 LCD 驱动电路和控制进入、退出电池供电模式的比较器。
Rev 2
21
71M6541D/F/G 和 71M6542F/G 数据资料
2.2.8
71M6x01 隔离传感器接口(远端传感器接口)
2.2.8.1 概述
非隔离传感器,例如电阻分流器,可通过 71M6x01 和脉冲变压 (图 36 所示为该传感器接口的顶层方框图)
的组合连接至 71M654x。71M6x01 通过脉冲变压器直接从 71M654x 取电,无需专用的供电电路。
71M6x01 建立与 71M654x 的双向通信,通过串行数据流提供电流采样和辅助信息(例如:传感器温度)。
71M6541D/F/G 和 71M6542F/G 均支持 71M6x01 隔离传感器。使能该功能时,两个模拟电流输入引脚
IBP 和 IBN 成为连接至远程传感器的数字平衡差分接口,详细信息请参考表 3。
每个 71M6x01 远端传感器由以下模块组成:
•
电源,用于从 71M654x 接收的电源脉冲
•
数字通信接口
•
分流信号前置放大器
•
Σ-Δ ADC 转换器,带有高精度带隙基准(斩波放大器)
•
温度传感器
•
熔丝器件,包含部件相关信息
在常规的复用周期内,71M654x 利用 MUX_DIV[3:0] (I/O RAM 0x2100[7:4])决定使能哪个通道。同时,对
远端传感器的调制器输出进行采样。每个转换结果在 CE 操作时隙写入 CE RAM。关于采样信号的 CE
RAM 地址,请参见表 3。
2.2.8.2 71M654x和 71M6x01 隔离传感器之间的通信
71M6x01 的 ADC 定时时钟来自 71M654x 产生的脉冲信号。电源脉冲的产生,以及 71M654x 和 71M6x01
远端传感器之间的通信协议通过硬件自动完成,用户无需进行任何操作,本数据资料不作详细介绍。
2.2.8.3 71M6x01 隔离传感器的控制
71M654x 可读、写每个 71M6x01 远端传感器的特定字节信息。
读取数据由 RCMD[4:0]和 TMUXRn[2:0]组合选择。为执行对 71M6x01 器件的读操作,MPU 首先写
TMUXRn[2:0]字段(其中 n = 2、4、6,分别位于 I/O RAM 0x270A[2:0]、0x270A[6:4]和 0x2709[2:0])。接着,
MPU 根据所要求的命令和相选择写入 RCMD[4:0] (SFR 0xFC[4:0])。RCMD[4:2]位清零时,操作完成,请
求发送的数据位于 RMT_RD[15:0] (I/O RAM 0x2602[7:0]为 MSB,0x2603[7:0]为 LSB)。操作期间还更新读
取奇偶校验位 PERR_RD (SFR 0xFC[6])。如果 MPU 在完成上次读操作之前写入 RCMD[4:0],则忽略命令。
因此,MPU 在继续发出下一条读命令之前必须判断 RCMD[4:2]是否清零。
RCMD[4:0]字段分为两个子域:COMMAND=RCMD[4:2]和 PHASE=RCMD[1:0],如表 5 所示。
表 5. RCMD[4:0]位
命令
相选择器
相关的 TMUXRn
RCMD[4:2]
RCMD[1:0]
控制字段
--000
00
无效
无效
IBP-IBN
TMUXRB [2:0]
001
01
命令 1
100
保留
101
无效
110
保留
111
保留
注:
1. 只 有 两 个 RCMD[4:2] (SFR 0xFC[4:2]) 码 与 常 规 工 作 有 关 , 为
RCMD[4:2] = 001 和 010。000 和 101 吗无效,如果使用,将被忽略。
其余编码为保留,不得使用。
2. 对于 RCMD[1:0]控制子域,编码 01、10 和 11 有效,00 无效,不得使
22
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
用。
表 6 所示为所允许的 RCMD[4:2]和 TMUXRn[2:0]数值组合、71M6x01 远端传感器返回的对应数据类型和格
式,并显示了数据如何储存至 RMT_RD[15:8]和 RMT_RD[7:0]。MPU 通过设置 RCMD[1:0]字段中的有效编
码,选择读取三相电中的一相,如表 5 所示。
表 6. 远程接口读命令
读操作
RCMD[4:2]
TMUXRn[2:0]
001
00X
010
00X
STEMP[10:0]
010
01X
VSENSE[7:0]
010
10X
VERSION[7:0]
注:
1.
2.
3.
RMT_RD [15:8]
RMT_RD [7:0]
TRIMT[7]=RMT_RD[8]
TRIMT[6:0]=RMT_RD[7:1]
STEMP[10:8]=RMT_RD[10:8]
STEMP[7:0]
TRIMT[7:0]
(熔丝寄存器,适用于全部
71M6x01)
(检测的 71M6x01 温度)
(检测的
(RMT_RD[15:11]高位带符号部分)
全零
VSENSE[7:0]
VERSION[7:0]
全零
71M6x01 供电电压)
(芯片版本)
TRIMT[7:0] 是用于全部 71M6x01 器件的 TRIMT 熔丝值。注意,TRIMT[7:0] 8 位数值由 RMT_RD[8] 和
RMT_RD[7:1]组成。关于 TRIMT[7:0]的更多信息,请参见 71M6xxx 的数据资料。
关于利用 71M6x01 读取的 STEMP[7:0]数值计算温度的公式,请参见 71M6xxx 的数据资料。
关于利用 71M6x01 读取的 VSENSE[7:0]数值计算电压的公式,请参见 71M6xxx 的数据资料。
71M6541D/F/G 获取每个隔离传感器 71M6x01 的硬件和相关信息,MPU 根据 71M6x01 隔离传感器的温度
特性实现电能测量的温度补偿。详情参见第 97 页第 4.7 节的计量温度补偿。
表 7 列出了用于控制外部 71M6x01 隔离传感器的全部 I/O RAM 寄存器,详情参见 71M6xxx 数据资料。
表 7. 用于远端传感器的 I/O RAM 控制位
名称
地址
RST
默认值
WAKE
默认值
读/写 说明
RCMD[4:0]
SFR
FC[4:0]
0
0
MPU 向 RCMD 写 非 零 值 时 , 71M654x 向 由
RCMD[1:0]选中的相应远端传感器发出一条命令。
R/W
完成命令后,71M654x 清除 RCMD[4:2]。命令码
本身位于 RCMD[4:2]。
PERR_RD
PERR_WR
SFR FC[6]
SFR FC[5]
0
0
71M654x 将这些位置位,表示在远端传感器上检
R/W 测到奇偶校验错误。这些位一旦置位,则被记忆,
直到由 MPU 清除。
2709[7:6]
00
00
用于远端传感器的 CHOP。
00 – 自动斩波,每个复用帧变化。
R/W 01 – 正
10 – 负
11 – 同 00
TMUXRB[2:0] 270A[2:0]
RMT_RD[15:8] 2602[7:0]
RMT_RD[7:0] 2603[7:0]
000
000
R/W TMUX 位,用于控制远端传感器。
0
0
CHOPR[1:0]
R
用于 71M6x01 读操作的读缓冲器。
控制 71M654x 驱动 71M6x01 电源脉冲的方式。置
R/W 1,脉冲驱动为高或低电平;清 0,驱动至高电
平,后接一个开路反激间隔。
使能隔离远程传感器,重新将引脚 IBP-IBN 配置为
RMTB_E
2709[3]
0
0
R/W
平衡线对的数字远程接口。
关于这些 I/O RAM 地址的详细信息,请参见从第 111 页开始的表 76。
RFLY_DIS
Rev 2
210C[3]
0
0
23
71M6541D/F/G 和 71M6542F/G 数据资料
数字计算引擎(CE)
2.3
CE 是一个专用的 32 位数字信号处理器,用来执行电量计量所需的精确运算。CE 运算和处理包括:
•
•
•
•
•
•
•
•
每个电流采样值与其对应电压采样值相乘,以获得每次采样的电能(与固定的采样时间相乘)。
对四个通道的非同步采样所产生的延迟进行算法补偿(不受频率影响)。
90°相移(用于无功计算)。
脉冲发生器。
输入信号频率监测(用于频率和相位信息)。
输入信号幅值监测(用于电压跌落检测)。
根据校准参数对采样进行缩放处理。
根据温度补偿信息对采样进行缩放处理。
2.3.1
CE程序存储器
CE 程序存储在程序存储器(FLASH)。CE 和 MPU 对 FLASH 的公共访问由存储器公用电路控制。每个 CE
指令为 2 字节长度。为 CE 程序分配的闪存空间不得超过 4096 个 16 位字(8KB)。CE 程序在复用器状态 0
开始启动。执行到 HALT 指令时,程序结束。为确保 CE 的正确运行,程序必须在复用周期结束之前执行
完毕。
CE 程 序 必 须 在 FLASH 地 址 以 1KB 为 边 界 处 开 始 。 I/O RAM 控 制 字 段 CE_LCTN[5:0] (I/O RAM
0x2109[5:0])定义哪个 1KB 边界为 CE 代码的起始地址。所以,第一条 CE 指令位于 1024*CE_LCTN[5:0]。
2.3.2
CE数据存储器
CE 和 MPU 共用数据存储器(XRAM)。CE 和 MPU 对 XRAM 的公共访问由存储器公用电路控制。CE 最多
可访问 3KB 数据 RAM (XRAM)中的全部 3KB,即从 RAM 地址 0x0000 至 0x0C00。
XRAM 可由 FIR 滤波器模块、RTM 电路、CE 和 MPU 访问。分别为 FIR 和 MPU 保留分配的时隙,以防止
CE 访问 XRAM 数据时发生总线冲突。
MPU 读、写 CE 和 MPU 之间共用的 XRAM 是两个处理器之间数据通信的主要途径。
表 3 列出了 XRAM 分配给 AFE 模拟输入的 CE 地址。
CE 通过支持硬件实现计量运算、脉冲计数和累加。通过 I/O RAM 控制字段 EQU[2:0]、计量公式选择字段
(I/O RAM 0x2106[7:5])、DIO_PV 位(I/O RAM 0x2457[6])、DIO_PW 位 (I/O RAM 0x2457[7]) 、脉冲辅助位和
SUM_SAMPS[12:0]累积周期辅助位(I/O RAM 0x2107[4:0]和 0x2108[7:0])控制硬件。
SUM_SAMPS[12:0]是一种能量累积方案,在一个累积周期内累加 SUM_SAMPS[12:0]个复用帧的能量。每个
能量输出的积分时间,比如 SUM_SAMPS[12:0]/2520.6 (MUX_DIV[3:0] = 011,I/O RAM 0x2100[7:4]和
FIR_LEN[1:0] = 10,I/O RAM 0x210C[2:1])。完成累积时,CE 触发硬件 XFER_BUSY 中断。
24
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
2.3.3
CE与MPU通信
CE 向 MPU 输出 6 种中断信号:CE_BUSY、XFER_BUSY、XPULSE、YPULSE、WPULSE 和 VPULSE。
这些信号在芯片内部已连接至 MPU 中断服务。CE_BUSY 表示 CE 正在处理数据,该信号每个复用帧出现
一次。XFER_BUSY 表示 CE 正在更新 CE RAM 的输出区域,累积循环结束时产生中断。CE 执行 HALT
指令后,CE_BUSY 和 XFER_BUSY 自动清零。
XPULSE、YPULSE、VPULSE 和 WPULSE 也可配置成中断,监测电网电压跌落故障、过零和脉冲事件中
断。此外,这些信号也可直接输出至 DIO 引脚,CE 提供直接输出。这些信号对应的中断为上升沿触发(参
见图 16 中的“外部”中断源 No. 2)。
2.3.4
电表公式
71M6541D/F/G 和 71M6542F/G 为 CE 提供辅助硬件,以支持不同的计量公式。辅助电路通过 I/O RAM 寄
存器 EQU[2:0] (公式辅助)控制。利用 CE 固件配置执行表 8 所列公式,完全满足工业计量需求。同时
EQU[2:0]也含有计量公式及计量相数信息。
表 8. 复用器输入选择
说明
EQU
0
单元 1,2W,1Ф,带零线
电流检测
1
单元 1,3W,1Ф
2†
单元 2,3W,3Ф ∆
有功和无功计量公式
推荐的复用器序列
单元 0
单元 1
单元 2
VA ∙ IA
VA ∙ IB1
N/A
IA VA IB1
VA(IA-IB)/2
N/A
N/A
IA VA IB
VA ∙ IA
VB ∙ IB
N/A
IA VA IB VB
注:
1. 可选,IB 可用于测量零线电流
† 仅限 71M6542F/G
2.3.5
实时监测器(RTM)
CE 含有一个实时监测器(RTM),可设置为在全速采样速率下监测四个可选的 XRAM。四个被监测位置,由
I/O RAM 寄存器 RTM0[9:8]、RTM0[7:0]、RTM1[9:8]、RTM1[7:0]、RTM2[9:8]、RTM2[7:0]、RTM3[9:8]和
RTM3[7:0]选择,以上数据在每次 CE 执行之前串行输出至 TMUXOUT (多功能监测口)引脚。RTM 可由控
制位 RTM_E (I/O RAM 0x2106[1])使能和禁用。RTM 输出时钟为 CKTEST。每个 RTM 字需要 35 个 CKCE
周期(1 个 CKCE 周期等于 203ns),含起始位,RTM 输出格式请参见图 10。RTM 未输出时,TMUXOUT
引脚为低电平。
图 11 为 MUX、CE_BUSY 和 RTM 时序关系图。本例中,MUX_DIV[3:0] = 4 (I/O RAM 0x2100[7:4])和
FIR_LEN[1:0] = 10 (I/O RAM 0x210C[1]) , (384),4 个 ADC 转换帧结果。每个 ADC 转换帧占用整数个
CK32 周期。最后还需要一个 CK32 的存储周期。
图 11 中还显示,RTM 串行数据流在状态“S”起始位置开始输出。整个 RTM 需要 140 个 CKCE 周期,总
是在下一次 CE 码执行开始之前结束。
Rev 2
25
71M6541D/F/G 和 71M6542F/G 数据资料
CK32
MUX_SYNC
MUX_STATE
S
CKTEST
0
31
FLAG
1
30
31
0
FLAG
1
30
31
SIG
N
30
L SB
1
SIG
N
0
FLAG
L SB
RTM DATA0 (32 bits)
RTM DATA1 (32 bits)
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
31
SIG
N
30
L SB
1
L SB
0
FLAG
SIG
N
RTM
图 10. RTM 时序
ADC MUX Frame
ADC TIMING
Settle
MUX_DIV Conversions, MUX_DIV=4 is shown
CK32
150
MUX_SYNC
MUX STATE
S
1
0
2
3
S
ADC EXECUTION
ADC0
CE TIMING
0
ADC1
450
900
ADC2
ADC3
1350
1800
CE_EXECUTION
CK COUNT = CE_CYCLES + 1CK for each ADC transfer
MAX CK COUNT
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
RTM TIMING
140
RTM
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY SUM_SAMPS CODE PASSES.
图 11. ADC MUX、CE 和 RTM 串行传输时序关系
26
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
2.3.6
脉冲发生器
71M6541D/F/G 和 71M6542F/G 支持四路脉冲发生器:VPULSE、WPULSE、XPULSE 和 YPULSE,其
中 VPULSE 和 WPULSE 有相应的硬件脉冲发生器支持。脉冲发生器可以将 CE 状态、SAG 输出到对应的
IO 口。所有脉冲均可配置为 MPU 中断。
PLS_INV (I/O RAM 0x210C[0])可以控制脉冲的极性。该位置 1 时,脉冲为高电平有效。默认为 0,低电平
有效。PLS_INV 会同时改变 4 路脉冲输出极性。
每个特定 CE 代码决定每个脉冲发生器的功能,MPU 必须配置 CE 寄存器实现脉冲输出功能。例如,在标
准 CE 代码中 XPULSE 用来产生过零信号,YPULSE 用来产生 SAG 信号。
过零脉冲常用于产生一个中断,使软件能够修正实时时钟,以及针对晶振老化进行调节,前提是电网频率
足够精确和稳定。SAG 脉冲通常用在交流电源跌落时产生预警中断,MPU 即可在 V3P3SYS 电压下降之前
将重要信息(比如电量)存入外部 EEPROM。
2.3.6.1 XPULSE和YPULSE
CE 产生的脉冲可输出至 XPULSE 和 YPULSE 脉冲输出引脚,SEGDIO6 和 SEGDIO7 引脚分别用于这些
脉冲。一般而言,XPULSE 和 YPULSE 输出可在每个 CE 代码周期更新一次。
详情参见第 125 页第 5.3 节 CE 接口说明。
2.3.6.2 VPULSE和WPULSE
参见图 12,每个 CE 代码周期,硬件将 WPULSE 和 VPULSE 输出符号位保存在一个 8 位 FIFO 中,并以
规定的间隔输出。这样 CE 代码就需要在其执行完之前计算 VPULSE 和 WPULSE 输出,并依靠硬件将其
分配至复用帧。如图 12 所示,FIFO 在每个复用帧开始时复位。从图 12 还可以看出 I/O RAM 寄存器
PLS_INTERVAL[7:0] (I/O RAM 0x210B[7:0])控制到第一个脉冲更新之间的延迟,以及随后更新之间的间隔。
PLS_INTERVAL[7:0]寄存器的 LSB 等于 4 个 CK_FIR 周期(如果 PLL_FAST = 1 且 ADC_DIV = 0,CK_FIR
通 常 为 4.9152MHz , 但 也 可 能 是 其 它 CK_FIR 频 率 ; 参 见 表 76 中 的 ADC_DIV 定 义 ) 。 如 果
PLS_INTERVAL[7:0] = 0,FIFO 禁用,脉冲输出由 CE 更新。
以 CK_FIR 时钟周期为单位的 MUX 帧持续时间由下式决定:
如果 PLL_FAST=1:
MUX frame duration in CK_FIR cycles = [1 + (FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [150 / (ADC_DIV+1)]
如果 PLL_FAST=0:
MUX frame duration in CK_FIR cycles = [3 + 3*(FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [48 / (ADC_DIV+1)]
以 CK_FIR 时钟周期为单位的 PLS_INTERVAL[7:0]计算如下:
PLS_INTERVAL[7:0] = floor (Mux frame duration in CK_FIR cycles / CE pulse updates per Mux frame / 4 )
由于 FIFO 在每个复用帧开始时复位,用户必须指定 PLS_INTERVAL[7:0],CE 在复用帧结束之前完成脉冲
更新。例如,71M654x CE 代码在每个复用周期更新 6 次输出,如果复用间隔为 1950 个 CK_FIR 时钟周期
长,适用于该间隔的理想值为 1950/6/4 = 81.25。然而,如果 PLS_INTERVAL[7:0] = 82,第 6 次输出太晚,
将丢失数据。这种情况下,PLS_INTERVAL[7:0]的合理数值为 81 (即四舍五入结果)。
由于 PLS_INTERVAL[7:0]的一个 LSB 等于 4 个 CK_FIR 时钟周期,以 CK_FIR 时钟周期为单位的脉冲时间
间隔 TI 为:
TI = 4*PLS_INTERVAL[7:0]
Rev 2
27
71M6541D/F/G 和 71M6542F/G 数据资料
如果使能 FIFO(及 PLS_INTERVAL[7:0] ≠ 0,硬件也提供脉宽调整功能,由寄存器 PLS_MAXWIDTH[7:0]
(I/O RAM 0x210A)实现。默认配置下,WPULSE 和 VPULSE 为负脉冲(即低电平脉冲,通过灌电流驱动
LED)。PLS_MAXWIDTH[7:0]决定以 CK_FIR 时钟周期为单位的最大负脉冲宽度 TMAX,取决于脉冲间隔 TI,
计算公式如下:
TMAX = (2 * PLS_MAXWIDTH[7:0] + 1) * TI
如果 PLS_MAXWIDTH = 255 或 PLS_INTERVAL = 0,则不执行脉宽检查,脉冲默认为 50%占空比。TMAX 通
常设置为 10 ms,对于大多数校准系统工作良好。
脉冲极性可用控制位 PLS_INV (I/O RAM 0x210C[0])反转。置位 PLS_INV 时,脉冲为高电平有效。PLS_INV
默认值为零,低电平有效。
WPULSE 和 VPULSE 脉冲分别输出连接至 SEGDIO0/WPULSE 和 SEGDIO1/VPULSE (引脚 45 和 44)引
脚。脉冲也可以从 OPT_TX 引脚 53 输出(详情参见 OPT_TXE[1:0] 、I/O RAM 0x2456[3:2])。
ADC MUX Frame
Settle
MUX_DIV Conversions (MUX_DIV=4 is shown)
CK32
150
MUX_SYNC
CE CODE
S1
S0
S2
S3
S4
S5
W_FIFO
RST
WPULSE
S0
S1
S1
S0
4*PLS_INTERVAL
S2
4*PLS_INTERVAL
4*PLS_INTERVAL
S3
S2
4*PLS_INTERVAL
S4
S3
4*PLS_INTERVAL
S5
S4
S5
4*PLS_INTERVAL
1. This example shows how the FIFO distributes 6 pulse generator updates over one MUX frame.
2. If WPULSE is low longer than (2*PLS_MAXWIDTH+1) updates, WPULSE will be raised until the next
low-going pulse begins.
3. Only the WPULSE circuit is shown. The VARPULSE circuit behaves identically.
4. All dimensions are in CK_FIR cycles (4.92MHz).
5. If PLS_INTERVAL=0, FIFO does not perform delay.
图 12. 脉冲发生器 FIFO 时序
2.3.7
CE功能概述
71M654x 通过一个 ADC 和复用器对模拟输入进行采样,如图 2 和图 3 所示。VA 和 VB 电压采用由直接连
接在 71M654x 的电阻分压器组成,因此,始终使用 71M654x 器件的 ADC 和复用器功能。而电流传感器也
可以直接连接至 71M654x 或通过远端隔离器连接,71M6x01 远端传感器有其独立的 ADC 和电压基准。电
流传感器通过远端传感器连接时,71M654x 将通过隔离接口(通过脉冲变压器)以数字方式接收采样数据。
直接将其存入相应的 CE RAM,如图 3 所示。ADC (即 71M654x 中的 ADC 和 71M6x01 中的 ADC)处理其
对应传感器通道,每个复用周期内对每个通道进行一次采样。
图 14 (71M6541D/F/G) 和 图 15 (71M6542F/G) 所 示 为 两 个 电 流 传 感 器 (IA 和 IB) 均 直 接 连 接 至
71M6541D/F/G 时(如图 2 所示)的采样时序。而 IB 通道为 71M6x01 远端传感器时,采样数据不通过
71M6541D/F/G 复用器,如图 3 所示。这种情况下,在复用周期的后半部分进行采样,数据直接储存到相
应的 CE RAM,如图 3 所示。远端电流传感器通道与其对应电压的时序关系被确定,因此 CE 可以精确补
偿延迟。
28
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
参见图 15,71M6542F/G 具有一路附加的电压输入(VB),支持 2 相电表设计。与 VA 相同,VB 通过电阻
分压器直接连接至 71M6542F/G,使用 71M6542F/G 内的 ADC 和复用功能。MUX_DIV[3:0] = 4 配置复用
器 具 有 一 个 附 加 时 隙 , 用 来 处 理 VB 电 压 采 样 。 和 71M6541D/F/G 一 样 , IA 采 样 从 直 接 连 接 至
71M6542F/G 的电流传感器获得,而 IB 采样从连接的 CT 或通过 71M6x01 隔离器件远程连接(见图 2 和图
3)的分流器获得。
一个累积周期内处理的采样数量由 I/O RAM 寄存器 SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0]、0x2108[7:0])
控制。每个能量输出的积分时间为:
SUM_SAMPS / 2520.6,其中 2520.6 为采样率,单位为 Hz
例如,SUM_SAMPS = 2100 时,每个累积周期建立 2100 个采样,持续时间为 833ms。完成累积周期后,
XFER_BUSY 中断通知 MPU 有更新的累积数据。
每个复用周期结束时,都可以通过 CE_BUSY 中断通知 MPU 状态寄存器已更新,例如电压跌落数据和数
字化的输入信号。
图 13 所示为 SUM_SAMPS = 2100 个累积周期,包括 2100 个样本,每个采样周期 397μs,随后是
XFER_BUSY 中断。本例为 50Hz 信号采样情况,具体的电网频率与 SUM_SAMPS 无关。此外,并非必须
从电网电压过零点开始采样,累积周期也无需是信号周期的整数倍。
833ms
20ms
XFER_BUSY
Interrupt to MPU
图 13. 累积间隔
Rev 2
29
71M6541D/F/G 和 71M6542F/G 数据资料
IB
VA
IA
122.07 µs
30.5
µs
122.07 µs
122.07 µs
Multiplexer Frame (13 x 30.518 µs = 396.7 µs -> 2520.6 Hz)
MUX_DIV[3:0] = 3 Conversions
Settle
CK32
(32768 Hz)
MUX STATE
S
0
1
S
2
图 14. 复用周期内采样(MUX_DIV[3:0] = 3)
VB
IB
VA
IA
91.5 µs
91.5 µs
91.5 µs
30.5 µs
91.5 µs
Multiplexer Frame (13 x 30.518 µs = 396 µs à2520Hz)
MUX_DIV[3:0] = 4 Conversions
Settle
CK32
(32768 Hz)
MUX STATE S
0
1
2
3
S
图 15. 复用周期内采样(MUX_DIV[3:0] = 4)
30
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
2.4
80515 MPU核
71M6541D/F/G 和 71M6542F/G 集成了 80515 MPU (8 位、8051 兼容),大多数指令可以在一个时钟周期
完成。因此 4.9MHz 主频相当于 4.9 MIPS 的处理能力。80515 架构消除了冗余总线状态,指令读取和执行
并行执行。通常情况下,机器周期与存储周期对齐,因此,大多数单字节指令在单个机器周期(MPU 时钟周
期)内完成,相对于相同时钟频率的 Intel® 8051 速率提升了 8 倍(MIPS)。
表 9 中 CKMPU 是 MCK 时钟(19.6608MHz)的分频输出,可以通过控制字段 MPU_DIV[2:0] (I/O RAM
0x2200[2:0])设置 MPU 时钟频率。具体运行频率取决于实际需求(表计计算、AMR 管理、存储器管理、
LCD 驱动管理和 I/O 管理),如表 9 所示。
表 9. CKMPU 时钟频率
MPU_DIV [2:0]
CKMPU 频率
000
001
010
011
100
101
110
111
4.9152MHz
2.4576MHz
1.2288MHz
614.4kHz
307.2kHz
CE 代码以一种库文件的形式提供给客户,具体的计量性能和功能与 CE 代码版本有关。Teridian 提供演示
源代码,帮助用户缩短设计周期。
2.4.1
存储器架构和寻址
80515 MPU 核心采用 Harvard 架构,代码和数据空间相隔离。80515 中的存储器管理与工业标准 8051 类
似。有三个存储区域:程序存储器(MPU 和 CE 共用)、外部 RAM (CE 和 MPU 共用,以及配置 I/O RAM)和
内部数据存储器(内部 RAM)。表 10 列出了存储器映射。
程序存储器(FLASH)
80515 可寻址高达 64KB 程序存储空间(0x0000 至 0xFFFF)。MPU 取指令或执行 MOVC 操作时,进行存储
器读操作。
从复位或低功耗状态唤醒后,MPU 从程序存储器的地址 0x0000 开始执行。程序存储器的低地址部分包括
复位和中断向量。中断向量以 8 字节间隔分布,从 0x0003 开始。
MPU外部数据存储器(XRAM)
不管是内部还是外部数据存储器,物理上均在 71M654x 器件内部。本文提及的外部数据存储器只是相对于
80515 MPU 内核而言。
从地址 0x0000 开始的 3KB RAM 由 CE 和 MPU 共用。CE 通常使用前 1KB,为 MPU 留 2KB。不同版本
CE 代码,所占用的存储空间不同。准确数据请查阅具体版本代码的说明文档。
如果 MPU 覆盖 CE 的工作 RAM,CE 输出可能破坏。如果 CE 被禁用,MUX_DIV[3:0] ≠ 0 时,
RAM 的 前 0x40 字 节 仍 然 不 可 用 , 因 为 71M654x ADC 原 始 数 据 会 更 新 到 这 些 地 址 。 设 置
MUX_DIV[3:0] = 0 禁用 ADC 输出,防止 CE 覆盖 RAM 的前 0x40 字节。
此外,MUXn_SEL[3:0]值必须在 MUX_DIV[3:0]写操作之后写入。
Rev 2
31
71M6541D/F/G 和 71M6542F/G 数据资料
MPU 执行 MOVX @Ri,A 或 MOVX @DPTR,A 指令时,80515 写外部数据存储器。MPU 通过执行 MOVX
A,@Ri 或 MOVX A,@DPTR 指令(PDATA, SFR 0xBF 为 MOVX A,@Ri 指令提供高 8 个字节)读外部数据存储
器。
内部和外部存储器映射
表 10 中列出了各种存储器件的地址、类型、用途及大小。
表 10. 存储器映射
地址
(十六进制)
0000-7FFF
存储器技术
闪存
存储器类型
非易失
典型用途
存储器大小
(字节)
MPU 程序和非易失数
据
64/32KB †
CE 程序(在 1KB 边
界)
最大 3KB.
名称
MPU 和 CE 程序
存储器
0000-0BFF
静态 RAM
易失
外部 RAM
(XRAM)
CE 和 MPU 共用
5/3KB †
2000-27FF
静态 RAM
易失
配置 RAM (I/O
RAM)
硬件控制
2KB
2800-287F
静态 RAM
非易失
(电池)
配置 RAM (I/O
RAM)
电池缓冲存储器
128
0000-00FF
静态 RAM
易失
内部 RAM
80515 核心的一部分
256
†存储器大小取决于 IC 具体型号,详情参见第 2.5.1 节物理存储器。
MOVX寻址
有两种类型的指令,区别在于提供 8 位或 16 位外部数据 RAM 的间接地址。
第一种类型中,MOVX A,@Ri,当前寄存器组的 R0 或 R1 提供地址的 8 个低位。地址的 8 个高位由
PDATA SFR 指定。这种方法允许用户按页存取(256 页,每页 256 字节)外部数据 RAM 的整个范围。
第二种类型 MOVX 指令中,MOVX A,@DPTR,数据指针产生一个 16 位地址。这种形式在存取非常大的
数据数组(高达 64 KB)时,由于无需额外指令来设置地址的 8 个高位,所以更快、更高效。
可以混合使用两种类型。这为用户提供了四个独立的数据指针,两个直接寻址,两个按页存取,可寻址整
个外部存储器范围。
双数据指针
双数据指针加快了数据的块搬移。标准 DPTR 为 16 位寄存器,用于寻址外部存储器或外设。在 80515 核中,
标准数据指针为 DPTR,第二个数据指针为 DPTR1。数据指针选择位位于 DPS 寄存器的 LSB (DPS[0], SFR
0x92)。DPS[0] = 0 时选择 DPTR,DPS[0] = 1 时选择 DPTR1。
用户通过改变 DPS 寄存器的 LSB 实现指针之间的切换。数据指针中的数值不受 DPS 寄存器的 LSB 影响。
所有 DPTR 相关指令将使用当前的有效 DPTR 数值。
有些编译器不支持第二个数据指针。
DPTR1 对于数据搬迁非常有用,相对于从寄存器重新加载 DPTR,它可使此类操作更快。如果在中
断服务程序中使用 DPTR1 时,必须保存并恢复 DPS、DPTR 和 DPTR1,增大了堆栈使用量,同时也
延长了中断响应时间。
通过在 Keil 编译器项目设置中选择 R80515 核,以及使用编译器指令“MODC2”,可在特定的库中
使能双数据指针。
32
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
PDATA 寄存器(SFR 0xBF)提供了另一种数据指针(USR2),定义了使用指令 MOVX A,@Ri 或 MOVX @Ri,A
读/写 XDATA 时的 16 位地址的高字节。
内部数据存储器映射和存取
80515 内部有 256 字节(0x00 至 0xFF)的数据存储器。内部数据存储器地址始终为单字节宽,表 11 列出了
内部数据存储器映射。
特殊功能寄存器(SFR)占用高 128 个字节。内部数据存储器的 SFR 区域只能通过直接寻址使用,该区域的
内部 RAM 必须使用间接寻址存取。低 128 字节包含工作寄存器和位寻址存储器。低 32 字节形成 4 组八寄
存器(R0-R7)组。程序存储器状态字的两位(PSW,SFR 0xD0)选择使用哪组寄存器。接下来的 16 字节形成
一块位寻址存储器空间,位地址为 0x00-0x7F。低 128 字节中的全部字节通过直接或间接寻址存取。
表 11. 内部数据存储器映射
地址范围
2.4.2
直接寻址
间接寻址
特殊功能寄存器(SFR)
RAM
0x80
0xFF
0x30
0x7F
字节寻址区域
0x20
0x2F
位寻址区域
0x00
0x1F
工作寄存器组 R0…R7
特殊功能寄存器(SFR)
特殊功能寄存器的映射如表 12 所示。
SFR 存储器空间中只有少数几个地址被占用,其它无效。对未生效的地址进行读操作将返回未定义的数据,
写操作无影响。71M654x 所特有的 SFR 以粗体表示。地址为 0x80、0x88、0x90 等寄存器位可寻址,其它
均为字节寻址。
表 12. 特殊功能寄存器映射
十六/
二进
制
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
Rev 2
位寻址
X000
字节寻址
X001
X010
INTBITS
VSTAT
B
IFLAGS
A
WDCON
PSW
T2CON
IRCON
IEN1
IP1
S0RELH
P3 (DIO12:15)
FLSHCTL
IEN0
IP0
S0RELL
P2 (DIO8:11)
S0CON
S0BUF
IEN2
DPS
P1(DIO4:7)
TCON
TMOD
TL0
SP
DPL
P0 (DIO0:3)
X011
X100
X101
RCMD
SPI_CMD
X110
S1RELH
S1CON
TL1
DPH
X111
PDATA
FLSHPG
S1BUF
ERASE
TH0
DPL1
S1RELL
TH1
DPH1
EEDATA EECTRL
CKCON
PCON
二/十
六进
制
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
87
33
71M6541D/F/G 和 71M6542F/G 数据资料
2.4.3
通用 80515 特殊功能寄存器
表 13 列出了通用 80515 SFR 的位置、说明及默认值。关于寄存器的更多说明,可参见表中所列页码。
表 13. 通用 80515 SFR—地址和复位值
P0
地址
(十六进制)
0x80
复位值
(十六进制)
0xFF
SP
0x81
DPL
DPH
名称
说明
页码
端口 0
36
0x07
堆栈指针
35
0x82
0x00
数据指针,低 0
35
0x83
0x00
数据指针,高 0
35
DPL1
0x84
0x00
数据指针,低 1
35
DPH1
0x85
0x00
数据指针,高 1
35
PCON
0x87
0x00
UART 速度控制
39
TCON
0x88
0x00
定时器/计数器控制
42
TMOD
0x89
0x00
定时器/模式控制
40
TL0
0x8A
0x00
定时器 0,低字节
39
TL1
0x8B
0x00
定时器 1,低字节
39
TH0
0x8C
0x00
定时器 0,高字节
39
TH1
0x8D
0x00
定时器 1,高字节
39
CKCON
0x8E
0x01
时钟控制(展宽=1)
36
P1
0x90
0xFF
端口 1
36
DPS
0x92
0x00
数据指针选择寄存器
32
S0CON
0x98
0x00
串口 0,控制寄存器
38
S0BUF
0x99
0x00
串口 0,数据缓存器
36
IEN2
0x9A
0x00
中断使能寄存器 2
42
S1CON
0x9B
0x00
串口 1,控制寄存器
38
S1BUF
0x9C
0x00
串口 1,数据缓存器
36
S1RELL
0x9D
0x00
串口 1,重装载寄存器,低字节
36
P2
0xA0
0xFF
端口 2
36
IEN0
0xA8
0x00
中断使能寄存器 0
41
IP0
0xA9
0x00
中断优先级寄存器 0
45
S0RELL
0xAA
0xD9
串口 0,重装载寄存器,低字节
36
P3
0xB0
0xFF
端口 3
36
IEN1
0xB8
0x00
中断使能寄存器 1
41
IP1
0xB9
0x00
中断优先级寄存器 1
45
S0RELH
0xBA
0x03
串口 0,重装载寄存器,高字节
36
S1RELH
0xBB
0x03
串口 1,重装载寄存器,高字节
36
PDATA
0xBF
0x00
用于 [email protected] 的地址高字节—也称为 USR2
32
IRCON
0xC0
0x00
中断请求控制寄存器
42
T2CON
0xC8
0x00
用于 INT2 和 INT3 的极性
42
PSW
0xD0
0x00
程序状态字
35
WDCON
0xD8
0x00
波特率控制寄存器(仅使用 WDCON[7]位)
36
A
0xE0
0x00
累加器
35
B
0xF0
0x00
B 寄存器
35
34
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
累加器(ACC, A, SFR 0x E0):
ACC 为累加器寄存器,大多数指令使用累加器保存操作数。累加器相关指令的助记法将累加器记为 A,而
非 ACC。
B寄存器(SFR 0xF0):
B 寄存器用于乘、除指令的过渡,亦可作为中间结果寄存器保存临时数据。
程序状态字(PSW, SFR 0xD0 ):
该寄存器包含各种标识和控制位,用于选择寄存器组(见表 14)。
表 14. PSW 位功能(SFR 0xD0)
PSW 位
符号
功能
7
CV
进位标识。
6
AC
用于 BCD 操作的辅助进位标识。
5
F0
用户可使用通用 Flag 0。.
请勿将 F0 与 CESTATUS 寄存器中的 F0 标识混淆。
4
3
RS1
寄存器组选择控制位。RS1 和 RS0 的内容选择工作寄存器组:
RS1/RS0
所选组
00
第0组
位置
0x00 – 0x07
01
第1组
0x08 – 0x0F
10
第2组
0x10 – 0x17
11
第3组
0x18 – 0x1F
RS0
溢出标识。
2
OV
1
–
用户定义标识。
0
P
奇偶标识,受硬件影响,指示累加器中 1 位的奇、偶数,即奇偶性。
堆栈指针(SP, SFR 0x81):
堆栈指针为 1 字节寄存器,复位后初始化为 0x07。该寄存器在 PUSH 和 CALL 指令之前递增,即实际应用
中堆栈从位置 0x08 开始。
数据指针:
数据指针(DPTR 和 DPRT1)为 2 字节宽。低字节部分分别为 DPL (SFR 0x82)和 DPL1 (SFR 0x84)。高字节分
别为 DPH (SFR 0x83)和 DPH1 (SFR 0x85)。数据指针可作为两个寄存器(例如 MOV DPL, #data8)赋值。它
们一般用于存取外部代码或数据空间(例如分别为 MOVC A,@A+DPTR 或 MOVX A,@DPTR)。
程序计数器:
程序计数器(PC)为 2 字节宽,复位后初始化为 0x0000。该寄存器在执行指令或操作程序存储器的数据时自
动递增。
端口寄存器:
SEGDIO0 至 SEGDIO15 由特殊功能寄存器 P0、P1、P2 和 P3 控制,如表 15 所示。SEGDIO15 以上由
I/O RAM 中的 LCD_SEGDIOn[ ]控制。由每个 SFR Pn 寄存器的上半字节控制输入/输出方向,下半字节为
DIO 状态数据,可通过一次写操作配置指定 DIO 引脚的方向并设置其输出值,有利于实现位脉冲接口。向
DIO_DIR 位写 1,将 DIO 配置为输出;写 0 将其配置为输入。向 DIO 位写 1,使对应引脚为高电平(V3P3);
写 0 使对应引脚为低电平(GND)。更多详情请参见第 2.5.8 节数字 I/O。
Rev 2
35
71M6541D/F/G 和 71M6542F/G 数据资料
表 15. 端口寄存器(SEGDIO0-15)
SFR
名称
SFR
地址
P0
P1
P2
P3
0x80
0x90
0xA0
0xB0
D7
D6
D5
D4
DIO_DIR[3:0]
DIO_DIR[7:4]
DIO_DIR[11:8]
DIO_DIR[15:12]
D3
D2
D1
D0
DIO[3:0]
DIO[7:4]
DIO[11:8]
DIO[15:11]
芯片端口 P0-P3 为双向端口,对应 SEGDIO0-15 引脚。每个端口由锁存(SFR P0 至 P3)、输出驱动器和输
入缓冲器组成,因此 MPU 可通过其中任意端口输出或读取数据。即使 DIO 引脚配置为输出,MPU 仍可读
取该引脚状态,例如,在 CE 控制下通过 DIO 引脚对脉冲计数。
SEGDIO0-15 上电默认配置为输入,并且未使能。必须写 PORT_E = 1 (I/O RAM 0x270C[5])才能使
能 SEGDIO0-15。默认 PORT_E = 0,防止 SEGDIO0-15 上电复位时可能发生的短时间输出瞬态脉
冲。
时钟展宽(CKCON)
CKCON[2:0] (SFR 0x8E)寄存器的三个低有效位定义访问外设时用于 MOVX 指令的展宽存储周期。对于
71M6541D/F/G 和 71M6542F/G,该寄存器的实际值保证 CE、MPU 和 SPI 之间对 XRAM 的访问。不应更
改 CKCON[2:0]的默认设置(001)。
表 16 列出了展宽值从 0 置为 7 时,外部存储器接口的信号变化。信号宽度以 MPU 时钟周期计数,下表中
用粗体标记 CKCON[2:0] (001)的默认配置。
表 16. 展宽存储周期宽度
2.4.4
CKCON[2:0]
展宽值
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
读信号宽度
memaddr
1
2
3
4
5
6
7
8
memrd
1
2
3
4
5
6
7
8
写信号宽度
memaddr
2
3
4
5
6
7
8
9
memwr
1
1
2
3
4
5
6
7
指令集
支持通用 8051 微控制器的所有指令。71M654X 软件用户指南(SUG)提供了指令集及相关操作码的完整清
单。
2.4.5
UART
71M6541D/F/G 和 71M6542F/G 具有 UART (UART0),可设置为与各种 AMR 模块及其它外部器件通信。
第二个 UART (UART1)连接至光电接口,在 2.5.7 部分详细说明 UART 和光电接口。
UART 为专用 2 线串口,可与外部主控处理器以高达 38,400 bits/s (MPU 时钟 = 1.2288MHz 时)的速率通
信。RX 和 TX UART0 工作如下:
•
•
36
UART0 RX:该引脚用于串行数据输入,符合 RS-232 标准,LSB 在前输入字节。
UART0 TX:该引脚用于串行数据输出,LSB 在前输出字节。
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
提供丰富的 UART 相关寄存器,用于控制和缓存数据。
SxBUF 寄存器既作为发送缓存器,又作为接收缓存器(S0BUF,SFR 0x99 用于 UART0,S1BUF,SFR 0x9C
用于 UART1)。MPU 写入时,SxBUF 作为发送缓存器;MPU 读取时,作为接收缓存器。向发送缓存器写
数据,对应 UART 开始发送。接收缓存器读取接收到的、数据。两个 UART 可同时发送、接收数据。
WDCON[7] (SFR 0xD8)选择使用定时器 1 还是内部波特率发生器。所有 UART 均可使能奇偶校验、奇/偶校
验、2/1 个停止位和 XON/XOFF 选项,通信波特率范围:300~38400 bps。表 17 给出了波特率的计算方法,
表 18 列出了可选的 UART 工作模式。
表 17. 波特率发生器
使用定时器 1
(WDCON[7] = 0)
使用内部波特率发生器
(WDCON[7] = 1)
UART0
2smod * fCKMPU/ (384 * (256-TH1))
2smod * fCKMPU/(64 * (210-S0REL))
UART1
N/A
fCKMPU/(32 * (210-S1REL))
S0REL 和 S1REL 为 10 位组合可重装载寄存器(S0RELL、S0RELH、S1RELL、S1RELH 地址分别为 SFR 0xAA、
SFR 0xBA、FR 0x9D 和 SFR 0xBB)。SMOD 为 SFR PCON 寄存器(SFR 0x87)中的 SMOD 位。TH1(SFR 0x8D)
为定时器 1 的高字节。
表 18. UART 模式
UART 0
UART 1
模式 0
N/A
起始位,8 个数据位、奇偶校验、停止位、可
变波特率(内部波特率发生器)。
模式 1
起始位,8 个数据位、停止位、可变波特
率(内部波特率发生器或定时器 1)。
起始位,8 个数据位、停止位、可变波特率(内
部波特率发生器)。
模式 2
起始位,8 个数据位、奇偶校验、停止
位、固定波特率,1/32 或 1/64 fCKMPU。
N/A
模式 3
起始位,8 个数据位、奇偶校验、停止
位、可变波特率(内部波特率发生器或定
时器 1)。
N/A
发送数据的奇偶校验可通过累加器的 P 标识获得。7 位带奇偶校验的串行模式:如 FLAG 通讯协议,
可通过设置和读取 8 位输出数据中的第 7 位实现。7 位不带奇偶校验的串行模式,可将第 7 位固定
置 1。通过设置和读取第 9 位,模拟带奇偶校验的 8 位串行模式,利用 S0CON (SFR 0x98)和
S1CON (SFR 0x9B) 寄 存 器 中 的 控 制 位 TB80 (S0CON[3]) 和 TB81 (S1CON[3]) 进 行 发 送 操 作 ,
S1CON[2] 中的 RB81 用于接收操作。
接收的第 9 位(对 UART0 为模式 3,对于 UART1 为模式 A)可作为多处理器系统中处理器通信之间的握手
信号。这种情况下,从机将 SM20 (S0CON[5]) (UART0)或 SM21 (S1CON[5] (UART1)置 1。主机输出从地址
时,将第 9 位设为 1,使所有从机中的串口接收中断。从机将接收到的地址与本身地址进行比较。如果地
址匹配,从机清除 SM20 或 SM21 位,并接收剩余消息,其它从处理器忽略此消息。寻址从处理器后,主处
理器将第 9 位设为 0,输出剩余消息,产生从机串口接收中断。
Rev 2
37
71M6541D/F/G 和 71M6542F/G 数据资料
UART控制寄存器:
UART0 和 UART1 的功能分别取决于串行端口控制寄存器 S0CON、S1CON (如表 19 和表 20 所示)和 PCON
寄存器(如表 21 所示)。
虽然 TI0、RI0、TI1 和 RI1 位于 SFR 寻址字节中,但须避免清除常见位。因为位操作将被用
“读-修改-写”所在字节的硬件宏实现。如果在读操作之后、写操作之前发生中断,会错误地清
除标识。
清除这些标识位的正确方式是写一个掩码,其中除被清除位为零外,其它位均为 1。标识位写 1
将被硬件忽略。
表 19. S0CON (UART0)寄存器(SFR 0x98)
位
S0CON[7]
符号
功能
SM0 和 SM1 位设置 UART0 模式:
SM0
模式
0
1
2
3
说明
SM0
0
0
1
1
N/A
8 位 UART
9 位 UART
9 位 UART
SM1
0
1
0
1
S0CON[6]
SM1
S0CON[5]
SM20
S0CON[4]
REN0
如置位,使能串行接收。由软件清除,禁用接收。
S0CON[3]
TB80
模式 2 和 3 中发送数据的第 9 位。由 MPU 置位或清除,取决于要实现的
功能(奇偶校验、多处理器通信等)。
S0CON[2]
RB80
S0CON[1]
TI0
S0CON[0]
RI0
模式 2 和 3 中接收数据的第 9 位。模式 1 中,SM20 为 0,RB80 为停止
位。模式 0 中,不使用该位。必须由软件清除。
发送中断标识;完成一次串行传输后由硬件置位。 必须由软件清除(见上文
提示)。
接收中断标识;完成一次串行接收后由硬件置位。 必须由软件清除(见上文
提示)。
使能多机通信功能。
表 20. S1CON (UART1)寄存器(SFR 0x9B)
位
S1CON[7]
符号
SM
功能
设置 UART1 的波特率和模式。
0
模式
A
9 位 UART
可变
1
B
8 位 UART
可变
SM
说明
波特率
S1CON[5]
SM21
使能多机通信功能。
S1CON[4]
REN1
如置位,使能串行接收。由软件清除,禁用接收。
S1CON[3]
TB81
模式 A 中发送数据的第 9 位。由 MPU 置位或清除,取决于要实现的功能
(奇偶校验、多处理器通信等)。
S1CON[2]
RB81
模式 A 和 B 中发送数据的第 9 位。模式 B 中,如果 SM21 为 0,RB81 为
停止位。必须由软件清除。
S1CON[1]
TI1
发送中断标识,完成一次串行传输后由硬件置位。必须由软件清除(见上文
提示)。
S1CON[0]
RI1
接收中断标识,完成一次串行接收后由硬件置位。必须由软件清除(见上文
提示)。
38
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
表 21. PCON 寄存器位说明(SFR 0x87)
位
PCON[7]
符号
功能
SMOD 置位时波特率翻倍。
SMOD
定时器和计数器
2.4.6
80515 有两个 16 位定时器/计数器寄存器:定时器 0 和定时器 1。这些寄存器可配置为计数或定时功能。
定时器模式下,寄存器在每个机器周期递增,即每 12 个 MPU 时钟周期加 1。计数器模式下,每次在相应
输入信号 T0 或 T1 (T0 和 T1 为定时器输入,来自于特定的 DIO 引脚,参见第 2.5.8 节数字 I/O)观察到下降
沿时,寄存器递增。由于识别一次 1 至 0 跳变需要 2 个机器周期,所以最大输入计数率为 1/2 时钟频率
(CKMPU)。对占空比没有限制,然而为了正确识别 0 或 1 状态,输入应稳定至少 1 个机器周期。
定时器 0 和定时器 1 有四种工作模式可供选择,如表 22 和表 23.所示。TMOD (SFR 0x89)寄存器(见表 24)
用于选择相应模式。定时器或计数器功能由 TCON (SFR 0x88)寄存器控制,如表 25 所示。TCON 寄存器中
的 TR1 (TCON[6])和 TR0 (TCON[4])分别是定时器 1 和定时器 0 的启动位。
表 22. 定时器/计数器模式说明
M1
M0
模式
功能
0
0
模式 0
13 位计数器/定时器模式,低 5 位位于 TL0 或 TL1 (SFR 0x8A 或 SFR
0x8B)寄存器,其余 8 位位于 TH0 或 TH1 (SFR 0x8C 或 SFR 0x8D)寄存
器(分别为定时器 0 和定时器 1)。TL0 和 TL1 的 3 个位固定为零。
0
1
模式 1
16 位计数器/定时器模式。
1
0
模式 2
8 位自动重装载计数器/定时器。重装载值保存在 TH0 或 TH1,TL0 或
TL1 每个机器周期递增。TL(x)溢出时,TH(x)中的值被复制至 TL(x) (其
中,x 在计数器/定时器 0 时为 0,在计数器/定时器 1 时为 1)。
1
1
模式 3
如果定时器 1 的 M1 和 M0 置 1,定时器 1 停止。
如果定时器 0 的 M1 和 M0 置 1,定时器 0 作为两个独立的 8 位定时器
/计数器。
模式 3 中,TL0 受 TR0 和门控位影响,溢出标志位 TF0;TH0 受 TR1 位影响,溢出标志位 TF1。
表 23 给出了定时器 0 和定时器 1 允许的工作模式组合。
表 23. 定时器/计数器模式组合
定时器 1
Rev 2
模式 0
模式 1
模式 2
定时器 0 - 模式 0
允许
允许
允许
定时器 0 - 模式 1
允许
允许
允许
定时器 0 - 模式 2
不允许
不允许
允许
39
71M6541D/F/G 和 71M6542F/G 数据资料
表 24. TMOD 寄存器位说明 (SFR 0x89)
位
符号
定时器/计数器 1
TMOD[7]
Gate
TMOD[6]
C/T
TMOD[5:4] M1:M0
功能
如果 TMOD[7]置位,使能计数器 1 的外部输入信号控制。TCON 寄存器(SFR
0x88)中的 TR1 位也必须置位,允许计数器 1 递增。如此设置时,计数器 1 将根据
对应的一个或多个引脚信号的下降沿递增,如 DIO_R2 至 DIO_R11 寄存器内容规
定。参见第 2.5.8 节数字 I/O 和 LCD 段驱动器和表 47。
定时器或计数器的功能选择位。置 1 时,执行计数器操作。清 0 时,对应的寄存
器作为定时器。
选择定时器/计数器 1 的模式,如表 22 所示。
定时器/计数器 0
TMOD[3]
Gate
如果 TMOD[3]置位,使能计数器 0 的外部输入信号控制。TCON 寄存器(SFR
0x88)中的 TR0 位也必须置位,以允许计数器 0 递增。如此设置时,计数器 0 将会
根据对应的一个或多个引脚信号的下降沿递增,如 DIO_R2 至 DIO_R11 寄存器内
容规定。参见第 2.5.8 节数字 I/O 和 LCD 段驱动器和表 47。
TMOD[2]
C/T
定时器或计数器的功能选择位。置 1 时,执行计数器操作。清 0 时,对应的寄存
器作为定时器。
TMOD[1:0] M1:M0
选择定时器/计数器 0 的模式,如表 22 所示。
表 25. TCON 寄存器位功能(SFR 0x88)
位
符号
功能
TCON[7]
TF1
定时器 1 溢出标识位,由硬件置位。该位可由软件清零,或响应中断处理时硬件
自动清零。
TCON[6]
TR1
定时器 1 运行控制位。如清零,定时器 1 停止。
TCON[5]
TF0
定时器 0 溢出标志位,由硬件置位。该位可由软件清零,或响应中断处理时硬件
自动清零。
TCON[4]
TR0
定时器 0 运行控制位。如清零,定时器 0 停止。
TCON[3]
IE1
在外部引脚 int1 监测到下降沿时,通过硬件置位中断 1 边沿标志位。响应中断处
理时硬件自动清零。
TCON[2]
IT1
中断 1 类型控制位。选择输入引脚的下降沿或低电平触发中断。
TCON[1]
IE0
在外部引脚 int0 监测到下降沿时,通过硬件置位中断 0 边沿标志位。响应中断处
理时硬件自动清零。
TCON[0]
IT0
中断 0 类型控制位。选择输入引脚的下降沿或低电平触发中断。
2.4.7
WD定时器(软件看门狗定时器)
无内部软件看门狗定时器。代之以标准硬件看门狗定时器(见第 2.5.11 节硬件看门狗定时器)。
2.4.8
中断
80515 提供 11 种中断源,分四个优先级水平。每个中断源在特殊功能寄存器(TCON、IRCON 和 SCON)中
都有其自己的中断请求标识。利用 IEN0 (SFR 0xA8)、IEN1 (SFR 0xB8)和 IEN2 (SFR 0x9A)中的中断使能位,
可独立使能或禁用相应中断。
40
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
图 16 所示为器件中断结构。
参见图 16,中断源可来自 80515 MPU 核内部(称为内部源)或来自 71M654x SoC 的其它部分(称为外部源)。
有 7 种外部中断源,如图 16 最左侧及表 26 和表 27 所示(即 EX0-EX6)。
中断概述
发生中断时,MPU 向量指向预定义的地址,如表 38 所示。一旦开始中断服务,只有更高优先级的中断才
能将其打断。中断服务由中断返回指令 RETI 结束。执行 RETI 指令时,处理器返回发生中断时的下一条指
令。
发生中断条件时,处理器置位对应的中断标识位。无论此中断是否使能,该位均被置位。每机器周期采样
一次中断标识,然后由硬件轮询。中断使能时,如果采样表明有未处理的中断,则置位中断请求标识。在
下一个指令周期,如果满足以下条件,硬件强制 LCALL 转至相应的向量地址,从而响应中断:
•
•
•
没有在执行相同或更高优先级的中断。
当前正在执行某条指令,且尚未完成。
正在执行的指令不是 RETI 或者对寄存器 IEN0、IEN1、IEN2、IP0 或 IP1 的任何写操作。
用于中断的特殊功能寄存器
以下的 SFR 寄存器控制中断功能:
•
•
•
•
中断使能寄存器: IEN0、IEN1 和 IEN2 (见表 26、表 27 和表 28)。
定时器/计数器控制寄存器, TCON 和 T2CON (见表 29 和表 30)。
中断请求寄存器, IRCON (见表 31)。
中断优先级寄存器:IP0 和 IP1 (见表 36)。
表 26. IEN0 位功能(SFR 0xA8)
位
IEN0[7]
IEN0[6]
IEN0[5]
IEN0[4]
IEN0[3]
IEN0[2]
IEN0[1]
IEN0[0]
符号
EAL
WDT
–
ES0
ET1
EX1
ET0
EX0
功能
EAL = 0 禁用全部中断。
不用于中断控制。
未使用。
ES0 = 0 禁用串行通道 0 中断。
ET1 = 0 禁用定时器 1 溢出中断。
EX1 = 0 禁用外部中断 1:DIO 状态变化。
ET0 = 0 禁用定时器 0 溢出中断。
EX0 = 0 禁用外部中断 0:DIO 状态变化。
表 27. The IEN1 位功能 (SFR 0xB8)
Rev 2
位
IEN1[7]
IEN1[6]
IEN1[5]
符号
–
–
EX6
IEN1[4]
IEN1[3]
IEN1[2]
IEN1[1]
EX5
EX4
EX3
EX2
IEN1[0]
–
功能
未使用。
未使用。
EX6 = 0 禁用外部中断 6:
XFER_BUSY、RTC_1S、RTC_1M 或 RTC_T
EX5 = 0 禁用外部中断 5:EEPROM 或 SPI
EX4 = 0 禁用外部中断 4:VSTAT
EX3 = 0 禁用外部中断 3:CE_BUSY
EX2 = 0 禁用外部中断 2:
XPULSE、YPULSE、WPULSE 或 VPULSE
未使用。
41
71M6541D/F/G 和 71M6542F/G 数据资料
表 28. IEN2 位功能(SFR 0x9A)
位
符号
IEN2[0]
ES1
功能
ES1 = 0 禁用串行通道 1 中断。
表 29. TCON 位功能(SFR 0x88)
位
TCON[7]
TCON[6]
TCON[5]
TCON[4]
TCON[3]
TCON[2]
符号
TF1
TR1
TF0
TR0
IE1
IT1
TCON[1]
TCON[0]
IE0
IT0
功能
定时器 1 溢出标识。
不用于中断控制。
定时器 0 溢出标识。
不用于中断控制。
外部中断 1 标识:DIO 状态变化。
外部中断 1 类型控制位:
0 = 低电平中断。
1 = 下降沿中断。
外部中断 0 标识:DIO 状态变化。
外部中断 0 类型控制位:
0 = 低电平中断。
1 = 下降沿中断。
表 30. T2CON 位功能(SFR 0xC8)
位
T2CON[7]
T2CON[6]
符号
–
I3FR
T2CON[5]
I2FR
T2CON[4:0]
–
功能
未使用。
外部中断 3 的极性控制:CE_BUSY
0 = 下降沿。
1 = 上升沿。
外部中断 2 的极性控制:
XPULSE、YPULSE、WPULSE 和 VPULSE
0 = 下降沿。
1 = 上升沿。
未使用。
表 31. IRCON 位功能(SFR 0xC0)
42
位
IRCON[7]
符号
–
功能
未使用。
IRCON[6]
–
未使用。
IRCON[5]
IEX6
IRCON[4]
IEX5
IRCON[3]
IEX4
IRCON[2]
IEX3
1 = 发生外部中断 6,且尚未清除:
XFER_BUSY、RTC_1S、RTC_1M 或 RTC_T
1 = 发生外部中断 5,且尚未清除:
EEPROM 或 SPI
1 = 发生外部中断 4,且尚未清除:
VSTAT
1 = 发生外部中断 3,且尚未清除:
CE_BUSY
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
IRCON[1]
IEX2
IRCON[0]
–
1 = 发生外部中断 2,且尚未清除:
XPULSE、YPULSE、WPULSE 或 VPULSE
未使用。
TF0 和 TF1 (定时器 0 和定时器 1 溢出标识)由硬件在服务例程调用时自动清零(调用服务例程时,信
号 T0ACK 和 T1ACK—端口 ISR—高电平有效)。
Rev 2
43
71M6541D/F/G 和 71M6542F/G 数据资料
外部MPU中断
这 7 种外部中断是在 80515 核外部的中断,即由 71M654x 其它电路产生,例如:CE、DIO、RTC 或
EEPROM 接口。
外部中断连接如表 32 所示。中断 2 和中断 3 的极性可在 MPU 中通过 T2CON (SFR 0xC8)的 I3FR 和 I2FR
位设置。中断 2 和中断 3 应设置为下降沿触发(I3FR = I2FR = 0)。通用 8051 MPU 资料规定中断 4 至 6 定义
为上升沿触发。所以,连接至中断 5 和 6 的下降沿触发信号在内部进行了反相,实现表 32 所示的触发沿极
性。
表 32. 外部 MPU 中断
外部中断
连接
极性
标识复位
0
数字 I/O
见 2.5.8
自动
1
数字 I/O
CE_PULSE
见 2.5.8
自动
2
上升
自动
3
CE_BUSY
下降
自动
4
VSTAT (VSTAT[2:0]改变)
上升
自动
5
EEPROM busy (下降), SPI (上升)
6
XFER_BUSY (下降), RTC_1SEC, RTC_1MIN, RTC_T
(上升)
自动
下降
手动
外部中断 0 和 1 可通过 DIO 映射表映射到器件引脚,更多信息请参见第 2.5.8 节数字 I/O。
SFR 对应的中断使能位必须置 1,才能允许相应中断发生。同样,每种中断都有其自身的标识位,由中断
硬 件 设 置 , 并 由 MPU 响 应 中 断 处 理 程 序 后 复 位 。 除 了 外 部 中 断 6 、 5 和 2 使 能及 其 标 识 位 外,
XFER_BUSY、RTC_1SEC、RTC_1MIN、RTC_T、SPI、EEPROM 和 4 个 W/V/X/YPULSE 都需要其自
身的使能和标识位(见表 33:中断使能和标识位)。
IE0 至 IEX6 在硬件指向中断处理程序后自动清除。其它标识,IE_XFER 至 IE_VPULSE,必须软
件写 0 清除。
由于这些位位于 SFR 寻址字节内,多数应用中通过位操作将其清除,但在此必须避免。硬件以
一个字节宽的“读-修改-写”硬件宏实现位操作。如果在读操作之后、写操作之前发生中断,其标
识将被意外清除。
清除标识位的正确方式是写一个掩码,除被清除位为零外,其它位均为 1。标识位写 0 清除,写
1 时硬件忽略。
表 33. 中断使能和标识位
中断使能
44
中断标识
中断说明
名称
位置
名称
位置
EX0
SFR 0xA8[[0]
IE0
SFR 0x88[1]
外部中断 0
EX1
SFR 0xA8[2]
IE1
SFR 0x88[3]
外部中断 1
EX2
SFR 0xB8[1]
IEX2
SFR 0xC0[1]
外部中断 2
EX3
SFR 0xB8[2]
IEX3
SFR 0xC0[2]
外部中断 3
EX4
SFR 0xB8[3]
IEX4
SFR 0xC0[3]
外部中断 4
EX5
SFR 0xB8[4]
IEX5
SFR 0xC0[4]
外部中断 5
EX6
EX_XFER
EX_RTC1S
EX_RTC1M
SFR 0xB8[5]
0x2700[0]
0x2700[1]
0x2700[2]
IEX6
IE_XFER
IE_RTC1S
IE_RTC1M
SFR 0xC0[5]
SFR 0xE8[0]
SFR 0xE8[1]
SFR E0x8[2]
外部中断 6
XFER_BUSY 中断(int 6)
RTC_1SEC 中断(int 6)
RTC_1MIN 中断(int 6)
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
中断使能
中断标识
中断说明
名称
位置
名称
位置
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
0x2700[4]
0x2701[7]
0x2700[7]
0x2700[6]
0x2700[5]
0x2701[6]
0x2701[5]
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR 0xE8[4]
SFR 0xF8[7]
SFR 0xE8[7]
SFR 0xE8[6]
SFR 0xE8[5]
SFR 0xF8[4]
SFR 0xF8[3]
RTC_T 报警时钟中断(int 6)
SPI 中断
EEPROM 中断
CE_XPULSE 中断(int 2)
CE_YPULSE 中断(int 2)
CE_WPULSE 中断(int 2)
CE_VPULSE 中断(int 2)
中断优先级结构
全部中断源被分组,如表 34 所示。
表 34. 中断优先级组
组
组成内容
0
外部中断 0
1
定时器 0 中断
2
3
4
5
串行通道 1 中断
–
–
外部中断 2
外部中断 1
–
外部中断 3
定时器 1 中断
–
外部中断 4
串行通道 0 中断
–
–
外部中断 5
–
外部中断 6
外部中断 0~6 的优先级由 IP0 (SFR 0xA9)和 IP1 (SFR 0xB9)共同决定(表 36)。每个中断支持四级优先级(如表
35 所示)。如果同时接收到相同优先级中断请求,8051 将会按照表 37 所示的内部轮询顺序决定首先处理哪
个请求。
如果在中断使能的情况下修改中断优先级,此时很容易引起软件问题。因此推荐在中断使能之前时
初始化中断优先级。
表 35. 中断优先级
优先级
IP1[x]
IP0[x]
0
0
优先级 0 (最低)
0
1
优先级 1
1
0
优先级 2
1
1
优先级 3 (最高)
表 36. 中断优先级寄存器(IP0 和 IP1)
寄存器
地址
IP0
IP1
SFR 0xA9
SFR 0xB9
Rev 2
第7位
(MSB)
–
–
第6位
第5位
第4位
第3位
第2位
第1位
–
–
IP0[5]
IP1[5]
IP0[4]
IP1[4]
IP0[3]
IP1[3]
IP0[2]
IP1[2]
IP0[1]
IP1[1]
第0位
(LSB)
IP0[0]
IP1[0]
45
71M6541D/F/G 和 71M6542F/G 数据资料
表 37. 中断轮询排序
外部中断 0
串行通道 1 中断
定时器 0 中断
外部中断 1
外部中断 3
定时器 1 中断
轮询排序
外部中断 2
外部中断 4
串行通道 0 中断
外部中断 5
外部中断 6
中断源和向量
表 38 中列出了中断及其对应的标识和向量地址。
表 38. 中断向量
中断请求标识
46
说明
中断向量地址
IE0
外部中断 0
0x0003
TF0
定时器 0 中断
0x000B
IE1
外部中断 1
0x0013
TF1
定时器 1 中断
0x001B
RI0/TI0
串行通道 0 中断
0x0023
RI1/TI1
串行通道 1 中断
0x0083
IEX2
外部中断 2
0x004B
IEX3
外部中断 3
0x0053
IEX4
外部中断 4
0x005B
IEX5
外部中断 5
0x0063
IEX6
外部中断 6
0x006B
Rev 2
71M6541D/F/G 和 1M6542F/G 数据资料
0
External
Source
Internal
Source
Individual
Enable Bits
Individual Flags
DIO
DIO status
changed
DIO_Rn
TCON.1 (IE0)
byte received
UART1
(optical)
Logic and Polarity
Selection
Interrupt
Flags
Interrupt Enable
IEN0.7
(EAL)
IEN0.0
(EX0)
Priority
Assignment
IT0
IEN2.0
(ES1)
S1CON.0 (RI1)
IP1.0/
IP0.0
>=1
byte transmitted
S1CON.1 (TI1)
IEN0.1
(ET0)
Timer 0
XPULSE
YPULSE
2
1
3
overflow occurred
CE detected zero
crossing
CE detected sag
EX_XPULSE
TCON.5 (TF0)
EX_YPULSE
IE_YPULSE
WPULSE
Wh pulse
EX_WPULSE
IE_WPULSE
VPULSE
VARh pulse
EX_VPULSE
IE_VPULSE
DIO_Rn
TCON.3 (IE1)
DIO
CE_BUSY
DIO status
changed
IEN1.1
(EX2)
IE_XPULSE
>=1
I3FR
overflow occurred
VSTAT
IEN0.3
(ET1)
TCON.7 (TF1)
>=1
byte transmitted
5
command
received
XFER_BUSY
accumulation
cycle completed
RTC_1M
RTC_T
EX_EEX
S0CON.0 (TI0)
IEN1.4
(EX5)
IE_EEX
>=1
SPI
RTC_1S
6
BUSY fell
IEN0.4
(ES0)
S0CON.0 (RI0)
UART0
EEPROM
every second
every minute
alarm clock
EX_SPI
IP1.4/
IP0.4
IRCON.4
(IEX5)
IE_SPI
EX_XFER
IE_XFER
EX_RTC1S
IE_RTC1S
EX_RTC1M
IE_RTC1M
IEN1.5
(EX6)
IP1.5/
IP0.5
IRCON.5
(IEX6)
>=1
EX_RTCT
Flag=1
means that
an interrupt
has occurred
and has not
been cleared
IE_RTCT
EX0 – EX6 are cleared
automaticallywhen the
hardware vectors to the
interrupt handler
Interrupt
Vector
3/19/2010
“Internal Source”表示来自于 80515 MPU 核的中断源。
“External Source” 表示来自于 71M654x SoC 其它电路、在 80515 MPU 核之外的中断源。
图 16. 中断结构
Rev 2
IP1.3/
IP0.3
IRCON.3
(IEX4)
Supply status changed
byte received
IP1.2/
IP0.2
IRCON.2
(IEX3)
IEN1.3
(EX4)
4
IP1.1/
IP0.1
IEN0.2
(EX1)
IEN1.2
(EX3)
CE completed code run and
has new status information
Timer 1
I2FR
IRCON.1
(IEX2)
Polling Sequence
No.
47
71M6541D/F/G 和 71M6542F/G 数据资料
2.5
片上资源
2.5.1
物理存储器
2.5.1.1 闪存模式
器件包括 128KB (71M6541G、71M6542G)、64KB (71M6542F、71M6541F)或 32KB (71M6541D)片上
FLASH,用来装载 MPU 和 CE 程序代码。它还包括 CE RAM 和 I/O RAM 映像。上电时,使能 CE 之前,
MPU 需要将这些映像复制到各自位置。
CE 程序空间限制为 4096 个 16 位字(8KB)。并且它在 FLASH 的起始地址必须以完整的 1KB 为单位。
CE_LCTN[5:0]字段(I/O RAM 0x2109[5:0])定义哪个 1KB 边界含有 CE 代码。所以,第一条 CE 指令位于
1024*CE_LCTN[5:0]。
FLASH 可由 MPU、CE 及 SPI 接口(读/写)访问。
表 39. 闪存访问
访问者
访问类型
条件
MPU
R/W/E
只有 CE 被禁用时才能写和擦除。
CE
SPI
R
R/W/E
只有调用 SFM (MPU 暂停)时才可访问。
FLASH 写操作步骤
如 果 FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4]) 密 钥 设 置 正 确 , MPU 可 写 入 FLASH 。 这 是 除 外 部
EEPROM 之外,用户可以操作的非易失存储器之一。
FLASH 程序写使能位 FLSH_PWE (SFR 0xB2[0])用来区分存储器指令([email protected],A)操作的是 FLASH
还是 XRAM。该位由硬件在每个字节写操作之后自动清零。使能中断时,禁止对该位进行写操作。
如果 CE 位使能(CE_E = 1,I/O RAM 0x2106[0]),FLASH 写操作只有在 FLSH_PSTWR (SFR 0xB2[2])置位时
才有效,该位使能“posted flash write”。CE_E = 0 时,FLSH_PSTWR 操作无效;而 CE_E = 1 时,
FLSH_PSTWR 延迟 FLASH 写操作,延时间隔为 CE 程序的执行周期。延迟时间内, FLSH_PEND 位(SFR
0xB2[3])置 1,MPU 继续执行命令。CE 程序周期结束时(CE_BUSY 变低), FLSH_PEND 位清零,同时进
行写操作。MPU 可查询 FLSH_PEND 位,确定何时完成写操作。FLSH_PEND = 1 时,忽略其它 FLASH 写
操作请求。
更新 FLASH 的个别字节
FLASH 单元的初始值为 0xFF (全部位为 1)。将非 0xFF 数值写入 FLASH 单元时,首先需要擦除该单元。
由于单元不能独立擦除,所以需要将整页内容复制到 RAM,然后擦除该页。之后,更新需要的 RAM 内容,
再写回至 FLASH。
FLASH 擦除步骤
按照一定的顺序,将特定的操作码写入至特定 SFR 寄存器,才能启动 FLASH 擦除功能。这些特殊的操作
码/顺序可以防止 FLSH 的意外擦除。
整体擦除顺序为:
•
•
写 1 至 FLSH_MEEN 位(SFR 0xB2[1])。
写操作码 0xAA 至 FLSH_ERASE 寄存器(SFR 0x94)。
该功能只有在 ICE 端口使能(即硬件的 ICE_E 引脚拉高)时才有效。
48
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
页擦除顺序为:
•
•
写页地址至 FLSH_PGADR[5:0] (SFR 0xB7[7:2] )。
写操作码 0x55 至 FLSH_ERASE 寄存器(SFR 0x94)。
程序加密
加密位使能时,安全机制将限制 ICE 除全局 FLASH 擦除之外的任何操作,确保用户 MPU 和 CE 程序代码
的安全。用户需要在主程序执行前的 64 个 CKMPU 周期内使能 SECURE 位,启用加密功能。一旦加密机
制使能,将其禁用的唯一方式是执行 FLASH 全局擦除,然后进行芯片复位。
MPU 引导代码的前 64 个周期称为预引导阶段,ICE 在该阶段禁用。PREBOOT (SFR 0xB2[7])位是该阶段的
只读状态位,MPU 可以通过它识别启动阶段。完成预引导后,可使能 ICE,并允许控制 MPU。
芯片复位时,安全使能位 SECURE (SFR 0xB2[6])也同时复位,与该位相关的硬件只允许写 1。所以,在预
引导代码内需要置位 SECURE 位来使能安全特性,一旦使能,软件将无法取消该功能。同时预引导代码受
到保护,外部将无法读取任何程序代码。
具体说,SECURE 置位时,以下情况适用:
•
•
•
ICE 仅限于整体 FLASH 擦除。
FLASH 的 0 页,用户预引导代码的首选位置,不可被 MPU 或 ICE 页擦除。第 0 页只能通过全局
FLASH 擦除。
禁止 MPU 或 ICE 对 0 页进行写操作。
71M6541D/F/G 和 71M6542F/G 还具有防止意外写入及擦除 FLASH 的硬件机制。为了使能 FLASH 写入和
擦 除 操 作 , 必 须 向 FLSH_UNLOCK[3:0] 字 段 写 入 4 位 硬 件 密 钥 。 密 钥 为 二 进 制 数 ‘0010’ 。 如 果
FLSH_UNLOCK[3:0]不是‘0010’,硬件禁止 FLASH 擦除和写操作。在 SPI FLASH 编程(SFM 模式)时,密
钥应由外部 SPI 主控器件写入;或者在 ICE FLASH 编程时,通过 ICE 接口写入。使用装载器功能时,应
该将密钥送至装载程序,由装载程序将其写入 FLSH_UNLOCK[3:0]。 FLSH_UNLOCK[3:0]不自动复位,应
该在 SPI 或 ICE 结束更改 FLASH 时将其清零。表 40 中汇总了用于 FLASH 安全的 I/O RAM 寄存器。
表 40. 闪存加密
位置
复位
唤醒
方向
说明
FLSH_UNLOCK[3:0]
2702[7:4]
0
0
R/W
必须为 2,才允许 FLASh 的写操作,更多详
情参见 FLASH 安全说明。
SECURE
SFR B2[6]
0
0
R/W
禁止擦除 0 页及 CE_LCTN[5:0] (I/O RAM
0x2109[5:0])定义的 CE 代码开始以上的地
址 。 也 禁 止 通 过 ICE 和 SPI 端 口 读
FLASH。
名称
SPI FLASH 模式
一般器件的 SPI 从接口不能读或写 FLASH。然而,71M6541D/F/G 和 71M6542F/G 具有特殊 FLASH 模式
(SFM),以方便用户的初始(生产)编程。71M654x 处于 SFM 模式时,SPI 接口可擦除、读和写 FLASH。该
模式下,SPI 不可访问其它存储器元件,例如 XRAM 和 I/O RAM。为保护 FLASH 内容,需要几步操作才
能激活 SFM 模式。
关于 SFM 详情请参见第 2.5.10 节(SPI 从机接口)。
Rev 2
49
71M6541D/F/G 和 71M6542F/G 数据资料
2.5.1.2 MPU/CE RAM
71M654x 包括 3~5KB 片上静态 RAM 存储器(XRAM)和 MPU 核的 256 字节内部 RAM。静态 RAM 用于
MPU 和 CE 操作的数据存储。
2.5.1.3 I/O RAM (配置RAM)
I/O RAM 可看做是一系列控制基本硬件功能的寄存器。I/O RAM 地址空间从 0x2000 开始。表 74 列出了
I/O RAM 寄存器。
71M6541D/F/G 和 71M6542F/G 在 I/O RAM 地址空间包括 128 字节片上非易失 RAM 存储器(地址 0x2800
至 0x287F)。该存储器部分由 VBAT_RTC 引脚的电压支持,只要 VBAT_RTC 上的电压处于规定范围内
(2.0~3.8V),在 BRN、LCD 和 SLP 模式下就可保持其中的数据。
2.5.2
振荡器
振荡器驱动标准的 32.768kHz 钟表晶体。这种类型的晶体具有较高精度,且驱动功耗很小。振荡器经过特
殊设计,配合钟表晶体工作,支持高阻、低功耗操作。振荡器功耗非常低,可有效延长连接至 VBAT_RTC
的电池寿命。
振荡器校准可提高 RTC 和表计精度,更多信息请参见第 2.5.4 节实时时钟(RTC)。
振荡器由 V3P3SYS 引脚或 VBAT_RTC 引脚供电,取决于 V3OK (即如果 V3P3SYS ≥ 2.8 VDC, V3OK =
1;如果 V3P3SYS < 2.8 VDC,V3OK = 0)。振荡器消耗大约 100nA,相对于电池内部漏电流可忽略不计。
2.5.3
PLL和内部时钟
器件时钟源来自 32.768 kHz 晶振输出,经过 PLL 倍频 600 倍,得到 19.660800 MHz 的主控时钟(MCK)。
除 RTC 时钟之外,所有片上定时都源于 MCK。表 41 为时钟功能及其控制汇总。
MPU 中的两个通用计数器/定时器由 CKMPU 控制(参见第 2.4.6 节定时器和计数器)。
通过设置 PLL_FAST 位= 1 (I/O RAM 0x2200[4]),主控时钟可升至 19.66MHz;通过设置 PLL_FAST = 0,
可降至 6.29MHz。MPU 时钟频率 CKMPU 可由 I/O RAM 控制字段 MPU_DIV[2:0] (I/O RAM 0x2200[2:0])控
制分频输出,设为 MCK*2-(MPU_DIV+2),其中, MPU_DIV[2:0]为 0 至 4。通过降低 MPU 时钟频率,可减小
71M654x 电流损耗。ICE_E 引脚为高电平时,电路还产生 9.83MHz 时钟,供仿真器使用。
LCD_BSTE 禁用时,PLL 只有在 SLP 模式或 LCD 模式下关闭。LCD_BSTE 取决于 LCD_VMODE [1:0]字
段的设置(见表 56)。
该部件从 SLP 或 LCD 模式唤醒时,PLL 在 6.29 MHz 模式下开启,PLL_OK 标识(SFR 0xF9[4])置 1 之前
PLL 频率不精确。由于潜在的过冲,在 PLL_OK 为 1 之前,MPU 不应更改 PLL_FAST 值。
50
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
表 41. 时钟系统汇总
时钟
固定频率或范围
源自
PLL_FAST=1
OSC
晶体
MCK
晶体/PLL
CKCE
MCK
CKADC
MCK
CKMPU
MCK
CKICE
MCK
CKOPTMOD
MCK
CK32
MCK
2.5.4
PLL_FAST=0
32.768 kHz
–
19.660800MHz
6.291456MHz
PLL_FAST
(600*CK32)
(192*CK32)
4.9152MHz
1.5728MHz
–
1.572864MHz,
4.9152MHz,
ADC_DIV
2.4576MHz
0.786432MHz
4.9152MHz …
1.572864MHz…
MPU_DIV[2:0]
307.2kHz
98.304kHz
9.8304MHz…
3.145728MHz …
MPU_DIV[2:0]
196.608kHz
614.4kHz
38.40kHz
32.768kHz
38.6kHz
功能
控制
晶振时钟
主控时钟
CE 时钟
ADC 时钟
MPU 时钟
ICE 时钟
–
光 UART 调
制
–
32kHz 时钟
实时时钟(RTC)
2.5.4.1 RTC概述
RTC 由晶振直接驱动,由 V3P3SYS 引脚或 VBAT_RTC 引脚供电,取决于 V3OK。RTC 由计数器链和输
出寄存器组成。计数器链由秒、分、时、星期、日、月和年寄存器组成。链寄存器支持影子寄存器功能,
方便读写操作。
表 42 列出了 RTC 控制的 I/O RAM 寄存器。
2.5.4.2 访问RTC
RTC_RD (I/O RAM 0x2890[6])位和 RTC_WR (I/O RAM 0x2890[7])位,用控制影子寄存器功能。
RTC_RD 为低电平时,RTC 每 2ms 更新一次影子寄存器。RTC_RD 为高电平时,暂停更新,影子寄存器内
容保持不变,适合 MPU 读取。所以,MPU 希望读取 RTC 时,通过设置 RTC_RD 位冻结影子寄存器,读取
影子存器,然后将 RTC_RD 位置低,恢复更新影子寄存器。RTC_RD 位在 RTC 更新完影子寄存器后自动
清除。由于 RTC 更新频率 500Hz,因此 RTC_RD 位从高变低到影子寄存器接收第一次更新,大约延迟
2ms。
RTC_WR 为高电平时,也禁止影子寄存器的更新。在此期间,MPU 可以修改影子寄存器的内容。RTC_WR
变低时,硬件电路将在下一个 2ms 之内使用影子寄存器覆盖 RTC 寄存器。影子寄存器中的每个字包括一
个变更位,确保 MPU 向 RTC_WR 写 0 时只更新编程字。RTC_WR 位在 RTC 将影子寄存器更新至 RTC 寄
存器之后自动清除。
RTC 的亚秒寄存器 RTC_SBSC (I/O RAM 0x2892)在一次秒中断之后、下一个秒中断边界之前可由 MPU 读取。
RTC_SBSC 寄存器表示到下一个秒边界剩余的 1/128 秒周期的数量。写 0x00 至 RTC_SBSC 复位计数器,重
新开始从 0 至 127 计数。读和复位亚秒计数器可作为准确设置 RTC 的算法的一部分。
RTC 能够处理闰年。每个计数器都有其自身的输出寄存器。RTC 链寄存器不受复位引脚、看门狗定时器复
位或电池模式和任务模式之间转换的影响。
Rev 2
51
71M6541D/F/G 和 71M6542F/G 数据资料
表 42. RTC 控制寄存器
名称
位置
复位
唤醒
方向
说明
RTC_ADJ[6:0]
2504[6:0]
00
–
R/W
用于模拟 RTC 频率调节的寄存器。
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
RTC_Q[1:0]
289B[2:0]
289C[7:0]
289D[7:2]
289D[1:0]
4
0
0
0
4
0
0
0
R/W
用于数字 RTC 调节的寄存器。有效范围:
0x0FFBF ≤ RTC_P ≤ 0x10040
R/W
用于数字 RTC 调节的寄存器。
RTC_RD
2890[6]
0
0
R/W
冻结 RTC 影子寄存器,使其适合于 RTC 读取。
读 RTC_RD 时,返回影子寄存器的状态:0 = 更
新,1 = 冻结。
RTC_WR
2890[7]
0
0
R/W
冻结 RTC 影子寄存器,使其适合于 RTC 写操
作。RTC_WR 被清除时,在下一个 RTC 时钟(大
约 500Hz)将影子寄存器的内容写入 RTC 寄存
器。读 RTC_WR 时,只要 RTC_WR 置位,则返
回 1。在 RTC 寄存器更新之前,它将继续返回
1。
RTC_FAIL
2890[4]
0
0
R/W
表示 RTC 发生计数错误,此时时间不可信。该位
可通过写 0 清除。
RTC_SBSC[7:0]
2892[7:0]
R
自上 1 秒边界的时间,LSB = 1/128 秒。
2.5.4.3 RTC频率控制
提供两种频率修正方法:
•
•
第一种方法是模拟频率修调,使用 I/O RAM 寄存器 RTCA_ADJ[6:0] (I/O RAM 0x2504[6:0]),微调晶振
负载电容。
第二种方法是数字频率修正,调整 RTC 时钟频率。
将 RTCA_ADJ[6:0]设为 00,对应负载电容最小化,振荡器频率最大化。将 RTCA_ADJ[6:0]设为 7F,将负
载电容最大化,振荡器频率最小化。可调电容大约为:
C ADJ =
RTCA _ ADJ
⋅ 16.5 pF
128
最小调整量(大约为 0.3ppm)取决于晶振特性、PCB 布局及外部晶振电容的值。任何时候均可调节,并应该
在 1 秒间隔内测量获得的时钟频率。
第二种频率修调方法为数字式,调节范围±988ppm,分辨率为 3.8 ppm (±1.9 ppm)。注意,3.8 ppm 对应
于 4*RTCP+RTCQ 构成的 19 位参量数的 1 个 LSB,1.9ppm 对应于½ LSB。速率调节从调整后的下一个秒
边界开始执行。由于 LSB 造成每次调整为 4 秒,所以应在 4 秒的整数倍间隔内测量频率。
通过向 RTC_P[16:0] (I/O RAM 0x289B[2:0]、0x289C, 0x289D[7:2])和 RTC_Q[1:0] (I/O RAM 0x289D[1:0])写
入相应数值调节时钟频率。如上所述,通过影子寄存器更新 RTC 速率调节寄存器 RTC_P 和 RTC_Q。
RTC_WR (I/O RAM 0x2890[7])降低时,新值被加载至计数器。
默认频率为 32,768 RTCLK 周期/秒。为了将时钟频率改变 Δppm,利用下式计算 RTC_P 和 RTC_Q:

 32768 ⋅ 8
4 ⋅ RTC_P + RTC_Q = floor 
+ 0.5 
−6

 1 + ∆ ⋅10
相反,给定 4RTC_P+RTC_Q 数值时,ppm 变化量为:
∆ () = �
52
32768 ∙ 8
− 1� 106
4 ∗  + 
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
例如,对于-988ppm 的变化,4·RTC_P + RTC_Q = 262403 = 0x40103。RTC_P = 0x10040,RTC_Q = 0x03。
RTC_P 和 RTC_Q 的默认值分别为 0x10000 和 0x0,对应于 0 调节。
TMUX2OUT 测试引脚的两种设置,PULSE_1S 和 PULSE_4S,可用于测量和校准 RTC 时钟频率。其占
空比大约为 25%,周期为 1s 或 4s 的方波
RTCA_ADJ、RTC_P 和 RTC_Q 的默认值应为标称值,处于调节范围的中间。写入非法数值 (比如
RTC_P 写 0)会造成工作不正常。
如果已知晶振的温度系数,MPU 可根据集成的温度传感器,在必要时修正 RTC 时钟。或者,将温度补偿
值写入 RTC 调整 NV RAM (注,此处的 128 字节与 IO RAM 区不是同一存储块),并置位 OSC_COMP 位
(I/O RAM 0x28A0[5])。这种情况下,即使在 LCD/SLP 模式,振荡器也可以自动修正。详情请参见实时
RTC 温度补偿部分。
2.5.4.4 RTC温度补偿
71M6541D/F/G 和 71M6542F/G 可配置为定期测量管芯温度,包括 SLP 模式、LCD 模式和 MPU 停止模式。
如果由 OSC_COMP 位使能,硬件电路可根据温度信息查表,修正晶振输出频率,无需 MPU 介入。查找表
是 RTC 专用的 128 字节 NV RAM 存储器,用户需要在启动 OSC_COMP 之前填写适当的频率修正数据。
表 43 所示为用于自动 RTC 温度补偿的 I/O RAM 寄存器。
表 43. 用于 RTC 温度补偿的 I/O RAM 寄存器
名称
OSC_COMP
位置
28A0[5]
复位
唤醒
方向
说明
0
0
R/W
使能 RTC_P 和 RTC_Q 在每次温度测量时被自动更
新。
温度测量结果(10 位数据加 1 个符号位)。
整体读取 16 位 STEMP[10:0]数据,然后右移 5
位。如以下代码所示:
volatile int16_t xdata STEMP _at_0x2881;
fa = (float)(STEMP/32);
读和写 RTC 查找表的 RAM 地址。
自 动 递 增 标 识 。 置 位 时 , LKPADDR[6:0] 在
LKP_RD 或 LKP_WR 位在每次触发后自动递增。
递增地址可从 LKPADDR[6:0]读取。
STEMP[10:3]
STEMP[2:0]
2881[7:0]
2882[7:5]
–
–
R
LKPADDR[6:0]
2887[6:0]
0
0
R/W
LKPAUTOI
2887[7]
0
0
R/W
LKPDAT[7:0]
2888[7:0]
0
0
R/W
读/写 RTC 查找 RAM 数据。
LKP_RD
LKP_WR
2889[1]
2889[0]
0
0
0
0
R/W
R/W
用于 RTC 查找表 RAM 读/写的选通位。置位时,
LKPADDR 和 LKPDAT 寄存器用于读或写操,操作
完成后选通位硬件清除。如果此时 LKPAUTOI 置
位, LKPADDR 自动递增。
参见图 17,查表法通过将 STEMP[10:0]寄存器中的 10 位加符号位数值右移 2 位,获得 8 位加符号位数值
(即 NV RAM 地址 = STEMP/4)。限制器确保得到的查找地址在 6 位加符号位范围:-64 至+63 (十进制)之内。
地址指向的 8 位 NV RAM 内容作为 2 的补码增加至 4*RTC_P + RTC_Q 标称值,0x40000。
关于利用寄存器 RTC_P[16:0] (I/O RAM 0x289B[2:0] 、 0x289C 、 0x289D[7:2])和 RTC_Q[1:0] (I/O RAM
0x2891[1:0]进行时钟频率调整的内容,请参见第 2.5.4.3 节 RTC 频率控制。必须正确定标加载至 NV RAM
的 8 位值,以便与第 2.5.4.3 节 RTC 频率控制给定的 RTC_P 和 RTC_Q 公式一致。注意,8 位 2 的补码查找
值与 0x40000 之和构成一个 19 位数值,等于 4*RTC_P+RTC_Q,如图 17 所示。每次查找及求和运算后,
温度补偿输出自动加载 RTC_P[16:0]和 RTC_Q[1:0]寄存器。
Rev 2
53
71M6541D/F/G 和 71M6542F/G 数据资料
LIMIT
STEMP
10+S
>>2
8+S
Look Up
RAM
63
ADDR
-256
-64
63
255
6+S
Q
-64
Σ
7+S
19
4*RTC_P+RTC_Q
19
0x40000
图 17. 自动温度补偿
128 个 NV RAM 单元以 2 的补码形式组合,如表 44 所示。如上所述,STEMP[10:0]数字温度补偿值标定为
对应 NV RAM 地址等于 STEMP[10:0]/4 (限制在-64 至+63)。关于利用 STEMP[10:0]读数计算温度值(以°C
为单位)的公式,请参见第 56 页的第 2.5.5 节:71M654x 温度传感器。
该温度公式用于计算表 44 中的两个温度列(第二列和最右侧一列)。第二列使用 STEMP[10:0]的全部 11 位,
最右侧一列则由经过限制器之后的数据(6+S)值与 4 相乘得到。由于每个查找表地址步长对应于 4 x
0.325°C 温度步长,所以乘以 4 后,将限制器之后的 6+S 值加 2,计算出最右侧一列的数值。该方法确保
补偿数据以最小量化误差加载至查找表。表 44 列出了与图 17 每一节点对应的数值。表中未列出超出-256
至+255 范围的 STEMP[10:0]值。限制器输出被限制在-64 至+63 范围,它直接就是 128 字节查找表的相应
地址。最右侧一列给出对应于 128 字节补偿表中每个地址单元的标称温度。
表 44. NV RAM 温度表结构
54
STEMP[10:0]
(10+S)
(十进制)
温度( C)
(公式)
-256
-61.71
-255
-61.39
-254
-61.06
-253
…
-4
-60.73
…
20.69
-3
21.02
-2
21.35
o
-1
21.67
0
22.00
1
22.33
2
22.65
3
22.98
4
23.31
5
23.64
6
23.96
7
…
252
24.29
…
104.40
253
104.73
254
105.06
255
105.39
STEMP[10:0]>>2
(8+S)
(十进制)
限制器输出
(6+S)
(十进制)
温度( C)
(查找表)
-64
-64
-61.06
…
…
…
-1
-1
21.35
0
0
22.65
1
1
23.96
…
…
…
63
63
105.06
o
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
为正确工作,MPU 必须将反映晶体温度特性的数值加载至查找表,通常在初始化期间完成。由于不能直接
寻址查找表,MPU 需采用以下步骤加载整个 NV RAM 表:
1.
2.
3.
4.
5.
6.
将 LKPAUTOI 位(I/O RAM 0x2887[7])置位,使能地址自动递增。
向 I/O RAM 寄存器 LKPADDR[6:0] (I/O RAM 0x2887[6:0])写 0。
将 8 位数据写至 I/O RAM 寄存器 LKPDAT (I/O RAM 0x2888)。
将 LKP_WR 位(I/O RAM 0x2889[0])置位,将 8 位数据写至 NV_RAM。
等待 LKP_WR 清零(LKP_WR 在数据复制到 NV RAM 后自动清零)。
重复第 3 步至第 5 步,直到将全部数据写至 NV RAM。
NV RAM 亦可通过将 1 写入 LKP_RD 位(I/O RAM 0x2889[1])读取。通过置位 LKPAUTOI 位(I/O RAM
0x2887[7]),可加快读/写 NV RAM 的过程。LKPAUTOI 置位时,LKPADDR[6:0]在 LKP_RD 或 LKP_WR 每
次触发后自动递增。通过写 0 至 LKPAUTOI 位,并将相应地址加载至 LKPADDR[6:0],可随机存取 NV
RAM。
如果未使用振荡器的温度补偿功能,可将 NV RAM 存储区域作为普通 NV 存储空间,利用以上介
绍的步骤读/写 NV RAM 数据。这种情况下,保持 OSC_COMP 位(I/O RAM 0x28A0[5])为 0,即禁
用自动振荡器温度补偿特性。
2.5.4.5 RTC中断
RTC 每秒和每分钟产生中断。这些中断称为 RTC_1SEC 和 RTC_1MIN。此外,RTC 还具有闹钟功能,分
钟和小时寄存器等于表 45 中定义的相应数值时,产生中断。闹钟中断称为 RTC_T。三种中断均在 MPU 的
外部中断 6。关于这些中断的使能位和标识,请参见中断部分的表 33。
分钟和小时的目标寄存器列在表 45 中。
表 45. 用于 RTC 中断的 I/O RAM 寄存器
名称
RTC_TMIN[5:0]
RTC_THR[4:0]
Rev 2
位置
289E[5:0]
289F[4:0]
复位 唤醒 方向 说明
0
0
0
0
R/W 目标分钟寄存器,参见下文的 RTC_THR[4:0]。
R/W 目 标 小 时 寄 存 器 。 RTC_T 中 断 , RTC_MIN 等 于
RTC_TMIN 且 RTC_HR 等于 RTC_THR 时,发生 RTC_T
中断。
55
71M6541D/F/G 和 71M6542F/G 数据资料
2.5.5
71M654x温度传感器
71M654x 具有片上温度传感器,用于确定其带隙基准的温度。温度数据的主要用途是对计量(电流、电压和
能量)及 RTC 进行温漂补偿。请参见第 97 页第 4.7 节计量温度补偿,另请参考第 53 页第 2.5.4.4 节 RTC
温度补偿。
与前几代 Teridian SoC 不同,71M654x 不与计量部分共用 ADC 转换温度,而是采用一片低功耗 ADC,支
持 SLP、LCD 模式,以及 BRN 和 MSN 模式的测量需求。这意味着即使在 MPU 暂停 LCD/SLP 模式下,
也可以对晶振频率进行温度补偿,参见第 53 页第 2.5.4.4 节 RTC 温度补偿。
MSN 和 BRN 模式下,通过置位 TEMP_START (I/O RAM 0x28B4[6])控制位,利用命令唤醒温度传感器。
MPU 必须等待 TEMP_START 位清零,才能读取 STEMP[10:0]并进行下次测量,置位 TEMP_START。SLP
和 LCD 模式下,以 TEMP_PER[2:0] (I/O RAM 0x28A0[2:0])设定的间隔定期唤醒。
从两个 I/O RAM 地址 STEMP[10:3] (I/O RAM 0x2881)和 STEMP[2:0] (I/O RAM 0x2882[7:5])读取温度测量结
果。注意,必须读取这两个 I/O RAM 地址并正确组合,构成 STEMP[10:0]的 11 位数值(见表 46 中的
STEMP)。所得到的 11 位值为 2 的补码,范围从-1024 至+1023 (十进制)。利用以下公式从 11 位
STEMP[10:0]读数计算检测到的温度。
以下公式用于计算检测到的温度。第一个公式适用于 71M654x 工作在 MSN 模式及 TEMP_PWR = 1 的条件
下。第二个公式用于 71M654x 处于 BRN 模式下,这种情况下,TEMP_PWR 和 TEMP_BSEL 位必须设为相
同值,从而检测为温度传感器供电的电池,BSENSE 为电池电压测量值。所以,第二个公式需要读取
STEMP 和 BSENSE。第二个公式中,芯片处于 BRN 模式时,BSENSE (检测到的电池电压)用于获取更准确
的温度读数。
71M654x 处于 MSN 模式时(TEMP_PWR = 1):
Temp(°C ) = 0.325 ⋅ STEMP + 22
71M654x 处于 BRN 模式时(TEMP_PWR = TEMP_BSEL):
Temp (oC ) = 0.325 ⋅ STEMP + 0.00218 ⋅ BSENSE 2 − 0.609 ⋅ BSENSE + 64.4
表 46 列出了用于温度和电池测量的 I/O RAM 寄存器。
如果 TEMP_PWR 选择 VBAT_RTC,并且 VBAT_RTC 引脚的电池电量已经耗尽(电压低于 2.0V),那
么 温 度 测 量 过 程 会 无 法 结 束 ( 即 TEMP_START 位 一 直 为 1) 。 这 种 情 况 下 , 必 须 选 择 V3P3D
(TEMP_PWR = 1)供电方式来实现正常的温度测量。
表 46. 用于温度和电池测量的 I/O RAM 寄存器
名称
TBYTE_BUSY
位置
复位
唤醒
方向
28A0[3]
0
0
R
说明
表示硬件仍然在写 0x28A0 字节;为 1 时,不允许对
该字节进行写操作。写操作持续时间可长达 6ms。
设置两次温度测量之间的时间间隔,任何模式
(MSN、BRN、LCD 或 SLP)下均可使能自动测量。
TEMP_PER
TEMP_PER[2:0]
28A0[2:0]
0
–
R/W
0
1-6
7
TEMP_BAT
56
28A0[4]
0
–
时间
手动更新(见 TEMP_START)
2 ^ (3+TEMP_PER) (秒)
连续
R/W 只要进行温度测量,则测量 VBAT。
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
名称
位置
复位
唤醒
方向
说明
TEMP_START
28B4[6]
0
–
TEMP_PER[2:0]必须清零,使 TEMP_START 生效。
如果 TEMP_PER[2:0] = 0,置位 TEMP_START 开始温
度测量。SLP 和 LCD 模式下忽略。完成温度测量
R/W
时 , 硬 件 清 除 TEMP_START 。 MPU 必 须 等 待
TEMP_START 位清零,才能读取 STEMP[10:0]以及再
次置位 TEMP_START。
TEMP_PWR
28A0[6]
0
–
选择温度传感器电源:
R/W 1 = V3P3D,0 = VBAT_RTC。SLP 和 LCD 模式下忽
略该位,总是由 VBAT_RTC 供电。
TEMP_BSEL
28A0[7]
0
–
R/W
选 择 温 度 传 感 器 监 测 的 电 池 : 1 = VBAT , 0 =
VBAT_RTC。
该位用于监测 VCO 温度。常规工作时,TEMP_TEST
必须为 00。其它任何值都会造成 VCO 以如下控制电
压连续运行。
TEMP_TEST[1:0] 2500[1:0]
0
–
STEMP[10:3]
STEMP[2:0]
2881[7:0]
2882[7:5]
BSENSE[7:0]
2885[7:0]
–
–
2704[3]
0
0
BCURR
R/W
TEMP_TEST
功能
00
正常工作
01
保留,用于工厂测试
1X
保留,用于工厂测试
R
R
温度测量结果。为了正确形成 STEMP[10:0],MPU
必须读取 0x2881[7:0],将其左移 3 位(LSB 补零),然
后读取 0x2882[7:5],将其右移 5 位(5 个 MSB 补
零),然后将两个数进行逻辑或。
R
电池测量结果。
R/W 将 100μA 负载连接至 TEMP_BSEL 所选电池。
关于读取 71M6x01 器件中温度传感器的信息,请参见 71M6xxx 数据资料。
2.5.6
71M654x电池监测器
71M654x 温度测量电路还可监测 VBAT 和 VBAT_RTC 处的电池。被测电池(即 VBAT 或 VBAT_RTC 引脚)
由 TEMP_BSEL (I/O RAM 0x28A0[7])选择。
TEMP_BAT (I/O RAM 0x28A0[4])置位时,测量电池作为每次温度测量的一部分。电池读数储存在寄存器
BSENSE[7:0] (I/O RAM 0x2885)。以下公式用于从 BSENSE[7:0] 和 STEMP[10:0]计算在 VBAT 引脚(或
VBAT_RTC 引脚)上测得的电压。下式结果以伏特为单位:
VBAT (orVBAT _ RTC ) = 3.293V + ( BSENSE[7 : 0] − 142) ⋅ 0.0246V + STEMP[10 : 0] ⋅ 0.000276V
MSN 模式下,可通过置位 BCURR (I/O RAM 0x2704[3])位将 100μA 负载加至所选电池(即 TEMP_BSEL 位选
定的电池)。通过在有或没有 BCURR 的情况下测量电池,可测得电池阻抗。BRN、LCD 和 SLP 模式下,无
论 BCURR 是否置位,均不施加电池负载。
关于读取 71M6x01 器件中 VCC 检测器的信息,请参见 71M6xxx 数据资料。
Rev 2
57
71M6541D/F/G 和 71M6542F/G 数据资料
2.5.7
UART和光接口
71M6541D/F/G 和 71M6542F/G 提供两个异步接口:UART0 和 UART1。两个接口均可用于连接至 AMR
模块、用户接口等。
参见图 19,UART1 包括实现 IR/光接口。引脚 OPT_TX 设计可直接驱动外部 LED,用于通过光链路发送
数据。引脚 OPT_RX 与 RX 引脚的门限相同,但是亦可用于检测来自光链路接收器的外部光电探测器输入,
OPT_TX 和 OPT_RX 连接至专用 UART 端口(UART1)。
OPT_TX 和 OPT_RX 引脚可分别通过配置 OPT_TXINV (I/O RAM 0x2456[0])和 OPT_RXINV (I/O RAM
0x2457[1])翻转。此外,OPT_TX 输出支持 38K 调制,调制可用于 MSN 和 BRN 模式(见表 67)。
OPT_TXMOD 位(I/O RAM 0x2456[1])使能调制。占空比由 OPT_FDC[1:0] (I/O RAM 0x2457[5:4])控制,可选
择 50%、25%、12.5%和 6.25%占空比。6.25%占空比意味着 OPT_TX 在 6.25%周期内为低电平。T
无需 UART1 时,可选择将 OPT_TX 配置为 SEGDIO51。通过 OPT_TXE[1:0] (I/O RAM 0x2456[3:2])字段和
LCD_MAP[51] (I/O RAM 0x2405[0])配置。OPT_TXE[1:0]字段允许 MPU 选择将 VPULSE、WPULSE、
SEGDIO51 或脉冲调制器通过 OPT_TX 引脚输出。同样,亦可选择将 OPT_RX 引脚配置为 SEGDIO55,
其控制位为 OPT_RXDIS (I/O RAM 0x2457[2])和 LCD_MAP[55] (I/O RAM 0x2405[4]) 。
from
OPT_TX UART
OPT_TXINV
VARPULSE
Internal
3
WPULSE
2
DIO2
1
MOD
A
B
0
EN DUTY
OPT_TXE[1:0]
OPT_TXMOD
OPT_FDC
2
V3P3
OPT_TX
OPT_TXMOD = 1,
OPT_FDC = 2 (25%)
OPT_TXMOD = 0
A
A
B
B
1/38kHz
图 18. 光接口
DIO 模拟光 UART (第 3 个 UART)
如图 19 所示,71M654x 还可将 DIO5 设置成光驱动 UART。控制位 OPT_BB (I/O RAM 0x2022[0])置位时,
光端口由 DIO5 驱动,而原有 SEGDIO5 引脚由 UART1_TX 驱动。这种配置通常用于高速串口多于 2 个的
应用,且允许光 UART 速率较慢的设计。
58
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
Internal
SEG55
DIO55
1
1
OPT_RXDIS
UART1_TX
0
DIO5
1
EN
OPT_TXMOD
OPT_FDC
OPT_TXINV
LCD_MAP[55]
SEG51
VARPULSE
3
2
DIO51
B
0
DUTY
V3P3
SEGDIO51/
OPT_TX
1
WPULSE
MOD
A
0
SEGDIO55/
OPT_RX
0
0
UART1_RX
0
LCD_MAP[51]
1
OPT_TXE[1:0]
SEG5
2
1
0
SEGDIO5/TX2
1
LCD_MAP[5]
OPT_BB
OPT_TXMOD=1,
OPT_FDC=2 (25%)
OPT_TXMOD=0
A
B
1/38kHz
图 19. 光接口(UART1)
2.5.8
数字I/O和LCD段驱动器
2.5.8.1 通用信息
71M6541D/F/G 和 71M6542F/G 大多数引脚支持 DIO/LCD 功能复用。每个 SEG/DIO 引脚可配置为 DIO 引
脚或段(SEG)驱动器引脚。
复位或上电时,所有 DIO 引脚为 DIO 输入(SEGDIO0-15 除外,参见下面的注意事项),只有在 MPU 控制
下进行相应配置才可用于其它功能。引脚功能可由 I/O RAM 寄存器 LCD_MAPn (0x2405 – 0x240B)配置。将
LCD_MAPn 中与引脚对应的位置 1,即可将引脚配置为 LCD;将 LCD_MAPn 置 0,将其配置为 DIO。
复位或上电后,引脚 SEGDIO0 至 SEGDIO15 初始为 DIO 输出,但由 PORT_E = 0 (I/O RAM
0x270C[5])禁用,以避免复位期间脉冲引脚误动作。配置引脚 SEGDIO0 至 SEGDIO15 后,MPU
必须通过置位 PORT_E 使能这些引脚。
一旦引脚配置为 DIO,即可独立配置为输入或输出。对于 SEGDIO0 至 SEGDIO15,通过 SFR 寄存器 P0
(SFR 0x80)、P1 (SFR 0x90)、P2 (SFR 0xA0)和 P3 (SFR 0xB0) 实现,如表 48 (71M6541D/F/G)和表 52
(71M6542F/G)所示。
PB 引脚为专用数字输入,不属于 SEGDIO 系统。
CE 具有脉冲计数寄存器,每个脉冲计数器的中断输出在内部连接到脉冲中断逻辑。因此,产生脉
冲中断不需要将脉冲信号连接到外部引脚,参见图 16 中的 No. 2 中断源。
I/O RAM 寄 存 器 DIO_Rn (I/O RAM 0x2009[2:0] 至 0x200E[6:4]) , 用 于 独 立 配 置 引 脚 SEGDIO2 至
SEGDIO11 (配置为 DIO 时)和 PB 的内部信号源。例如:中断或定时器控制(DIO_RPB[2:0] , I/O RAM
0x2450[2:0],配置 PB 引脚)。这种方式下,即使 DIO 引脚配置为输出,亦可跟踪。表 47 列出了可利用
DIO_R2[2:0]至 DIO_R11[2:0]和 DIO_RPB[2:0]分配的内部信号源。如果多个输入连接至同一源,它们之间
与信号源的触发是逻辑或的关系。
表 47. 通过 DIO_Rn[2:0]位的能够选择的资源
DIO_Rn[2:0]数值
Rev 2
选择用于 SEGDIOn 或 PB 引脚的资源
0
无
1
保留
2
T0 (计数器 0 时钟)
3
T1 (计数器 1 时钟)
59
71M6541D/F/G 和 71M6542F/G 数据资料
选择用于 SEGDIOn 或 PB 引脚的资源
DIO_Rn[2:0]数值
4
高优先级 I/O 中断(INT0)
5
低优先级 I/O 中断(INT1)
注:
资 源 只 有 SEGDIO2 至 SEGDIO11 和 PB 引 脚 可 选 , 参 见 表 48
(71M6541D/F/G)和表 52 (71M6542F/G)。
驱动 LED、继电器线圈等时,DIO 引脚应该灌入电流至 GNDD (如图 20 中右侧所示),不是从
V3P3D 源出电流(如图 20 中左侧所示)。这是由于将 V3P3D 连接至 V3P3SYS 或 VBAT 的内部
开关电阻造成的,参见第 143 页第 6.4.6 节 V3P3D 开关。
必须避免在专用于唤醒功能的DIO引脚上灌入或输出电流,例如利用上拉或下拉电阻。违反这一
规则将造成休眠或LCD模式下静态电流增大。
V3P3SYS
MISSION
LCD/SLEEP
BROWNOUT
MISSION
LCD/SLEEP
BROWNOUT
VBAT
V3P3D
HIGH
HIGH-Z
LOW
DIO
VBAT
V3P3D
HIGH
HIGH-Z
LOW
DIO
GNDD
GNDD
Not recommended
V3P3SYS
Recommended
图 20. 连接外部负载至 DIO 引脚
60
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
2.5.8.2 用于 71M6541D/F/G的数字I/O
71M6541D/F/G 总共有 37 个 SEG 复用引脚。这些引脚可分类如下:
17 个 SEG/DIO 复用引脚:
o
o
o
o
SEGDIO4…SEGDIO5 (2 个引脚)
SEGDIO9…SEGDIO14 (6 个引脚)
SEGDIO19…SEGDIO25 (7 个引脚)
SEGDIO44…SEGDIO45 (2 个引脚)
15 个与其它功能共用的 SEG/DIO 复用引脚:
o
o
o
o
o
o
o
SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 个引脚)
SEGDIO2/SDCK, SEGDIO3/SDATA (2 个引脚)
SEGDIO6/XPULSE, SEGDIO7/YPULSE (2 个引脚)
SEGDIO8/DI (1 个引脚)
SEGDIO26/COM5, SEGDIO27/COM4 (2 个引脚)
SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 个引脚)
SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 个引脚)
5 个与其它功能共用的 SEG 段复用引脚:
o
o
ICE 接口引脚:SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E_RST (3 个引脚)
测试端口引脚:SEG46/TMUX2OUT, SEG47/TMUXOUT (2 个引脚)
有 4 个专用的 COM 输出(COM0 至 COM3),加上 2 个被列在共用组合 SEG/DIO 引脚下的 COM 输出
(SEGDIO26/COM5、SEGDIO27/COM4)。
因此,在没有引脚被作为 DIO 的配置中,可有多达 37 个 LCD 段引脚加 4 个 COM,或者 35 个 LCD 段引
脚加 6 个 COM。在不使用 LCD 段引脚的配置中,可有多达 32 个 DIO 引脚。
SEGDIO19 至 SEGDIO27 的配置如表 49 所示,引脚 SEGDIO36-39 和 SEGDIO44-45 的配置如表 50 所示。
SEG46 至 SEG50 不可配置为 DIO。引脚 SEGDIO51 和 SEGDIO55 的配置如表 51 所示。
表 48. SEGDIO0 至 SEGDIO14 数据/方向寄存器(71M6541D/F/G)
SEGDIO
引脚#
配置:
0 = DIO, 1 = LCD
SEG 数据寄存器
DIO 数据寄存器
方向寄存器:
0 = 输入, 1 = 输出
内部资源可配置
(见表 47)
Rev 2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
–
1
2
3
4
5
6
7
LCD_MAP[7:0] (I/O RAM 0x240B)
0
0
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
–
LCD_MAP[14:8] (I/O RAM 0x240A)
9
10
11
12
13
14
–
LCD_SEG0[5:0]至 LCD_SEG14[5:0] (I/O RAM 0x2410[5:0]至 0x241E[5:0]
0
4
1
2
3
P0 (SFR 0x80)
5
6
7
0
4
P0 (SFR 0x80)
–
–
Y
1
2
3
P1 (SFR 0x90)
5
6
7
0
4
P1 (SFR 0x90)
Y
Y
Y
Y
1
2
3
P2 (SFR 0xA0)
5
6
7
0
4
P2 (SFR 0xA0)
Y
Y
Y
Y
1
2
–
P3 (SFR 0xB0)
5
6
–
P3 (SFR 0xB0)
Y
–
–
–
–
61
71M6541D/F/G 和 71M6542F/G 数据资料
表 49. SEGDIO19 至 SEGDIO27 数据/方向寄存器(71M6541D/F/G)
SEGDIO
–
–
–
19
20
21
22
23
24
25
26
27
–
–
–
–
引脚#
–
–
–
16
15
14
13
12
11
10
9
8
–
–
–
–
3
4
5
6
7
0
1
2
3
–
–
–
–
–
–
LCD_MAP[23:19] (I/O RAM 0x2409)
LCD_MAP[27:24] (I/O RAM 0x2408)
–
–
– 19 20 21 22 23 24 25 26 27 –
–
–
–
LCD_SEGDIO19[5:0]至 LCD_SEGDIO27[5:0]
(I/O RAM 0x2423[5:0]至 0x242C[5:0])
–
–
– 19 20 21 22 23 24 25 26 27 –
–
–
–
LCD_SEGDIO19[0] 至 LCD_SEGDIO27[0]
(I/O RAM 0x2423[0]至 0x242C[0])
–
–
– 19 20 21 22 23 24 25 26 27 –
–
–
–
LCD_SEGDIO19[1]至 LCD_SEGDIO27[1]
(I/O RAM 0x2423[1]至 0x242C[1])
–
配置:
0 = DIO, 1 = LCD
SEG 数据寄存器
DIO 数据寄存器
方向寄存器:
0 = 输入, 1 = 输出
表 50. SEGDIO36-39 至 SEGDIO44-45 数据/方向寄存器(71M6541D/F/G)
SEGDIO
–
–
–
–
36
37
38
39
–
–
–
–
44
45
引脚#
–
–
–
–
3
2
1
64
–
–
–
–
63
62
–
–
5
–
–
–
–
–
–
–
–
4
5
6
7
–
–
–
–
4
LCD_MAP[39:36]
LCD_MAP[45:44]
(I/O RAM 0x2407)
(I/O RAM 0x2406)
–
–
36 37 38 39
–
–
–
–
44
LCD_SEGDIO36[5:0]至 LCD_SEGDIO45[5:0]
(I/O RAM 0x2434-2437[5:0]至 0x243C-243D[5:0])
–
–
36 37 38 39
–
–
–
–
44
LCD_SEGDIO32[0]至 LCD_SEGDIO45[0]
(I/O RAM 0x2434-2437[0]至 0x243C-243D[0])
–
–
36 37 38 39
–
–
–
–
44
LCD_SEGDIO32[1]至 LCD_SEGDIO45[1]
(I/O RAM 0x2434-2437[1]至 0x243C-243D[1])
配置:
0 = DIO, 1 = LCD
SEG 数据寄存器
DIO 数据寄存器
方向寄存器:
0 = 输入, 1 = 输出
45
45
45
表 51. SEGDIO51 和 SEGDIO55 数据/方向寄存器(71M6541D/F/G)
SEGDIO
51
–
–
–
55
–
–
–
引脚#
33
–
–
–
32
–
–
–
配置:
0 = DIO, 1 = LCD
SEG 数据寄存器
3
7
–
–
–
–
–
–
LCD_MAP[55], LDC_MAP[51]
(I/O RAM 0x2405)
51
55
–
–
–
–
–
–
LCD_SEGDIO51[5:0], LCD_SEGDIO55[5:0]
(I/O RAM 0x2443[5:0]和 0x2447[5:0])
51
DIO 数据寄存器
方向寄存器:
0 = 输入, 1 = 输出
62
–
–
–
55
–
–
–
LCD_SEGDIO51[0]至 LCD_SEGDIO55[0]
(I/O RAM 0x2443[0]和 0x2447[0])
51
–
–
–
55
–
–
–
LCD_SEGDIO51[1]至 LCD_SEGDIO55[1]
(I/O RAM 0x2443[1]和 0x2447[1])
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
2.5.8.3 用于 71M6542F/G的数字I/O
71M6542F/G 总共有 55 个 SEG 复用引脚可用。这些引脚可分类如下:
35 个 SEG/DIO 复用引脚:
o SEGDIO4…SEGDIO5 (2 个引脚)
o SEGDIO9…SEGDIO25 (17 个引脚)
o SEGDIO28…SEGDIO35 (8 个引脚)
o SEGDIO40…SEGDIO45 (6 个引脚)
o SEGDIO52…SEGDIO53 (2 个引脚)
15 个与其它功能共用的 SEG/DIO 复用引脚:
o
o
o
o
o
o
o
SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 个引脚)
SEGDIO2/SDCK, SEGDIO3/SDATA (2 个引脚)
SEGDIO6/XPULSE, SEGDIO7/YPULSE (2 个引脚)
SEGDIO8/DI (1 个引脚)
SEGDIO26/COM5, SEGDIO27/COM4 (2 个引脚)
SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 个引脚)
SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 个引脚)
5 个与其它功能共用的 SEG 段复用引脚:
o
o
ICE 接口引脚:SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E_RST (3 个引脚)
测试端口引脚:SEG46/TMUX2OUT, SEG47/TMUXOUT (2 个引脚)
有 4 个专用 COM (COM0 至 COM3),加上 2 个列在复用 SEG/DIO 引脚的 COM(SEGDIO26/COM5、
SEGDIO27/COM4)。
因此,在没有引脚作为 DIO 的配置中,可提供多达 55 个 LCD 段控制引脚和 4 个 COM,或者 53 个 LCD
段控制引脚和 6 个 COM。在不使用 LCD 段控制引脚的配置中,可提供多达 50 个 DIO 引脚。
例:通过写 0 至 LCD_MAP[15:8]的第 4 位,写 1 至 P3[4] 和 P3[0],将 SEGDIO12 (见表 52 中的引脚 32)
配置为 DIO 输出,为 1 (高电平)。通过写 1 至 LCD_MAP[15:8]的第 4 位,将相同引脚配置为 LCD 驱动器。
显示信息被写入至 LCD_SEG12 的第 0 至第 5 位。
SEGDIO16 至 SEGDIO31 配置如表 53 所示,引脚 SEGDIO32 至 SEGDIO45 配置如表 54 所示。SEG46
至 SEG50 不可配置为 DIO 引脚。引脚 SEGDIO51 至 SEGDIO55 的配置如表 55 所示。
表 52. SEGDIO0 至 SEGDIO15 数据/方向寄存器(71M6542F/G)
SEGDIO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
引脚#
45
44
43
42
41
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
LCD_MAP[7:0] (I/O RAM 0x240B)
0
配置:
0 = DIO, 1 = LCD
SEG 数据寄存器
DIO 数据寄存器
方向寄存器:
0 = 输入, 1 = 输出
内部资源可配置
(见表 47)
Rev 2
0
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
LCD_MAP[15:8] (I/O RAM 0x240A)
9
10
11
12
13
14
15
LCD_SEG0[5:0]至 LCD_SEG15[5:0] (I/O RAM 0x2410[5:0]至 0x241F[5:0]
0
1
2
3
P0 (SFR 0x80)
0
1
2
3
P1 (SFR 0x90)
0
1
2
3
P2 (SFR 0xA0)
0
1
2
3
P3 (SFR 0xB0)
4
5
6
7
P0 (SFR 0x80)
4
5
6
7
P1 (SFR 0x0)
4
5
6
7
P2 (SFR 0xA0)
4
5
6
7
P3 (SFR 0xB0)
–
–
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
–
–
–
–
63
71M6541D/F/G 和 71M6542F/G 数据资料
表 53. SEGDIO16 至 SEGDIO31 数据/方向寄存器(71M6542F/G)
SEGDIO
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
引脚#
28
27
25
24
23
22
21
20
19
18
17
16
11
10
9
8
配置:
0 = DIO, 1 = LCD
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LCD_MAP[23:16] (I/O RAM 0x2409)
LCD_MAP[31:24] (I/O RAM 0x2408)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LCD_SEGDIO16[5:0]至 LCD_SEGDIO31[5:0]
(I/O RAM 0x2420[5:0] to 0x242F[5:0])
SEG 数据寄存器
16
17
18
19
27
28
29
30
31
18
LCD_SEGDIO16[0]至 LCD_SEGDIO31[0]
(I/O RAM 0x2420[0] to 0x242F[0])
19 20 21 22 23 24 25 26 27
LCD_SEGDIO16[1]至 LCD_SEGDIO31[1]
(I/O RAM 0x2420[1] to 0x242F[1])
28
29
30
31
DIO 数据寄存器
方向寄存器:
0 = 输入, 1 = 输出
16
17
20
21
22
23
24
25
26
表 54. SEGDIO32 至 SEGDIO45 数据/方向寄存器(71M6542F/G)
SEGDIO
32
33
34
35
36
37
38
39
40
41
42
43
44
45
引脚#
7
6
5
4
3
2
1
100
99
98
97
96
95
94
0
1
5
32
33
32
33
32
33
2
3
4
5
6
7
0
1
2
3
4
LCD_MAP[39:32]
LCD_MAP[45:40]
(I/O RAM 0x2407)
(I/O RAM 0x2406[5:0])
34 35 36 37 38 39 40 41 42 43 44
LCD_SEGDIO32[5:0]至 LCD_SEGDIO45[5:0]
(I/O RAM 0x2430[5:0]至 0x243D[5:0])
34 35 36 37 38 39 40 41 42 43 44
LCD_SEGDIO32[0]至 LCD_SEGDIO45[0]
(I/O RAM 0x2430[0]至 0x243D[0])
34 35 36 37 38 39 40 41 42 43 44
LCD_SEGDIO32[1]至 LCD_SEGDIO45[1]
(I/O RAM 0x2430[1]至 0x243D[1])
配置:
0 = DIO, 1 = LCD
SEG 数据寄存器
DIO 数据寄存器
方向寄存器:
0 = 输入, 1 = 输出
45
45
45
表 55. SEGDIO51 至 SEGDIO55 数据/方向寄存器(71M6542F/G)
SEGDIO
51
52
53
54
55
–
–
–
引脚#
53
52
51
47
46
–
–
–
0
1
配置:
0 = DIO, 1 = LCD
SEG 数据寄存器
DIO 数据寄存器
方向寄存器:
0 = 输入, 1 = 输出
64
2
3
4
–
–
–
LCD_MAP[55:51]
(I/O RAM 0x2405[7:3])
51 52 53 54 55
–
–
–
LCD_SEGDIO51[5:0]至 LCD_SEGDIO55[5:0]
(I/O RAM 0x2443[5:0]至 0x2447[5:0])
51 52 53 54 55
–
–
–
LCD_SEGDIO51[0]至 LCD_SEGDIO55[0]
(I/O RAM 0x2443[0]至 0x2447[0])
51 52 53 54 55
–
–
–
LCD_SEGDIO51[1]至 LCD_SEGDIO55[1]
(I/O RAM 0x2443[1]至 0x2447[1])
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
2.5.8.4 LCD驱动器
LCD 驱动器由多达 6 个 COM (COM0 至 COM5)和多达 56 个段驱动组成。LCD 接口非常灵活,可驱动 7
段数字、14 段数字或指示符号。
倍压电路和对比度调节 DAC 从 VBAT 或 V3P3SYS 产生 VLCD 电压,电压值取决于 V3P3SYS 电压。倍压
电路可驱动 500Ω 负载,所产生的最大电压比两倍供电电压低 1V,用于 LCD 供电。倍压电路和 DAC 采用
经过微调的低功耗基准供电。
产生 VLCD 的配置由 I/O RAM 字段 LCD_VMODE[1:0] (I/O RAM 0x2401[7:6])控制,解码为 LCD_EXT、
LDAC_E 和 LCD_BSTE 内部信号。表 56 中列出了详细的 LCD_VMODE[1:0]配置。
表 56. LCD_VMODE[1:0]配置
LCD_VMODE [1:0] LCD_EXT LDAC_E LCD_BSTE
11
1
0
0
10
0
1
1
01
0
1
0
00
0
0
0
说明
连接至 VLCD 引脚的外部 VLCD。
V3P3L 的定义请参见下方注释 2。
使能 LCD 升压,最大 VLCD 引脚电压为 2*V3P3L1。
一般而言,VLCD 引脚电压如下:
VLCD = max(2*V3P3L-1, 2.5(1+LCD_DAC[4:0]/31)
禁用 LCD 升压时,最大 VLCD 电压为 V3P3L。
VLCD = max(V3P3L, 2.5V+2.5*LCD_DAC[4:0]/31)
VLCD=V3P3L,禁用 LCD DAC 和 LCD 升压。
LCD 模式下,该设置获得最小电池电流。
注:
1. LCD_EXT、LDAC_E 和 LCD_BSTE 为 71M654x 内部信号,解码自 LCD_VMODE[1:0]控制字
段设置(I/O RAM 0x2401[7:6])。这些解码信号有效时,具有以上说明栏的影响,总结如下:
LCD_EXT:置位时,VLCD 引脚接收外部供电电压
LDAC_E:置位时,使能 LCD DAC
LCD_BSTE:置位时,使能 LCD 升压电路
2. V3P3L 为内部电源,源自 VBAT 引脚或 V3P3SYS 引脚供电,取决于 V3P3SYS 引脚电压。
V3P3SYS 引脚下降至低于 3.0 VDC 时,71M654x 切换至 BRN 模式,V3P3L 从 VBAT 引脚供
电;否则,MSN 模式下,V3P3L 从 V3P3SYS 引脚供电。
使用 VLCD 升压电路时,须谨慎设置 LCD_DAC[4:0] (I/O RAM 0x240D[4:0])数值,确保不超过
LCD 制造商推荐的工作电压指标。
倍压电路在所有 LCD 模式下均有效,包括 LCD_BSTE = 1 时的 LCD 模式。如果禁用升压电路,LCD 系统
直接工作于 VBAT,可降低 LCD 模式下的耗流。
LCD DAC 使用低功耗基准供电,在 VBAT 和倍压限制之内,产生的 VLCD 电压为 2.5 VDC + 2.5 *
LCD_DAC[4:0]/31。
LCD_BAT 位(I/O RAM 0x2402[7])可以设定 LCD 系统在任何功耗模式下均使用电池供电(这样会在 V3P3SYS
具有供电电压时,仍然消耗电池电压)。
如果 LCD_EXT = 1,液晶驱动电源由 VLCD 引脚供给。这种情况下,LCD DAC 功能无效。
LCD 系统的每个 SEG 引脚可驱动多达 6 段。如果显示器支持 6COM,那么设定 6COM 驱动模式可以大大
减少所需的 SEG 引脚数,进而增加 DIO 引脚可用数量。关于不同 LCD 驱动模式选择的信息,请参见
LCD_MODE[2:0]字段(I/O RAM 0x2400[6:4])设置(表 57)。如果选择 5COM 模式,SEGDIO27 则转换为
COM4。如果选择 6COM 模式,SEGDIO26 转换为 COM5。这种转换优先于 SEGDIO26 和 SEGDIO27 的
SEG/DIO 映射。此外,与 LCD_MODE[2:0]无关,如果 LCD_ALLCOM = 1,在 SEGDIO26 和 SEGDIO27
的 LCD_MAP[ ]置位时,它们则变为 COM4 和 COM5。
Rev 2
65
71M6541D/F/G 和 71M6542F/G 数据资料
LCD_ON (I/O RAM 0x240C[0])和 LCD_BLANK (I/O RAM 0x240C[1])位是控制 LCD 显示全灭或全亮的便捷方
式。任何一位都不影响 LCDSEG_DIO[ ]寄存器中储存的 LCD 数据内容。而 LCD_RST (I/O RAM 0x240C[2])
则可将全部 LCD 数据清 0。LCD_RST 仅影响配置为 LCD 的引脚。
将 LCD 频率设置在能够在所需温度范围内提供满意的 LCD 视觉效果的最低值,能够一定程度降低
功耗。
66
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
表 57 列出了控制 LCD 接口工作的全部 I/O RAM 寄存器。
表 57. LCD 配置
名称
位置
复位 唤醒 方向 说明
LCD_ALLCOM
2400[3]
0
–
R/W
LCD_BAT
2402[7]
0
–
R/W
LCD_E
2400[7]
0
–
R/W
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
R/W
R/W
LCD_RST
240C[2]
0
–
R/W
LCD_DAC[4:0]
240D[4:0]
0
–
R/W
LCD_CLK[1:0]
2400[1:0]
0
–
R/W
LCD_MODE[2:0] 2400[6:4]
0
–
R/W
将 全 部 6 个 SEG/COM 引 脚 配置为 COM 。不 影 响
LCD_MAP 为 0 的引脚。
在所有模式下将 LCD 电源连接至 VBAT。
使能 LCD 显示。禁用时,VLC2、VLC1 和 VLC0 接地
(如果其 LCD_MAP 位为 1),类似于 COM 和 SEG 输
出。
LCD_ON = 1 打开全部 LCD 段,不影响 LCD 数据。类
似地,LCD_BLANK= 1 关闭全部 LCD 段,不影响 LCD
数据。如果两位均置位,则打开所有 LCD 段。
清零所有 LCD 数据位。这些位影响被配置为 LCD 驱动
器的 SEGDIO 引脚。
该寄存器控制 LCD 对比度 DAC,调节 VLCD 电压,输
出范围为 2.5 VDC 至 5 VDC。VLCD 电压为:
VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31
所以,DAC 的 LSB 为 80.6mV。最大 DAC 输出电压受
限于 V3P3SYS、VBAT,以及 LCD_BSTE 是否置位。
设置 LCD 时钟频率(1/T),参见图 21 关于 T 的定义。.
注意:fw = 32768 Hz
00-fw/2^9, 01-fw/2^8, 10-fw/2^7, 11-fw/2^6
LCD 偏压和复用模式。
LCD_MODE
000
001
010
011
100
101
110
输出
4COM,1/3 偏压
3COM,1/3 偏压
2COM,½偏压
3COM,½偏压
静态显示
5COM,1/3 偏压
6COM,1/3 偏压
该寄存器制定如何产生 VLCD。
LCD_VMODE[1:0] 2401[7:6]
00
00
R/W
LC_VMODE
11
10
01
00
说明
外部 VLCD
使能 LCD 升压和 LCD DAC
使能 LCD DAC
无升压和 DACVLCD = VBAT
或 V3P3SYS
LCD 可驱动为静态、 ½偏压和 1/3 偏压。图 21 定义了 COM 波形。注意,特定模式下不使用的 COM 引脚
保持“段关闭”状态,而非 GND、VCC 或高阻。
段驱动器 SEGDIO22 和 SEGDIO23 可配置为以 0.5Hz 或 1Hz 闪烁。闪烁频率由 LCD_Y (I/O RAM
0x2400[2])控制。连接至这些驱动引脚的段可最多有 6 个。I/O RAM 字段 LCD_BLKMAP22[5:0] (I/O RAM
0x2402[5:0])和 LCD_BLKMAP23[5:0] (I/O RAM 0x2401[5:0])设定哪些像素需要闪烁。LCD_BLKMAP22[5:0]
和 LCD_BLKMAP23[5:0]为非易失。
Rev 2
67
71M6541D/F/G 和 71M6542F/G 数据资料
可利用 LCD_DAC[4:0]字段(I/O RAM 0x240D[4:0])对 LCD 偏压进行温度补偿,偏压在 1.4 V 至 3.3 V (MSN
模式下为 V3P3SYS,BRN 和 LCD 模式下为 VBAT)范围内调节。LCD_DAC[4:0]字段设为 000 时,DAC 被
旁路并关断,用于减小 LCD 模式下的电流。
STATIC (LCD_MODE=100)
1/2 BIAS, 2 STATES (LCD_MODE = 010 )
0
1
COM0
COM0
1/2 BIAS, 3 STATES (LCD_MODE = 011 )
0
1
2
COM0
COM1
COM1
(1/2)
COM1
COM2
(1/2)
COM2
(1/2)
COM2
COM3
(1/2)
COM3
(1/2)
COM3
(1/2)
COM4
(1/2)
COM4
(1/2)
COM4
(1/2)
COM5
(1/2)
COM5
(1/2)
COM5
(1/2)
SEG_ON
SEG_ON
SEG_ON
SEG_OFF
SEG_OFF
SEG_OFF
T
1/3 BIAS, 3 STATES (LCD_MODE = 011 )
0
1
2
COM0
COM1
COM2
(2/3)
(1/3)
1/3 BIAS, 4 STATES (LCD_MODE = 000 )
3
0
1
2
COM0
1/3 BIAS, 6 STATES (LCD_MODE = 110 )
4
5
3
0
1
2
COM0
COM1
COM1
COM2
COM2
COM3
COM3
COM4
COM4
COM4
COM5
COM5
COM5
SEG_ON
SEG_ON
SEG_ON
SEG_OFF
SEG_OFF
SEG_OFF
COM3
图 21. LCD 波形
68
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
LCD驱动器(71M6541D/F/G)
71M6541D/F/G 如果采用 6COM 模式,则最多提供 35 个 SEG 引脚,能够驱动最多 6 x 35 = 210 像素的
LCD 显示。8 段/数字时,这相当于 26 个数字。
LCD 段数据写入 LCD_SEGn[5:0] I/O RAM 寄存器,如第 2.5.8.2 节和第 2.5.8.3 节介绍。
SEG46 至 SEG50 不可配置为 DIO 引脚。这些引脚的显示数据写入 I/O RAM 寄存器 LCD_SEG46[5:0]至
LCD_SEG50[5:0] ( 见 表 58) 。 ICE_E 引 脚 拉 高 时 , 引 脚 E_RXTX/SEG48 、 E_TCLK/SEG49 和
E_RST/SEG50 作为 ICE 接口引脚。反之,使能 SEG 功能。
LCD_MAP[46]和 LCD_MAP[47] (I/O RAM 0x2406[6]和 0x2407[7])必须设为 1,以允许 TMUX2OUT/SEG46
和 TMUXOUT/SEG47 作为 SEG 驱动器工作。如果 LCD_MAP[46]和 LCD_MAP[47]为 0,这些引脚作为
TMU2XOUT 和 TMUXOUT 工作 (见第 78 页第 2.5.12 节测试端口(TMUXOUT 和 TMUX2OUT 引脚))。
表 58. SEG46 至 SEG50 的 71M6541D/F/G LCD 数据寄存器
Rev 2
46
47
48
49
50
引脚#
61
60
38
37
36
LCD_SEG50[5:0]
LCD_SEG49[5:0]
SEG 数据寄存器
LCD_SEG48[5:0]
总为 LCD 引脚,除用于 ICE
接口或
TMUXOUT/TMUX2OUT 时。
LCD_SEG47[5:0]
配置
LCD_SEG46[5:0]
SEG
69
71M6541D/F/G 和 71M6542F/G 数据资料
LCD驱动器(71M6542F/G)
71M6542F/G 如果采用 6COM 模式,则最多提供 56 个 SEG 引脚,能够驱动最多 6 x 56 = 336 像素的
LCD 显示。8 段/数字时,这相当于 42 个数字。
LCD 段数据写入 LCD_SEGn[5:0] I/O RAM 寄存器,如第 2.5.8.3 节用于 71M6542F/G 的数字 I/O 介绍。
SEG46 至 SEG50 不可配置为 DIO 引脚。这些引脚的显示数据写入 I/O RAM 寄存器 LCD_SEG46[5:0] (I/O
RAM 0x243E[5:0])至 LCD_SEG50[5:0] (I/O RAM 0x2442[5:0]),参见表 59。相关引脚作为 ICE 接口引脚,
并且只要 ICE_E 拉高,ICE 功能设置将优先于 SEG 功能。
表 59. SEG46 至 SEG50 的 71M6542F/G LCD 数据寄存器
SEG
46
47
48
49
50
引脚#
93
92
58
57
56
2.5.9
LCD_SEGDIO50[5:0]
LCD_SEGDIO49[5:0]
LCD_SEGDIO48[5:0]
LCD_SEGDIO47[5:0]
SEG 数据寄存器
除 用 于 ICE 接 口 或
TMUXOUT/TMUX2OUT , 则
始终为 LCD 引脚。
LCD_SEGDIO46[5:0]
配置:
EEPROM 接口
71M654x 支持硬件 2 线或 3 线(μ-wire)型 EEPROM 接口。接口使用 SFR EECTRL (SFR 0x9F)和 EEDATA
(SFR 0x9E)寄存器通信。
2.5.9.1 2 线EEPROM接口
71M654x 有两个专用 I2C 接口引脚,此类引脚与外部 EEPROM 器件通信。通过配置 DIO_EEX[1:0] = 01
(I/O RAM 0x2456[7:6])开启 SEGDIO2 (SDCK)和 SEGDIO3 (SDATA)引脚的第二功能(I2C 接口)。MPU 通
过 SFR 寄存器 EEDATA 和 EECTRL 与接口通信。如果 MPU 希望写入 EEPROM 一个字节数据,应将数据
放入 EEDATA,然后写发送命令至 EECTRL。这将触发传送操作,BUSY 位变低时结束。BUSY 变低时,
触发 INT5。MPU 然后可检查 RX_ACK 位,查看 EEPROM 是否应答。
读字节时,写接收命令至 EECTRL,然后等待 BUSY 位变低。完成之后,接收数据位于 EEDATA。串行发送
和接收时钟在每次传输时为 100kHz,然后保持为高电平状态,直到下次传输开始。选择双引脚接口时,
EECTRL 位如表 60 所示。
70
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
表 60. 2 线接口对应的 EECTRL 位
状态位
名称
读/写
复位
状态
极性
说明
7
ERROR
R
0
正
接收到非法命令后为 1。
6
BUSY
R
0
正
串行数据总线忙时为 1。
5
RX_ACK
R
1
正
1 表示 EEPROM 发送了 ACK 位。
4
TX_ACK
R
1
正
1 表示已向 EEPROM 发送 ACK 位。
操作
CMD[3:0]
3:0
CMD[3:0]
W
0000
正
0000
无操作命令。
0010
从 EEPROM 接收一个字节,然后发
送 ACK。
0011
发送一个字节至 EEPROM。
0101
发起一个 STOP 序列。
0110
从 EEPROM 接收最后字节,不发送
ACK。
1001
发起一个 START 序列。
Others
无操作,置位 ERROR 位。
EEPROM 接口也可通过软件直接控制 DIO2 和 DIO3 实现,即软件模拟 I2C 接口。DIO 线的方向可由
输入该位输出,可利用单次写操作写输出值,从而避免冲突(见表 15 端口寄存器(SEGDIO0-15));串
行 SDATA 中防止冲突无需电阻。
2.5.9.2 带有单独数据引脚的 3 线(μ-wire) EEPROM接口
71M654x 提供一个 500kHz 3 线接口,使用 SDATA、SDCK 和 DIO 引脚用于 CS。接口通过 DIO_EEX[1:0]
= 10 选择。选择 3 线接口时,EECTRL 如表 61 所示。写 EECTRL 时,来自 EEDATA 的 8 位数据写入
EEPROM 或从 EEPROM 读取,取决于 EECTRL。
2.5.9.3 带有独立DI/DO引脚的 3 线(μ-wire/SPI) EEPROM接口
如果 DIO_EEX[1:0] = 11,除 DI 和 DO 为独立引脚外,3 线接口同上。这种情况下,SEGDIO3 变为 DO,
SEGDIO8 变为 DI。除了输出数据出现在 DO 引脚以及全部输入数据出现在 DI 之外,时序与 DIO_EEX[1:0]
= 10 时相同。该模式下,DI 忽略,在 DO 接收数据。该模式兼容于 SPI 模式 0、0 和 1、1,数据在时钟下
降沿移出,在时钟上升沿写入。
表 61. 3 线接口对应的 EECTRL 位
控制位
名称
读/写
说明
7
WFR
W
等待就绪。如果该位置位,BUSY 下降沿将被延迟,直到在数据线出现上
升沿。该位可用于写命令的最后字节期间,在 EEPROM 结束其内部写序
列后产生 INT5 中断。如果 Hi-Z=0,该位被忽略。
6
BUSY
R
串行数据总线忙时有效。BUSY 位下降时,产生 INT5 中断。
5
HiZ
W
表示 SD 信号在最后一个 SDCK 上升沿后立即悬空或置为高阻。
4
RD
W
表示 EEDATA (SFR 0x9E)由来自 EEPROM 的数据填充。
W
设定要发送的时钟数量。允许值为 0~8。如果 RD=1,从高到低的顺序读
取 CNT 位数据,并以右对齐存入 EEDATA 寄存器。如果 RD=0,EEDATA
寄存器数据被从高到低的顺序发送 CNT 位数据至 EEPROM 接口。如果
CNT[3:0]为 0,SDATA 将处于 HiZ 状态。
3:0
Rev 2
CNT[3:0]
71
71M6541D/F/G 和 71M6542F/G 数据资料
图 22 至图 26 中的时序图说明了 3 线 EEPROM 接口的操作。写 EECTRL (SFR 0x9F)寄存器时,意味着所
有命令开始执行。首先从连接至 CS 的 DIO 引脚上升沿开始;然后通过 EECTRL 和 EEDATA 发送多于 8 位
或少于 8 位的命令,如图 22 至图 26 所示。
会话结束后,必须将 CS 拉低。在读操作结束时,EEPROM 接口正在驱动 SDATA,但是当 CS 变低时将
转换为 Hi-Z (高阻)。MPU 程序应立即发出一个写命令,CNT=0,HiZ=0,接管控制 SDATA,强制其为低
阻状态。
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- No HiZ
SCLK (output)
SDATA (output)
D7
D6
D5
SDATA output Z
D4
D3
D2
(LoZ)
BUSY (bit)
图 22. 3 线接口:写命令,HiZ=0
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ
SCLK (output)
SDATA (output)
D7
D6
D5
SDATA output Z
D4
D3
D2
(LoZ)
(HiZ)
BUSY (bit)
图 23. 3 线接口:写命令,HiZ=1
EECTRL Byte Written
INT5
CNT Cycles (8 shown)
READ
SCLK (output)
SDATA (input)
SDATA output Z
D7
D6
D5
D4
D3
D2
D1
D0
(HiZ)
BUSY (bit)
图 24. 3 线接口:读命令
72
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
EECTRL Byte Written
Write -- No HiZ
INT5 not issued
CNT Cycles (0 shown)
Write -- HiZ
INT5 not issued
CNT Cycles (0 shown)
SCLK (output)
SCLK (output)
SDATA (output)
EECTRL Byte Written
SDATA (output)
D7
SDATA output Z
SDATA output Z
(LoZ)
(HiZ)
BUSY (bit)
BUSY (bit)
图 25. 3 线接口:写命令,CNT=0
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ and WFR
SCLK (output)
SDATA (out/in)
SDATA output Z
D7
D6
D5
(From 654x)
D4
D3
D2
(LoZ)
BUSY
(From EEPROM)
READY
(HiZ)
BUSY (bit)
图 26. 3 线接口:写命令,HiZ=1,WFR=1
2.5.10 SPI从机端口
SPI 从机接口直接与 MPU 数据总线通信,能够读和写数据 RAM 和 I/O RAM 位置。它还能够发送命令至
MPU。连接从机接口的端口包括:SPI_CSZ、SPI_CKI、SPI_DI 和 SPI_DO 引脚。这些引脚与 DIO/LCD
段驱动器引脚 SEGDIO36 至 SEGDIO39 组合复用。
此外,SPI 接口允许读取 FLASH 并对其编程。为便于 FLASH 编程,芯片需要重新上电或复位一次,使
SPI 引脚复位为默认的 PSI 模式。通过清除 SPI_E 位(I/O RAM 0x270C[4])直接禁用 SPI 端口。
SPI 接口的应用包括:
1) 外部主机从CE地址读取数据,获取表计信息。这可用于71M654x作为智能前端的应用。由于地址为16
位格式,所以可访问任何类型的XRAM数据:CE、MPU、I/O RAM,,但不能访问SFR或80515内部寄
存器组。
2) 可通过SPI接口建立通信链路:通过写MPU存储器,外部主机可启动和控制71M654x MPU的进程。写
CE或MPU通常产生一个中断,用来通知MPU读取和处理外部主机写入的字节功能。亦可在不产生中断
的情况下由外部主机写入数据。
3) 外部 DSP 可访问 ADC 产生的前端数据。这种模式将 71M654x 作为模拟前端(AFE)。
4) 由外部主机对 FLASH 编程(SPI FLASH 模式)。
SPI 传输
典型的 SPI 传输如下。SPI_CSZ 为高电平时,端口保持在初始化/复位状态。该状态期间,SPI_DO 保持在
高阻状态,SPI_CLK 和 SPI_DI 上的所有跳变被忽略。SPI_CSZ 为低电平时,端口在 SPI_CLK 的第一个
上升沿开始传输。如表 62 所示,一次传输包括可选的 16 位地址、8 位命令、8 位状态字节,后边跟一个或
多个字节的数据。SPI_CSZ 为高时,传输结束。有些传输可能仅包含命令。
Rev 2
73
71M6541D/F/G 和 71M6542F/G 数据资料
SPI_CSZ 为高时,非 x000 0000 形式的 SPI 命令字节将更新 SPI_CMD (SFR 0xFD)寄存器,同时触发中断。
通讯为单字节的情况例外。这种情况下,SPI_CMD 字节总是更新并请求中断。SPI_CSZ 为高电平时,不清
除 SPI_CMD。
SPI 端口支持高达 10Mb/s 的数据传输。串行读、写操作需要至少 8 个时钟/字节,进而 SPI 对 RAM 的访问
速度在 1.25MHz 以下,确保 SPI 总是能够访问 DRAM。
表 62. SPI 操作字段
大小
(字节)
字段名称
必需
说明
地址
是,单字节通信
除外
2
16 位地址。如果发送一简单 SPI 命令,则无需地址字段。
命令
是
1
8 位命令。该字节可作为 MPU 的控制命令。多字节通信中,
MSB 为读/写位。除非通信为多字节,且 SPI_CMD 准确为
0x80 或 0x00,SPI_CMD 寄存器更新,并请求 SPI 中断。否
则,SPI_CMD 寄存器保持不变,并且不请求中断。
状态
是,如果通讯包
括数据
1
8 位状态字段,表示之前的通信状态,该字节亦可用于 MPU
存储器映射为 SPI_STAT (I/O RAM 0x2708)寄存器。内容请参
见表 64。
数据
是,如果通讯包
括数据
1 或多
读或写数据。每个新字节的地址自动递增。
每次 SPI 通信输出 SPI_STAT 字节,并指示前一通信的奇偶校验和错误状态。潜在故障源有:
•
•
71M654x 未就绪。
通信未在字节边界结束。
SPI 安全模式
有时候希望防止 SPI 接口对任意 RAM 地址进行写操作,以免干扰 MPU 和 CE 工作,尤其是在 AFE 应用中。
出于这一原因,提供了 SPI 安全模式。SPI 安全模式下,只有地址 0x400 至 0x40F 的 16 个字节 SPI 可进
行写操作。如果 SPI 主机需要写其它地址,可以利用 SPI_CMD 寄存器从 MPU 请求写操作。SPI 安全模式
由 SPI_SAFE 位(I/O RAM 0x270C[3])位使能。
单字节通信
如果为单字节通信,该字节由 71M654x 解析为 SPI_CMD。对于任何命令,单字节通信总是更新 SPI_CMD
寄存器,从而生成 SPI 中断。
多字节通信
如图 27 所示,多字节操作包括 16 位地址字段、8 位 CMD、状态字节和数据字节序列。多字节通信为三或
四字节格式。
74
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
SERIAL READ
16 bit Address
Status Byte
8 bit CMD
DATA[ADDR]
DATA[ADDR+1]
Extended Read . . .
(From Host) SPI_CSZ
0
15
16
A0
C7
23
31
24
32
39
40
D0
D7
47
(From Host) SPI_CK
(From Host) SPI_DI
A15
A14
A1
C6
C5
C0
HI Z
(From 654x) SPI_DO
SERIAL WRITE
x
ST7
16 bit Address
ST6
ST5
ST0
D7
D1
DATA[ADDR]
Status Byte
8 bit CMD
D6
D6
D1
D0
DATA[ADDR+1]
(From Host) SPI_CSZ
Extended Write . . .
0
15
16
A0
C7
23
31
24
32
39
40
D0
D7
47
(From Host) SPI_CK
(From Host) SPI_DI
x
A15
A14
A1
(From 654x) SPI_DO
HI Z
C6
C5
D7
C0
ST7
ST6
ST5
D6
D1
D6
D1
D0
x
ST0
图 27. PI 从机端口—典型的多字节读、写操作
表 63. SPI 命令时序
命令时序
说明
ADDR 1xxx xxxx STATUS
Byte0 ... ByteN
从 ADDR 开始读取数据。ADDR 自动递增,直到 SPI_CSZ 为高;完成
后,SPI_CMD (SFR 0xFD)更新至 1xxx xxxx,产生 SPI 中断。命令字节为
1000 0000 时例外。这种情况下,不产生 MPU 中断,不更新 SPI_CMD。
从 ADDR 开始写数据。ADDR 自动递增,直到 SPI_CSZ 为高;完成后,
SPI_CMD 更新至 0xxx xxxx,产生 SPI 中断。命令字节为 0000 0000 时
例外。这种情况下,不产生 MPU 中断,不更新 SPI_CMD。
0xxx xxxx ADDR Byte0 ...
ByteN
Rev 2
75
71M6541D/F/G 和 71M6542F/G 数据资料
表 64. SPI 寄存器
名称
位置
复位
唤醒
方向
说明
SPI 中断使能位。
2701[7]
0
0
R/W
SFR FD[7:0]
–
–
R
SPI_E
270C[4]
1
1
R/W
SPI 端口使能位,使能引脚 SEGDIO36 至 SEGDIO39
的 SPI 接口。
IE_SPI
SFR F8[7]
0
0
R/W
SPI 中断标识,由硬件置位,通过写 0 清除。
270C[3]
0
0
R/W
SPI 安全模式使能位。置位时,将 SPI 写操作限制在
SPI_CMD 及 DRAM 中的 16 字节区域。
R
SPI_STAT 含有前一 SPI 通讯的状态结果。
第 7 位:就绪错误:71M654x 未准备好按照前一命令
读或写。
第 6 位:读数据奇偶性:该位是前一命令从 71M654x
读取的全部字节的奇偶校验。不包括 SPI_STAT 字节。
第 5 位:写数据奇偶性:该位时前一命令写入至
71M654x 的全部字节的总奇偶校验。它包括 CMD 和
ADDR 字节。
第 4 至 2 位:字节数的最低 3 位。不包括 ADDR 和
CMD 字节。1、2 和 3 字节指令返回 111。
第 1 位:SPIFLASH 模式:TEST 引脚为零时,该位为
零。
第 0 位:SPIFLASH 模式就绪:用于 SPIFLASH 模
式。表示 FLASH 已准备好接收另一条写指令。
EX_SPI
SPI_CMD
SPI_SAFE
SPI_STAT
76
2708[7:0]
0
0
SPI 命令,来自总线主控制器的 8 位命令。
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
SPI FLASH 模式(SFM)
常规模式,SPI 从器件接口不能读或写 FLASH。然而,71M6541D/F/G 和 71M6542F/G 支持 SPI FLASH
模式(SFM),方便 FLASH 的初始编程。SFM 模式下,SPI 接口可擦除、读、写 FLASH。该模式下,不可
访问其它存储器,例如 XRAM 和 I/O RAM。为防止 FLASH 被错误地更改,需要特殊条件和操作才能激活
SFM 模式。
SFM 模式下,支持对 FLASH 的 n 字节读取和双字节写入。关于读、写命令的格式,请参见第 73 页的 SPI
通信说明。由于 FLASH 写操作总是基于双字节字,所以初始地址必须为偶数。在写完奇数字节后,数据更
新至 16 位 FLASH 总线。
SFM 模式下,MPU 完全暂停。由于这一原因,以上 SPI 通信部分介绍的中断特性不适用于 SFM 模式。
71M6541D/F/G 和 71M6542F/G 只有被 WD 定时器或 RESET 引脚复位,才能退出 SFM 模式。
激活 SFM
激活 SFM 之前,必须满足以下条件:
•
•
•
•
•
引脚 ICE_E = 1。禁用看门狗,同时为防止无意篡改 FLASH 增加了另一层保护。
外部电源(V3P3SYS、V3P3A)处于适当电平(> 3.0 VDC)。
PREBOOT = 0 (SFR 0xB2[7]),SECURE (SFR 0xB2[6])功能有效。
SECURE = 0。该 I/O RAM 寄存器指示 SPI 加密模式被禁止。如果 SECURE 位 = 1 (在 SPI 加密模式下
不允许读取 FLASH),操作被限制为 SFM 整体擦除模式。
FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4]) = 0010。
I/O RAM 寄存器 SFMM (I/O RAM 0x2080)和 SFMS (I/O RAM 0x2081)用于激活 SFM。需顺序写 SFMM 和
SFMS 才能激活 SFM。顺序写过程可以防止 MPU 意外进入 SFM。
激活 SFM 的顺序为:
•
首先,写 SFMM (I/O RAM 0x2080)寄存器。写入该寄存器的值定义 SFM 模式。
o
o
o
•
0xD1:整体擦除模式。进入 SFM 时,激活 FLASH 整体擦除循环。
0x2E:FLASH 读回模式。进入 SFM 的目的是为了 FLASH 读回。不阻止 FLASH 写操作,由
用户保证只写之前未被写的位置。SPI 加密模式被置位时,该模式不可用。
如果向 SFMM 寄存器写入其它任何值,均不会激活 SFM。
接着,写 0x96 至 SFMS (I/O RAM 0x2081)寄存器。如果之前对 SFMM 的写操作满足要求,该动作将激
活 SFM。向该寄存器写入其它任何值都不会激活 SFM。此外,对该寄存器的任何写操作都自动将之前
写入 SFMM 寄存器的值复位为 0。
Rev 2
77
71M6541D/F/G 和 71M6542F/G 数据资料
SFM 详细介绍
进入 SFM 时,发生以下事件:
•
•
•
•
•
CE 被禁用。
MPU 暂停。MPU 一旦暂停,只能通过复位重新启动。复位可通过 RESET 引脚、看门狗复位或重新上
电 (VBAT 引脚上无电池)完成。
当 MPU 处于 FLASH 写操作或擦除期间,FLASH 控制逻辑被复位。
如果在 SFMM 寄存器 I/O RAM 0x2080 (见上文激活 SFM)已经写入 0xD1,执行 FLASH 整体擦除。
SECURE 位(SFR 0xB2[6])在该循环及所有整体擦除循环结束时被清除。
现在,所有 SPI 读、写操作都针对 FLASH 而非 XRAM 空间。
通过对任意地址执行 4 字节 SPI 写操作并检查状态字段,SPI 主机可获取“循环 FLASH”操作的状态。
SFM 模式下的所有 SPI 写操作必须为 6 字节通信格式,将两个字节写入偶数地址。写通信必须含有 0xxx
xxxx 形式的命令字节。写操作时禁用自动递增。
SPI 读操作可使用自动递增,并且访问单字节。SFM 读操作中,命令字节必须总为 1xxx xxxx 形式。
SFM 模式下的 SPI 命令
SFM 模式下,由于 MPU 暂停,所以不产生中断。命令的格式在第 73 页的 SPI 通信说明部分介绍。
2.5.11 硬件看门狗定时器
71M6541D/F/G 和 71M6542F/G 中包括一个独立、可靠、固定 1.5 秒溢出时间的看门狗定时器(WDT)。它
利用 RTC 晶振作为时基, MPU 固件必须每 1.5 秒内刷新一次(喂狗)。超过刷新时间,WDT 溢出,
71M654x 将复位。看门狗复位与 RESET 引脚被拉高复位一样(关于 RESET 和唤醒之后的 I/O RAM 位状态
的完整清单,请参见第 5.2 节 I/O RAM 映射—字母顺序)。WDT 溢出之后经过 4100 个 CK32 周期(即 125
ms),MPU 才能够从程序地址 0x0000 开始运行。
内部信号 WAKE=0 时,看门狗定时器也复位(参见第 3.4 节唤醒操作)。
详情请参见第 3.3.4 节看门狗定时器复位。
2.5.12 测试端口(TMUXOUT和TMUX2OUT引脚)
TMUXOUT 和 TMUX2OUT 是两个独立的多功能测试引脚,用户固件可以选择输出内部模拟或数字信号。
这 些 引 脚 与 SEG47 和 SEG46 功 能 复 用 。 为 作 为 测 试 引 脚 , LCD_MAP[46] (I/O RAM 0x2406[6])和
LCD_MAP[47] (I/O RAM 0x2406[7])必须为 0。
可选择表 65 中所列数字或模拟信号之一在 TMUXOUT 引脚输出。复用器功能由 I/O RAM 寄存器
TMUX[5:0] (I/O RAM 0x2502[5:0])控制,如表 65 所示。
可选择表 66 中所列数字或模拟信号之一在 TMUX2OUT 引脚输出。复用器功能由 I/O RAM 寄存器
TMUX2[4:0] (I/O RAM 0x2503[4:0])控制,如表 66 所示。
TMUX[5:0]和 TMUX2[4:0] I/O RAM 为非易失存储器,其内容由电池电源保持,复位不会丢失。
78
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
TMUXOUT 和 TMUX2OUT 引脚可用于产品开发期间或生产测试期间的诊断。PULSE_1S:秒信号输出,
可用于校准晶振。PULSE_4S:4 秒输出为 RTC 校准提供更高的精度。RTCLK:亦可用于校准 RTC。
表 65. TMUX[5:0]选择
信号名称
说明
1
RTCLK
32.768kHz 时钟波形。
9
WD_RST
MPU 固件“喂狗”指示。通过监测确定看门狗定时器的空闲时
间。
A
CKMPU
MPU 时钟—见表 9。
D
V3AOK 位
表示 V3P3A 引脚电压≥ 3.0V。预计 V3P3A 和 V3P3SYS 引脚在
PCB 板级连接在一起。71M654x 仅监测 V3P3A 引脚电压。
E
V3OK 位
表示 V3P3A 引脚电压≥ 2.8V。预计 V3P3A 和 V3P3SYS 引脚在
PCB 板级连接在一起。71M654x 仅监测 V3P3A 引脚电压。
内部复用帧 SYNC 信号。请参见图 6 和图 7。
TMUX[5:0]
1B
MUX_SYNC
1C
CE_BUSY 中断
1D
CE_XFER 中断
1F
从 CE 的 RTM 输出
参见第 25 页第 2.3.3 节和第 47 页图 16。
参见第 25 页第 2.3.5 节。
注:
未列出的 TMUX[5:0]值均为保留。
表 66. TMUX2[4:0]选择
TMUX2[4:0]
信号名称
说明
0
WD_OVF
看门狗定时器溢出指示。
1
PULSE_1S
占空比为 25%的 1 秒脉冲。该信号可用于测量 RTC 相对于理想 1
秒间隔的偏差。应对多个周期的测试进行平均,滤除抖动。
2
PULSE_4S
占空比为 25%的 4 秒脉冲。该信号可用于测量 RTC 相对于理想 4
秒间隔的偏差。应对多个周期的测试进行平均,滤除抖动。4 秒脉
冲比 1 秒脉冲测量的精度更高。
3
RTCLK
32.768kHz 时钟波形。
8
SPARE[1] 位 – I/O RAM
0x2704[1]
复制 0x2704[1]的储存值,通用。
9
SPARE[2] 位 – I/O RAM
0x2704[2]
复制 0x2704[2]的储存值,通用。
A
WAKE
指示何时发生了 WAKE 事件。
内部复用帧 SYNC 信号,参见图 6 和图 7。
B
MUX_SYNC
C
MCK
参见第 50 页第 2.5.3 节。
E
GNDD
数字地,利用该信号将 TMUX2OUT 引脚置于静态。
12
13
14
15
16
17
18
INT0 – DIG I/O
INT1 – DIG I/O
INT2 – CE_PULSE
INT3 – CE_BUSY
INT4 - VSTAT
INT5 – EEPROM/SPI
INT6 – XFER, RTC
中断 0,参见第 40 页第 2.4.8 节,另请参见第 47 页图 16。
1F
RTM_CK (flash)
参见第 25 页第 2.3.5 节。
注:
未列出的 TMUX2[4:0]均为保留位。
Rev 2
79
71M6541D/F/G 和 71M6542F/G 数据资料
3
功能说明
3.1
工作原理
电源供给负载的能量可表示为:
t
E = ∫ V (t ) I (t )dt
0
假设相角不变,则下式成立:


P = 有功能量[Wh] = V * A * cos φ* t

S = 视在能量[VAh] =
Q = 无功能量[VARh] = V * A * sin φ * t
P2 + Q2
对于实际电表,电压、电流幅值、相位角和谐波分量会时常变化。所以,简单的 RMS 测量本质上并不精确。
现代固态电表 IC,例如 Teridian 71M654x,通过模拟上述积分运算进行计算,即处理 ADC 以恒定频率采
集的电流和电压值。只要 ADC 分辨率足够高,采样频率高于所要求的谐波范围,将电流和电压采样值乘以
采样时间周期,即可获得准确的瞬时能量。在时间上对瞬时能量值求和,即可获得非常准确的累积能量。
500
400
300
200
100
0
0
5
10
15
20
-100
-200
Current [A]
-300
Voltage [V]
Energy per Interval [Ws]
-400
Accumulated Energy [Ws]
-500
图 28. 电压、电流、瞬时能量和累积能量
图 28 所示为 V(t)、I(t)、瞬时功率和累积功率波形,电压和电流信号为 50 个采样点,周期为 20ms。
240VAC 和 100A 应用在 20ms 周期内的累积结果为 480Ws (= 0.133Wh),如累积功率曲线所示。即使存
在动态相位偏移和谐波失真,上述采样法也能够可靠工作。
80
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
电池供电模式
3.2
施加系统电源(V3P3SYS)后,器件马上处于任务模式(MSN 模式)。MSN 模式意味着器件由系统电源供电,
内部 PLL 稳定。该模式是器件能够测量能量的常规工作模式。
系统电源不可用时,71M654x 工作于以下三种电池模式之一:
•
•
•
BRN 模式(掉电模式)
LCD 模式(LCD 模式)
SLP 模式(休眠模式).
内部比较器监测 V3P3SYS 引脚电压(注意,V3P3SYS 和 V3P3A 通常在 PCB 上连接在一起)。V3P3SYS
电压下降至 3.0 VDC 以下时,比较器复位 V3OK 内部电源状态位。只要断开系统电源且 V3OK = 0,
71M654x 就切换至电池电源(VBAT 引脚),通过发起中断并更新 VSTAT[2:0]寄存器(SFR 0xF9[2:0] ,见表
68)通知 MPU。系统从 MSN 转换至 BRN 模式时,MPU 继续执行代码。关于 BRN 模式期间获得最低功耗
的设置,请参见第 3.2.1 节 BRN 模式。根据 MPU 代码,MPU 可选择留在 BRN 模式还是转换至 LCD 或
SLP 模式(通过 I/O RAM 位 LCD_ONLY , I/O RAM 0x28B2[6]和 SLEEP , I/O RAM 0x28B2[7])。除了由
V3P3A 电源供电外,BRN 模式与 MSN 模式类似,例如,ADC 不准确。BRN 模式下,CE 继续运行,应将
其关闭以节约 VBAT 功率。另外,PLL 继续以与 MSN 模式相同的频率工作,应降低其频率以节省功率
(CKGN = 0x24 (I/O RAM 0x2200)。
系统电源恢复时,71M654x 从任何电池模式(BRN、LCD、SLP)自动恢复至 MSN 模式,切回系统电源
(V3P3SYS、V3P3A)供电,发起中断并更新 VSTAT[1:0]。MPU 软件应通过发起软复位恢复 MSN 工作模式,
恢复与 MSN 模式对应的系统设置。
图 29 所示为各种工作模式的状态图,以及模式之间可能的转换。
器件在电池电源下唤醒时,自动进入 BRN 模式(见第 3.4 节唤醒功能)。从 BRN 模式,器件可进入 LCD 模
式或 SLP 模式,由 MPU 控制。
RESET
MSN
V3P3SYS
falls
VSTAT=00X
V3P3SYS
rises
System Power
Battery Power
VSTAT=001
V3P3SYS
rises
LCD_ONLY
BRN
V3P3SYS
rises
RESET &
VBAT
sufficient
Wake Flags
SLEEP or
VBAT
insufficient
Wake
event
LCD
Wake
event
VBAT
insufficient
VBAT
insufficient
RESET &
VBAT
insufficient
SLP
图 29. Operation 工作模式状态图
Rev 2
81
71M6541D/F/G 和 71M6542F/G 数据资料
从 LCD 和 SLP 模式至 BRN 模式的转换可由以下事件发起:
•
•
•
•
唤醒定时器超时。
按下按钮(PB)。
SEGDIO4、SEGDIO52 (仅限 71M6542F/G)或 SEGDIO55 引脚产生上升沿。
RX 或 OPT_RX 引脚有上升或下降沿产生。
MPU 可访问各种唤醒事件的标识寄存器,详情参见第 3.4 节唤醒功能。
表 67 所示为各种工作模式下的电路功能。
表 67. 电路功能
电路功能
CE (计算引擎)
FIR
ADC, VREF
PLL
电池测量
温度传感器
最大 MPU 时钟速率
MPU_DIV 时钟分频器
ICE
DIO 引脚
看门狗定时器
LCD
LCD 升压
EEPROM 接口(2 线)
EEPROM 接口(3 线)
UART (全速)
光 TX 调制
FLASH 读
FLASH 页擦除
FLASH 写
RAM 读和写
唤醒定时器
OSC 和 RTC
DRAM 数据保持
NV RAM 数据保持
系统电源
MSN (任务模式)
PLL_FAST=1
PLL_FAST=0
有
有
有
有
有
有
4.92MHz
(从 PLL)
有
有
有
有
有
有
有
有
有
38.4kHz
有
有
有
有
有
有
有
有
有
有
有
有
有
有
1.57MHz
(从 PLL)
有
有
有
有
有
有
有
有
有
38.9kHz
有
有
有
有
有
有
有
有
电池电源
BRN (掉电模式)
PLL_FAST=1 PLL_FAST=0
注1
--有
有
有
4.92MHz
(从 PLL)
有
有
有
有
有
有
有
有
有
38.4kHz
有
有
有
有
有
有
有
有
注1
--有
有
有
1.57MHz
(从 PLL)
有
有
有
有
有
有
有
有
有
38.9kHz
有
有
有
有
有
有
有
有
LCD
休眠
2
---2
升压
-有
-----有
--
--
----有
有
--------有
有
-有
-------------有
有
-有
注:
1.
2.
3.
82
CE 在 BRN 模式下有效,但是 ADC 数据不准确。MPU 应停止 CE 工作,以降低功耗(CE_E = 0,I/O RAM 0x2106[0])。
“--”表示相应电路不工作。
“升压”代表 LCD 升压电路工作(即 LCD_VMODE[1:0] = 10 (I/O RAM 0x2401[7:6])。LCD 升压电路需要来自 PLL 的时钟才可
工作。所以,LCD 模式下,如果 LCD 升压使能,PLL 将自动保持势能状态,否则 PLL 关闭。
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
3.2.1
BRN模式
BRN 模式下,大多数非计量数字功能处于有效工作状态(如表 67 所示),包括 ICE、UART、EEPROM、
LCD 和 RTC。BRN 模式下,PLL 继续以与 MSN 模式下相同的频率工作。MPU 应按比例缩小 PLL (使用
PLL_FAST,I/O RAM 0x2200[4])或 MPU 频率(使用 MPU_DIV[2:0],I/O RAM 0x2200[2:0]),以降低功耗。
BRN 模式下,MPU 可选择进入 LCD 或 SLP 模式。如果系统电源恢复时 71M654x 处于 BRN 模式,器件自
动转换至 MSN 模式。
BRN 模式下推荐的最小功耗配置如下:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RCE0 = 0x00 (I/O RAM 0x2709[7:0]) - 禁用远端传感器
LCD_BAT = 1 (I/O RAM 0x2402[7]) - LCD 由 VBAT 供电
LCD_VMODE[1:0] = 0 (I/O RAM 0x2401[7:6]) - 禁用 5V LCD 升压
CE6 = 0x00 (I/O RAM 0x2106) - 禁用 CE、RTM 和 CHOP
MUX_DIV[3:0] = 0 (I/O RAM 0x2100[7:4]) - 禁用 ADC 复用器
ADC_E = 0 (I/O RAM 0x2704[4]) – 禁用 ADC
VREF_CAL = 0 (I/O RAM 0x2704[7]) – 未驱动 Vref
VREF_DIS = 1 (I/O RAM 0x2704[6]) - 禁用 Vref
PRE_E = 0 (I/O RAM 0x2704[5] - 禁用前置放大器
BCURR = 0 (I/O RAM 0x2704[3]) - 关闭电池 100μA 电流负载
TMUX[5:0] = 0x0E (I/O RAM 0x2502[5:0]) – TMUXOUT 输出设置为直流值(即不做脉冲类输出)
TMUX2[4:0] = 0x0E (I/O RAM 0x2503[4:0]) – TMUXOUT2 输出设置为直流值(即不做脉冲类输出)
CKGN = 0x24 (I/O RAM 0x2200) - PLL 设置为低速,MPU_DIV[2:0] (I/O RAM 0x2200[2:0])设置为最大
TEMP_PER[2:0] = 6 (I/O RAM 0x28A0[2:0]) - 温度测量设置为每 512s 自动测量
TEMP_BSEL = 1 (I/O RAM 0x28A0[7]) - 温度传感器监测 VBAT
PCON = 1 (SFR 0x87) - 主 BRN 周期结束时,挂起 MPU 并等待中断
根据需要调节波特率寄存器
禁用所有不使用的中断
3.2.2
LCD模式
通过置位 LCD_ONLY 控制位(I/O RAM 0x28B2[6]),MPU 任何时候均可控制 LCD 模式。然而,建议 MPU
只有在 71M654x 进入 BRN 模式后置位 LCD_ONLY 控制位。例如,如果 71M654x 处于 MSN 模式时置位
LCD_ONLY,LCD 模式的持续时间就非常短,71M654x 马上被“唤醒”。
LCD 模式下,V3P3D 禁用,从而断开 VBAT 的全部漏电流。LCD_ONLY 模式有效之前,建议 MPU 把 PLL
输出频率降低至 6.2 MHz (即写 PLL_FAST = 0,I/O RAM 0x2200[4]),使 PLL 电流最小化。LCD 升压系统
需要来自 PLL 的时钟才可工作。所以,如果使能 LCD 升压系统(即 LCD_VMODE[1:0] = 10,I/O RAM
0x2401[7:6]),PLL 在 LCD 模式下将自动保持有效,否则 PLL 关闭。
LCD 模式下,LCD_SEG 寄存器数据通过对应的段驱动器引脚显示。最多可使两个连接至 SEGDIO22 和
SEGDIO23 的 LCDE 段闪烁,无需 MPU 参与(MPU 在 LCD 模式下被禁用)。为了将电池功耗最小化,应仅
仅使能使用的段。
从 LCD 模式转换至 MSN 或 BRN 模式后,PC (程序计数器)为 0x0000,XRAM 处于未定义状态,配置 I/O
RAM 位被复位(I/O RAM 唤醒后的状态见表 76)。LCD 模式下,储存在非易失 I/O RAM 的数据保持(表 76
中的阴影部分为非易失)。
Rev 2
83
71M6541D/F/G 和 71M6542F/G 数据资料
3.2.3
SLP模式
V3P3SYS 引脚电压下降至低于 2.8 VDC 时,71M654x 进入 BRN 模式,V3P3D 引脚从 VBAT (而非
V3P3SYS)供电。一旦处于 BRN 模式,MPU 即可通过置位 SLEEP 位(I/O RAM x28B2[7])激活 SLP 模式。
SLP 模式下功耗最低,此时仍然维持 RTC (实时时钟)、RTC 温度补偿和非易失 I/O RAM 工作。
SLP 模式下,V3P3D 断开,从而断开所有可能的 VBAT 电流消耗。非易失 I/O RAM、SLP 模式下的功能电
路,例如温度传感器、振荡器、RTC 和 RTC 温度补偿,由 VBAT_RTC 引脚供电。SLP 模式只能通过系统
上电或第 3.4 节唤醒功能介绍的方法之一退出。
V3P3SYS 引脚连接有供电电源时(即处于 MSN 模式),如果触发 SLEEP 位,71M654x 则进入 SLP 模式,
复位内部 WAKE 信号,此时,71M654x 开始第 3.4 节唤醒功能中介绍的从休眠模式唤醒的标准步骤。
V3P3SYS 恢复供电时,71M654x 从 SLP 模式转换至 MSN 模式,MPU PC (程序计数器)初始化为 0x0000。
此时,XRAM 处于未定义状态,但非易失 I/O RAM 的内容保持(表 76 中的阴影部分为非易失存储器)。
84
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
3.3
故障和复位操作
3.3.1
掉电事件
内部比较器通过监测 V3P3A 引脚的电压并监测内部产生的 VDD 电压(2.5 VDC)监测电源故障。V3P3SYS
和 V3P3A 引脚必须在 PCB 连接在一起,从而使内部连接至 V3P3A 的比较器能够同时监测 V3P3SYS 和
V3P3A 引脚电压。以下讨论假设 V3P3A 和 V3P3SYS 引脚在 PCB 连接在一起。
电源故障期间,当 V3P3A 下降时,检测两个门限:
•
•
第一个门限,3.0 VDC (VSTAT[2:0] = 001),向 MPU 报告模拟电路不再准确。除报告 MPU 外,硬件不
切换电源。该状态对应内部标志位 V3AOK。
第二个门限,2.8 VDC,使 71M654x 切换至电池供电。此时仍然能够对 FLASH 和 RAM 进行读、写。
该状态对应内部标志位 V3OK。
电源状况由 SFR VSTAT[2:0]字段反映,如表 68 所示。VSTAT[2:0]字段位于 SFR 地址 0xF9,占用[2:0]位,
为只读。
除了主电源状态,VSTAT[2:0]寄存器还提供电池供电时内部 VDD 电压的信息。注,如果系统电源(V3P3A)
高于 2.8 VDC,71M6541D/F/G 和 71M6542F/G 总是从电池切换至系统电源供电。
表 68. VSTAT[2:0] (SFR 0xF9[2:0])
VSTAT[2:0]
说明
000
系统电源正常,V3P3A > 3.0 VDC。模拟电路正常工作并保持精确采集。
001
系统电源低,2.8 VDC < V3P3A < 3.0 VDC。模拟电路不准确。即将切换至电池电源。
010
IC 由电池供电,VDD 正常。VDD > 2.25 VDC,IC 保持完整的数字功能。
011
IC 由电池供电,2.25 VDC > VDD > 2.0 VDC。禁止 FLASH 写操作。
101
IC 由电池供电,VDD < 2.0 VDC,MPU 接近电压失效。在 4 个晶振时钟 CK32 周期内产
生复位。
对系统电源故障的响应几乎完全受固件控制。电源故障期间,系统性能缓慢下降。由内部比较器监测,使
硬件自动切换至 VBAT 输入供电。中断通知 MPU 由电池供电,此时,MPU 负责降低主频、禁用 PLL,以
降低功耗。
精密模拟电路,例如带隙基准、带隙缓冲器和 ADC,只能由 V3P3A 引脚供电(即由 V3P3A 引脚供电的电
路不能切换至 VBAT 供电);随着 V3P3A 引脚电压持续下降,这部分电路的精度下,最终导致失效。
V3P3A 引脚下降至 2.8 VDC 以下时,ADC 时钟暂停,放大器无偏置电压。在此期间,控制位,例如
ADC_E 位(I/O RAM 0x2704[4]),不受影响,因为其 I/O RAM 由 VDD 引脚(2.5 VDC)供电。VDD 引脚通过连
接至 V3P3D 引脚的内部 2.5 VDC 稳压器供电。V3P3SYS 引脚下降至 3.0 VDC 以下时,V3P3D 引脚切换
至 VBAT 引脚供电。注意,V3P3SYS 和 V3P3A 引脚通常在 PCB 连接在一起。
Rev 2
85
71M6541D/F/G 和 71M6542F/G 数据资料
3.3.2
低电池电压下的IC
没有系统电源供电时,71M6541D/F/G 和 71M6542F/G 将依赖 VBAT 引脚供电。如果 VBAT 电压不足以将
VDD 维持在 2.0 VDC 或更高,MPU 则无法可靠工作。器件工作于 BRN 模式,或者潜伏于 SLP 或 LCD 模
式时,将导致 VBAT 电压跌落。依据 MPU 代码,可区分两种情形:
•
情形 1:无系统电源供电,器件从 SLP 或 LCD 模式唤醒。这种情况下,硬件检查 VDD 数值,确定处
理器是否可能工作。如果不可能工作,器件将配置为 BRN 工作模式,保持处理器复位(WAKE=0)到该
模式下,VBAT 为 LCD 系统、VDD 稳压器、PLL 和故障比较器提供 1.0 VDC 基准。器件维持在这种等
待模式,直到施加系统电源或更换电池或重新为 VBAT 电池充电,使 VDD 达到足够的电压。
•
情形 2:器件由 VBAT 供电,VSTAT[2:0] (SFR 0xF9[2:0])变为 101(二进制),表示 VDD 下降至 2.0
VDC。这种情况下,固件有两种选择:
1) 一种选择是立即触发 SLEEP 位(I/O RAM 0x28B2[7])。这样可以保持 VBAT 中的剩余电量。当然,如
果电池电压未升高,71M654x 只要试图唤醒,则进入情形 1。
2) 另一种选择是立即进入情形 1 所述的等待模式,即如果固件未触发 SLEEP 位,硬件在 VSTAT[2:0]变
为 101 后 4 个 CK32 时钟周期(即 122μs)后复位处理器,如情形 1 所述,开始等待 VDD 变为高于
2.0 VDC。系统电源恢复时,或者 VDD 高于 2.0 VDC 时,MPU 唤醒。
无论哪种情况,当 VDD 恢复,同时 MPU 唤醒时,可读取 WF_BADVDD 标识(I/O RAM 0x28B0[2]),确定处
理器正从 VBAT 失效条件下恢复。WF_BADVDD 标识保持置位,直到下一次 WAKE 变低。该标记独立于其
它 WF 标识。
任何情况下,低 VBAT 电压都不会破坏 RTC 工作、NV 存储器状态或非易失存储器状态。因为这些电路由
VBAT_RTC 引脚供电。
3.3.3
复位序列
RESET 引脚拉高时,芯片内的所有数字功能停止,只有振荡器和 RTC 除外。此外,全部 I/O RAM 强制为
其 RST 状态。只有 RESET 为高电平并维持至少 2μs 的条件下,才发生可靠复位。注意,TMUX 和 RTC
的复位条件:TEST 引脚在 RESET 为高电平时拉高。
RESET 控制位(I/O RAM 0x 2200[3])与 RESET 引脚的复位效果完全相同。唯一需要保证的是 RESET 控制位
使用的复位定时器更短。
一旦启动,复位序列进行等待,直到复位定时器超时。超时发生在 4100 个 CK32 周期(125ms)内,此时,
MPU 从 0x0000 地址开始执行预引导和引导程序。关于预引导和引导程序的详细说明,请参见第 2.5.11 节
硬件看门狗定时器。
如果没有系统电源,复位定时器持续时间为 2 个 CK32 周期,此时,MPU 从地址 0x0000 开始执行 BRN 模
式。
ICE 接口的 E_RST 引脚拉低时,启动软件复位。该事件造成 MPU 及 MPU 核内其它寄存器复位,但是不
复位 IC 的其余部分,例如 I/O RAM。它不触发复位过程。这类复位的本意是复位 MPU 程序,而对芯片的
状态不做其它更改。
3.3.4
看门狗定时器复位
看门狗定时器(WDT)在第 2.5.11 节硬件看门狗定时器中详细说明。
WDT 发生溢出时,状态位 WF_OVF (I/O RAM 0x28B0[4])置位。与其它唤醒标识相似,该位由非易失电源供
电,可由 MPU 读取,以确定芯片复位是因为 WD 溢出、还是重新上电。WF_OVF 位由 RESET 信号清零,
也可以软件清零。
MPU 内部没有寄存器可以禁止 WDT。然而,为了调试,可将 ICE_E 引脚升高至 3.3 VDC,禁用 WDT。
正常工作时,通过定期向 WD_RST 控制位(I/O RAM 0x28B4[7])写 1 进行“喂狗”。71M654x 从 LCD 或
SLP 模式唤醒时,以及 ICE_E = 1 时,看门狗定时器也复位。
86
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
唤醒操作
3.4
如上所述,系统电源恢复时,器件总是在 MSN 模式唤醒。如第 3.2 节电池供电模式所述,从 LCD 和 SLP
模 式 至 BRN 模 式 的 转 换 可 由 唤 醒 定 时 器 超 时 、 按 钮 (PB) 输 入 置 为 高 电 平 、
SEGDIO4/SEGDIO52/SEGDIO55 置高,或者触发 RX 或 OPT_RX 引脚启动。
3.4.1
硬件唤醒事件
以下引脚信号事件将 71M654x 从 SLP 或 LCD 模式唤醒:PB 引脚的高电平、RX 引脚的任意信号沿、
SEGDIO4 引 脚 的 上 升 沿 、 SEGDIO52 引 脚 (71M6542F/G) 的 高 电 平 , SEGDIO55 引 脚 的 高 电 平 或
OPT_RX 引脚的任意信号沿。关于每一引脚的去抖,及 OPT_RX/SEGDIO55 引脚的更多信息,请参见表
69。SEGDIO4、SEGDIO52 (71M6542F/G)和 SEGDIO55 引脚必须配置为 DIO 输入,且必须置位其唤醒
使能位(EW_x 位)。SLP 和 LCD 模式下,MPU 保持在复位状态,不能轮询引脚或响应中断。发生其中一个
硬件唤醒事件时,内部 WAKE 信号升高,MPU 在 3 个 CK32 周期内开始执行。MPU 通过检查 WF_PB、
WF_RX 、 WF_SEGDIO4 、 WF_DIO52 (71M6542F/G)或 WF_DIO55 标识,可确定哪个引脚将其唤醒(见表
69)。
如果器件处于 SLP 或 LCD 模式,可由 PB 引脚的高电平唤醒。该引脚通常拉至 GND,可从外部连接,所
以可用按钮将其拉高。
有些引脚需要去抖,以抑制 EMI 噪声。检测硬件忽略初始跳变以后的所有跳变。表 69 列出了配有防抖电
路的引脚。
没有去抖电路的引脚,仍然必须保持为高电平至少达 2μs 才能有效识别。
表 69 还列出了唤醒使能和标识位。唤醒标识位由硬件在 MPU 从唤醒事件唤醒时置位。注意,只要按下
PB,PB 标识即被置位,即使器件处于唤醒状态。
表 71 列出了清除 WF 标识的事件。
除按钮和定时器外,器件还可以由以下事件重启:RESET 引脚、RESET 控制位(I/O RAM 0x2200[3])、WDT、
冷启动检测器和 E_RST。如表 69 所示,每种方法都有一个标识位,向 MPU 通告唤醒源。如果唤醒是由于
系统电源恢复引起的,则没有有效的 WF 标识,VSTAT[2:0]字段(SFR 0xF9[2:0])表示系统电源稳定。
表 69. 唤醒使能和标识位
唤醒使能
唤醒标识
去抖
说明
名称
位置
名称
位置
WAKE_ARM
28B2[5]
WF_TMR
28B1[5]
无
定时器唤醒。
EW_PB
28B3[3]
WF_PB
28B1[3]
有
PB 唤醒*。
EW_RX
28B3[4]
WF_RX
28B1[4]
2µs
RX 信号沿唤醒。
EW_DIO4
28B3[2]
WF_DIO4
28B1[2]
2µs
SEGDIO4 唤醒。
EW_DIO52†
28B3[1]
WF_DIO52
28B1[1]
有
SEGDIO52 唤醒*。
WF_DIO55
28B1[0]
有
总使能
WF_RST
28B0[6]
2µs
总使能
WF_RSTBIT
28B0[5]
无
总使能
WF_ERST
28B0[3]
2µs
EW_DIO55
Rev 2
28B3[0]
SECURE = 1:DIO55*唤醒,64ms
去抖。
OPT_RXDIS = 0:OPT_RX 信号眼
唤醒,2μs 去抖。
OPT_RXDIS: I/O RAM 0x2457[2]
RESET 后唤醒。
RESET 位之后唤醒。
E_RST 后唤醒。
(只有 ICE_E 为高电平才有效)
87
71M6541D/F/G 和 71M6542F/G 数据资料
唤醒使能
名称
唤醒标识
位置
去抖
说明
名称
位置
总使能
WF_OVF
28B0[4]
无
WD 复位后唤醒。
总使能
WF_CSTART
28B0[7]
无
冷启动后唤醒—首次加电。
总使能
WF_BADVDD
28B0[2]
无
VBAT 电压不足后唤醒。
†仅限 71M6542F/G。
*每 2ms 采样该引脚一次,必须保持为高达 64ms 才能为有效的高电平。该引脚为高电平触发。
88
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
表 70. 唤醒位
名称
位置
复位
唤醒
方向
EW_DIO4
28B3[2]
0
–
R/W
EW_DIO52
28B3[1]
0
–
R/W
EW_DIO55
28B3[0]
0
–
R/W
WAKE_ARM
28B2[5]
0
–
R/W
EW_PB
28B3[3]
0
–
R/W
EW_RX
28B3[4]
0
–
R/W
WF_DIO4
28B1[2]
0
–
R
WF_DIO52
28B1[1]
0
–
R
WF_DIO55
28B1[0]
0
–
R
WF_TMR
WF_PB
WF_RX
WF_RST
WF_RSTBIT
WF_ERST
WF_CSTART
WF_BADVDD
28B1[5]
28B1[3]
28B1[4]
28B0[6]
28B0[5]
28B0[3]
28B0[7]
28B0[2]
0
0
0
*
*
*
*
*
–
–
–
R
R
R
Rev 2
–
R
说明
连接 SEGDIO4 至 WAKE 逻辑,允许 SEGDIO4 上升
唤醒器件。除非 SEGDIO4 配置为数字输入,否则无
效。
连接 DIO52 至 WAKE 逻辑,允许 DIO52 高电平唤醒
器件(1M6542)。除非 DIO52 被配置为数字输入,否则
无效。
连接 DIO55 至 WAKE 逻辑,允许 DIO55 高电平唤醒
器件。除非 DIO55 配置为数字输入,否则无效。
准备好 WAKE 定时器,并装载 WAKE_TMR 寄存器(I/O
RAM 0x2880)值。MPU 使能 SLP 模式或 LCD 模式时,
WAKE 定时器有效工作。
连接 PB 引脚至 WAKE 逻辑,允许 PB 高电平唤醒器
件。PB 总是配置为输入。
连接 RX 引脚至 WAKE 逻辑,允许 RX 上升唤醒器
件。关于去抖事项,请参见第 3.4.1 节。
SEGDIO4 标识位。如果 SEGDIO4 配置为唤醒器件,
只要 SEGDIO4 升高,该位置位。如果 SEGDIO4 未配
置为唤醒,它将保持在复位状态。
SEGDIO52 标识位。如果 SEGDIO52 配置为唤醒器
件 , 只 要 SEGDIO52 为 高 电 平 , 该 位 置 位 。 如 果
SEGDIO52 未 配 置 为 唤 醒 , 它 将 保 持 在 复 位 状 态
(71M6542F/G)。
SEGDIO55 标识位。如果 SEGDIO55 配置为唤醒器
件 , 只 要 SEGDIO55 为 高 电 平 , 该 位 置 位 。 如 果
SEGDIO55 未配置为唤醒,它将保持在复位状态。
表示唤醒定时器造成器件唤醒。
表示 PB 引脚造成器件唤醒。
表示 RX 引脚造成器件唤醒。
表示 RST 引脚、E_RST 引脚、RESET 位(I/O RAM
0x2200[3])、冷启动检测或 VBAT 引脚的低电压造成器
件复位。
*详细信息请参见表 71。
89
71M6541D/F/G 和 71M6542F/G 数据资料
表 71. WAKE 标识清除事件
标识
唤醒事件
清除事件
定时器终止
WAKE 变低
WF_PB
PB 引脚高电平
WAKE 变低
WF_RX
RX 引脚信号沿
WAKE 变低
WF_DIO4
SEGDIO4 上升沿
WAKE 变低
WF_DIO52
SEGDIO52 高电平(仅限 71M6542F/G)
WAKE 变低
WF_DIO55
如果 OPT_RXDIS = 1 (I/O RAM
0x2457[2]),SEGDIO55 高电平唤醒
如果 OPT_RXDIS = 0,OPT_RX 任意信号
沿唤醒
WAKE 变低
WF_TMR
WF_RST
WF_RSTBIT
WF_ERST
WF_OVF
WF_CSTART
RESET 引脚驱动为高
WAKE 变低,WF_CSTART, WF_RSTBIT,
WF_OVF, WF_BADVDD
RESET 位置位(I/O RAM 0x2200[3])
WAKE 变低,WF_CSTART, WF_OVF,
WF_BADVDD, WF_RST
E_RST 引脚驱动为高,必须通过驱动
ICE_E 引脚为高电平,使能 ICE。
WAKE 变低,WF_CSTART, WF_RST,
WF_OVF, WF_RSTBIT
看门狗(WD)复位
WAKE 变低,WF_CSTART, WF_RSTBIT,
WF_BADVDD, WF_RST
冷启动(即首次加电后)
WAKE 变低,WF_RSTBIT, WF_OVF,
WF_BADVDD, WF_RST
注:
“WAKE 变低”意味着内部 WAKE 信号已复位,在进入 LCD 模式或 SLEEP 模式时自动发生 WAKE 信号
复位(即 MPU 置位 LCD_ONLY 位(I/O RAM 0x28B2[6])或 SLEEP (I/O RAM 0x28B2[7])位)。内部 WAKE 信
号复位时,全部唤醒标识被复位。由于各种唤醒标识在 WAKE 变低时自动复位,MPU 就没必要在进入
LCD 模式或 SLEEP 模式之前复位这些标识。此外,其它唤醒事件会造成唤醒标识复位,如上所示(例如,
WF_RST 标识在以下标识置位时被复位:WF_CSTART、WS_RSTBIT、WF_OVF、WF_BADVDD)。
3.4.2
定时器唤醒
如果器件处于 SLP 或 LCD 模式,可由唤醒定时器唤醒。该定时器超时之前,由于 WAKE 信号为低,MPU
处于复位状态。唤醒定时器超时时,WAKE 升高,MPU 在三个 CK32 周期内开始执行。通过检查 WF_TMR
唤醒标识(I/O RAM 0x28B1[2]),MPU 可判断为定时器唤醒。
器件进入 LCD 或 SLP 模式时,唤醒定时器开始计时。其持续时间由 WAKE_TMR[7:0] 寄存器(I/O RAM
0x2880)控制。定时器持续时间为 WAKE_TMR +1 秒。
通过设置 WAKE_ARM = 1 (I/O RAM 0x28B2[5])使能唤醒定时器,置位与进入 SLP 或 LCD 模式之前必须至
少有 3 个 CK32 的延时。置位 WAKE_ARM 以使能 WAKE_TMR 中的值预设定时器,MPU 写 SLEEP (I/O
RAM 0x28B2[7])或 LCD_ONLY (I/O RAM 0x28B2[6])位时,启动唤醒定时器。MPU 唤醒时,定时器既不复位
也不运行。因此,一旦设定和置位,MPU 在进入 SLP 模式或 LCD 模式后将每 WAKE_TMR[7:0]秒后唤醒
(即,一旦写入,WAKE_TMR[7:0]寄存器保持其值,不必在 MPU 每次进入 SLP 或 LCD 模式时重写。此外,
由于 WAKE_TMR[7:0]非易失,所以能在复位和电源故障时保持值)。
90
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
数据流和MPU/CE通信
3.5
计算引擎(CE)和 MPU 之间的数据流如图 30 所示。典型应用中,32 位 CE 顺序处理来自 IA、VA、IB 等引
脚输入电压的采样,执行计算,测量有功(Wh)、无功(VARh)、A2h 和 V2h,实现四象限表计。然后 MPU 存
取这些测量值,进一步处理并通过 MPU 可用的外围器件输出。
CE 和复用器均由 MPU 通过 I/O RAM 和 RAM 中的共用寄存器控制。
CE 总共可以输出 6 种信号至 MPU。包括 4 个脉冲和 2 个中断:
•
•
•
•
CE_BUSY
XFER_BUSY
WPULSE, VPULSE (用于有功和无功能量的脉冲)
XPULSE, YPULSE (辅助脉冲)
这些中断作为外部中断连接至 MPU 中断服务输入。CE_BUSY 表示 CE 正在处理数据。该信号每个复用循
环(典型为 1/2520=396μs)一次,表示 CE 已经更新 CESTATUS 寄存器(CE RAM 0x80)中的状态信息。
XFER_BUSY 表示 CE 正在将数据更新至 RAM 输出区域。CE 完成由 SUM_SAMPS[12:0]、I/O RAM
0x2107[4:0]、2108[7:0]确定的累积间隔(典型设定为 2520,即每 1000 ms)内的数据累加,就会产生该指示。
MPU 的中断发生在 XFER_BUSY 和 CE_BUSY 信号的下降沿。
WPULSE 和 VPULSE 通常用于表示有功(Wh)和无功(VARh)能量的能量累积。将 WPULSE 和 VPULSE 纳
入 MPU 中断系统可实现脉冲计数。
XPULSE 和 YPULSE 可用于向 MPU 发出事件告警。例如电网电压跌落和过零。将这些输出纳入 MPU 中
断系统,MPU 就没必要在每次发生 CE_BUSY 中断时读取 CESTATUS 寄存器,以检测跌落或过零事件。
Pulses
XPULSE
YPULSE
Interrupts
VPULSE
WPULSE
CE_BUSY
XFER_BUSY
CE
Samples
Processed
Metering
Data
CESTATUS
CECONFIG
MUX
Control
MPU
Control
Control
XRAM
I/O RAM (Configuration RAM)
图 30. MPU/CE 数据流
更多有关 CE 设置的信息,请参见第 5.3 节的 CE 接口说明。
Rev 2
91
71M6541D/F/G 和 71M6542F/G 数据资料
4
应用信息
4.1
连接 5V器件
71M654x 的全部数字输入兼容于外部 5V 供电器件。配置为输入的 I/O 引脚连接至外部 5V 供电器件时,不
需要加限流电阻。
4.2
直接连接传感器
图 31 至图 34 所示为电压检测分压电阻、电流检测电流变压器(CT)和电流检测锰铜分流器,以及它们与
71M654x 连接示意图。连接至 71M654x 传感器输入的全部输入信号为电压信号,按比例表示检测到的电
压或电流。
71M654x 的模拟输入引脚设计用于低阻传感器。RC 滤波器的电阻值不要超过 Teridian 演示板
中的电阻阻值。关于完整的传感器输入电路及对应元件值,请参见演示板原理图。
RIN
VA
VIN
ROUT
V3P3A
图 31. 电阻分压(电压检测)
IIN
IOUT
IAP
CT
RBURDEN
VOUT
V3P3A
Noise Filter
1:N
图 32. 单端输入 CT (电流检测)
IIN
IOUT
IAP
V3P3A
CT
RBURDEN
VOUT
IAN
Bias Network and Noise Filter
1:N
图 33. 差分输入 CT (电流检测)
IIN
IAP
V3P3A
RSHUNT
VOUT
IAN
Bias Network and Noise Filter
图 34. 差分输入锰铜分流器(电流检测)
92
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
使用本地传感器的 71M6541D/F/G
4.3
图 35 所示为使用本地电流传感器的 71M6541D/F/G 接线示意图。IAP-IAN 电流通道可采用锰铜分流器或
CT,IBP-IBN 通道采用 CT,因为需要隔离。此配置实现单相测量,利用一个电流传感器测量零线电流,具
有防窃电检测功能。这种配置亦可用于构建分相电表(例如 ANSI Form 2S)。为获得最佳性能,IAP-IAN 和
IBP-IBN 电流传感器输入均配置为差分模式(即,DIFFA_E = 1,DIFFB_E = 1 , I/O RAM 0x210C[4]和
0x210C[5])。同时 IBP-IBN 通道必须配置成禁用远端传感器接口(即,RMT_E = 0,I/O RAM 0x2709[3] )。与
图 35 对应的 AFE 配置请参见图 2。
NEUTRAL
CT
CT or
LOAD
Shunt
LINE
NEUTRAL
Note:
This system is referenced to LINE
POWER SUPPLY
Resistor Divider
LINE
MUX and ADC
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
LINE
IAP
IAN
TERIDIAN
WAKE-UP
71M6541D/F
REGULATOR
BATTERY
VBAT
VA
VBAT_RTC
IBP
IBN
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
AMR
IR
TX
POWER FAULT
COMPARATOR
HOST
RAM
COM0...5
SEG
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
BATTERY
MONITOR
FLASH
MEMORY
MPU
RTC
TIMERS
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
11/5/2010
图 35. 71M6541D/F/G (本地传感器)
Rev 2
93
71M6541D/F/G 和 71M6542F/G 数据资料
使用 71M6x01 和电流分流器的 71M6541D/F/G
4.4
图 36 所示为隔离和非隔离锰铜传感器的典型连接(采用 71M6x01 远端传感器接口)。该配置实现单相测量,
采用第二个电流传感器,具有防窃电检测功能。这种配置亦可用于构建分相电表(例如 ANSI Form 2S)。为
获得最佳性能,IAP-IAN 电流传感器输入配置为差分模式(即,DIFFA_E = 1,I/O RAM 0x210C[4])。
71M6x01 远端传感器接口的输出通过脉冲变压器连接至引脚 IBP-IBN。IBP-IBN 引脚必须配置为远端传感
器通信接口(即 RMT_E = 1,I/O RAM 0x2709[3])。与图 36 对应的 AFE 配置请参见图 3。
NEUTRAL
Shunt
LOAD
Note:
This system is referenced to LINE
Shunt
LINE
NEUTRAL
POWER SUPPLY
LINE
Resistor Divider
LINE
TERIDIAN
71M6xx1
MUX and ADC
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
IAP
IAN
Pulse
Transformer
TERIDIAN
WAKE-UP
71M6541D/F
REGULATOR
BATTERY
VBAT
VA
VBAT_RTC
IBP
IBN
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
AMR
IR
TX
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
RAM
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
11/5/2010
图 36. 71M6541D/F/G (71M6x01 远端传感器)
94
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
使用本地传感器的 71M6542F/G
4.5
图 37 所示为使用本地电流传感器的 71M6542F/G 接线示意图。IAP-IAN 电流通道可采用锰铜分流器或 CT,
IBP-IBN 通道采用 CT,因为需要隔离。此配置实现两相测量,按照公式 2 计算。为获得最佳性能,IAPIAN 和 IBP-IBN 电流传感器输入均配置为差分模式(即 DIFFA_E = 1,DIFFB_E = 1,I/O RAM 0x210C[4]和
0x210C[5])。同时 IBP-IBN 输入必须配置为禁用远端传感器接口(即,RMT_E = 0,I/O RAM 0x2709[3])。与
图 37 对应的 AFE 配置请参见图 4。
CT or
Shunt
PHASE A
LOAD
NEUTRAL
Shunt
Note:
This system is referenced to PHASE A
LOAD
PHASE B
NEUTRAL
POWER SUPPLY
Resistor Dividers
PHASE A
MUX and ADC
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
IAP
IAN
PHASE A
TERIDIAN
71M6542F
WAKE-UP
REGULATOR
VB
VA
VBAT
VBAT_RTC
IBP
IBN
SERIAL PORTS
IR
TX
RAM
MODUL- RX
ATOR TX
COM0...5
SEG
COMPUTE
ENGINE
RX
POWER FAULT
COMPARATOR
HOST
BATTERY
MONITOR
TEMPERATURE
SENSOR
VREF
AMR
BATTERY
FLASH
MEMORY
MPU
RTC
TIMERS
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
11/5/2010
图 37. 71M6542F/G (本地传感器)
Rev 2
95
71M6541D/F/G 和 71M6542F/G 数据资料
使用 71M6x01 和电流分流器的 71M6542F/G
4.6
图 38 所示为使用隔离和非隔离的 71M6542F/G 的典型 2 相连接。为获得最佳性能,IAP-IAN 电流传感器输
入配置为差分模式(即,DIFFA_E = 1,I/O RAM 0x210C[4])。71M6x01 远端传感器接口用于隔离 B 相。
71M6x01 远端传感器接口的输出通过脉冲变压器连接至引脚 IBP-IBN。IBP-IBN 引脚必须配置为远端传感
器通信接口(即 RMT_E = 1,I/O RAM 0x2709[3])。与图 38 对应的 AFE 配置请参见图 5。
Shunt
PHASE A
LOAD
NEUTRAL
Shunt
Note:
This system is referenced to PHASE A
LOAD
PHASE B
NEUTRAL
POWER SUPPLY
PHASE A
Resistor Dividers
PHASE A
TERIDIAN
71M6XX1
MUX and ADC
Pulse
Transformer
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
IAP
IAN
TERIDIAN
71M6542F
VB
VA
TEMPERATURE
SENSOR
SERIAL PORTS
TX
RAM
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
BATTERY
VBAT
VREF
IR
REGULATOR
VBAT_RTC
IBP
IBN
AMR
WAKE-UP
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
图 38. 71M6542F/G (71M6x01 远端传感器)
96
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
4.7
计量温度补偿
4.7.1
高精度电压基准
由于 VREF 的带隙放大器带有斩波稳定电路(由 CHOP_E[1:0] I/O RAM 0x2106[3:2]控制字段设置),因此可
以有效的消除电压基准(VREF)最常见的长期直流漂移。71M654x 和 71M6x01 各自的 VREF 电压基准源均
具有斩波电路。
Teridian 在器件生产过程中对 VREF 电压基准进行调节。
基准电压(VREF)调整在目标值 1.195V。调节过程中,TRIMT[7:0] (I/O RAM 0x2309)储存在非易失熔丝器件
中。TRIMT[7:0]调节到某一适当值,使得 VREF 随温度变化的波动最小。
对 于 71M654x 器 件(±0.5%能量 精度), MPU 可在初 始化期间读 取 TRIMT[7:0] 值,以计 算适合每 个
71M654x 器件的抛物线温度补偿系数。保证 71M654x 中 VREF 的温度系数为±40ppm/°C。
考虑工厂的 VREF 校准温度为+22°C,工业温度范围(-40°C 至+85°C),所以 71M654x 器件在极端温度时
的 VREF 误差可计算如下:
(85o C − 22 o C ) ⋅ 40 ppm / oC = +2520 ppm = +0.252%
and
(−40 C − 22 C ) ⋅ 40 ppm / oC = −2480 ppm = −0.248%
o
o
以上计算结果表示:理论上,电压和电流测量值的最大误差分约为±0.25%。电压采样和电流采样相乘,获
得每次采样的能量时,电压误差和电流误差组合造成最大能量测量误差为±0.5%。然而,理论误差±0.5%仅
考虑了电压基准(VREF)一个误差源。实际应用中,系统中还有其它误差源。基本的剩余误差源包括:电流
传感器(分流器或 CT)及其对应的信号处理电路,以及用于测量电压的分压电阻。因此 0.5%级 71M654x 器
件应用于 Class 1%设计时,为系统中其它误差源留有足够裕量。
4.7.2
71M654x的温度系数
下面提供的公式用于计算加至 71M654x (0.5%能量精度)的 TC1 和 TC2。为了获得 TC1 和 TC2,MPU 读
取 TRIMT[7:0] (I/O RAM 0x2309),并使用提供的 TC1 和 TC2 公式。然后即可利用 TC1 和 TC2 计算 PPMC
和 PPMC2,如下所示。得到的基准电压(VREF)曲线控制在±40ppm/°C 之内,对应于±0.5%能量测量精度。
请参见第 4.7.1 节电压基准精度。
TC1 = 275 − 4.95 ⋅ TRIMT [7 : 0]
TC 2 = −0.557 + 2.8 ⋅ 10 −4 ⋅ TRIMT [7 : 0]
PPMC =
PPMC 2 =
2 21
57 ⋅ 1.195
2 29
5 8 ⋅1.195
⋅ TC1 = 22.4632 ⋅ TC1
⋅ TC 2 = 1150.116 ⋅ TC 2
TC1 和 TC2 分别乘以一个系数得到 PPMC 和 PPMC2,该系数由 1.195V ADC 电压基准和 CE 的比例调节
电路决定,如上所示。
关于温度补偿的更多详细信息,请参见第 4.7.3 节和第 4.7.4 节。
Rev 2
97
71M6541D/F/G 和 71M6542F/G 数据资料
4.7.3
VREF温度补偿,使用本地传感器
本节讨论使用本地传感器的电表设计的计量温度补偿,如图 35 和图 37 所示。
在这些配置中,所有传感器直接连接至 71M654x,每个传感器通道的精度受 71M654x 中 VREF 随温度变
化引起的电压变动的影响。71M654x 中的 VREF 可利用温度的二阶多项式函数进行数字补偿。71M654x
具有片上温度传感器,用于对其 VREF 进行温度补偿。71M654x 还存在外部误差源。电压采样部分的电分
压阻和电流采样部分的锰铜分流器和/或 CT,及其对应的信号调理电路也受温度的影响。根据要求的精度
等级,它们也可能需要补偿。对于这些外部误差源的补偿,可选择与 VREF 的补偿集总在一起,将其补偿
合并至每个对应通道的 PPMC 和 PPMC2 系数。
MPU 根据检测到的温度计算每个传感器通道所需的补偿值。Teridian 提供演示程序,实现如下所示
GAIN_ADJn 补偿方程。得到的 GAIN_ADJn 值被 MPU 储存在三个 CE RAM 地址 GAIN_ADJ0-GAIN_ADJ2
(CE RAM 0x40-0x42) 。 演 示 代 码 提 供 了 合 适 的 温 度 补 偿 方 法 , 但 利 用 片 上 温 度 传 感 器 和 CE RAM
GAIN_ADJn 储存地址,可在 MPU 固件中采用其它方法。演示代码维护三组独立的 PPMC 和 PPMC2 系统,
并根据检测到的温度用下式计算三个独立的 GAIN_ADJn 值:
GAIN _ ADJ = 16385 +
10 ⋅ TEMP _ X ⋅ PPMC
214
+
100 ⋅ TEMP _ X 2 ⋅ PPMC 2
2 23
式中,TEMP_X 为相对于标称值或校准温度的偏差,以 0.1 °C 的整数倍表示。例如,由于 71M654x 校准
(基准)温度为 22 oC,实测温度为 27 oC,所以 TEMP_X = (27-22) x 10 = 50 (十进制),表示相对于 22 oC
的偏差为+5 oC。
表 73 给出了 GAIN_ADJn 输出值,以及补偿后的电压或电流测量值。
•
•
•
GAIN_ADJ0 补偿 71M654x 中的 VA 和 VB (71M6542F/G)电压测量值,用于补偿 71M654x 中的 VREF。
设计者可选择把对分压电阻的补偿增加至该通道的 PPMC 和 PPMC2 系数。
GAIN_ADJ1 提供对 IA 电流通道的补偿和对 71M654x VREF 的补偿。设计者可选择把对锰铜分流器或
CT 及对应信号调理电路的补偿增加至该通道的 PPMC 和 PPMC2 系数。
GAIN_ADJ2 提供对 IB 电流通道的补偿和对 71M654x VREF 的补偿。设计者可选择把对 CT 及对应信
号调理电路的补偿增加至该通道的 PPMC 和 PPMC2 系数。
表 72. GAIN_ADJn 补偿通道
增益调节输出
CE RAM 地址
71M6541D/F/G
71M6542F/G
GAIN_ADJ0
GAIN_ADJ1
GAIN_ADJ2
0x40
0x41
0x42
VA
IA
IB
VA, VB
IA
IB
在演示代码中,温度补偿由储存在每个通道的 PPMC 和 PPMC2 系数决定,由 MPU 演示代码在初始化时从
之前储存在 EEPROM 的数值设置。
为了禁用演示代码中的温度补偿,将每个 GAIN_ADJn 通道的 PPMC 和 PPMC2 设为零。为使能温度补偿,
PPMC 和 PPMC2 系数设置为与每个对应传感器通道的预期温度变动相匹配的值。
对于 VREF 补偿,线性系数 PPMC 和二次系数 PPMC2 按第 4.7.2 节 71M654x 的温度系数的介绍确定。
对外部误差源的补偿通过将与 VREF 相关的 PPMC 和与外部误差源相关的 PPMC 求和,得到该传感器通道
最终的 PPMC。同理,将与 VREF 相关的 PPMC2 值和与外部误差源相关的 PPMC2 值相加。
为了确定锰铜分流器或 CT 对 PPMC 和 PPMC2 系数的影响,设计者必须通过分流器或 CT 的数据资料获得
其温度系数,或者通过实验室测量获得。设计者必须考虑批量生产元件的差异,确保产品在生产过程中满
足其精度要求。
98
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
4.7.4
VREF温度补偿,使用远端传感器
本节讨论将电流分流器传感器与 Teridian 的 71M6x01 远端传感器配合使用的电表设计中的温度补偿,如图
36 和图 38 所示。
任何直接连接至 71M654x 的传感器受 71M654x 中 VREF 随温度变化引起的电压变动的影响。另一方面,
连接至 71M6x01 远端传感器的传感器受 71M6x01 中 VREF 的影响。71M654x 和 71M6x01 中的 VREF 可
利用温度的二阶多项式函数进行数字补偿。71M654x 和 71M6x01 都具有温度传感器,用于对其 VREF 进
行温度补偿。
参见图 36 和图 38,VA 电压传感器可用于 71M6541D/F/G 和 71M6542F/G,直接连接至 71M654x。VB
电压传感器仅在 71M6542F/G 中可用,也采用直接连接。所以,这些直接连接电压传感器的精度受
71M654x 中 VREF 的影响。71M654x 还有一个分流器传感器(IA),采用直接连接,因此也受 71M654x 中
VREF 的影响。外部电流传感器及其对应信号调理电路也受温度的影响,根据要求的精度等级,它们也可
能需要补偿。最后,第二个电流传感器(IB)被 71M6x01 隔离,依赖于 71M6x01 中的 VREF,另外还有对应
的锰铜分流器阻值随温度的变化。
MPU 负责根据检测到的温度计算每个传感器通道所需的补偿值。Teridian 提供演示代码,实现如下所示的
GAIN_ADJn 补偿方程。得到的 GAIN_ADJn 值被 MPU 储存在三个 CE RAM 地址 GAIN_ADJ0-GAIN_ADJ2
(CE RAM 0x40-0x42) 。 演 示 代 码 提 供 了 合 适 的 温 度 补 偿 方 法 , 但 利 用 片 上 温 度 传 感 器 和 CE RAM
GAIN_ADJn 储存地址,可在 MPU 固件中采用其它方法。演示代码维护三组独立的 PPMC 和 PPMC2 系统,
并根据检测到的温度用下式计算三个独立的 GAIN_ADJn 值:
GAIN _ ADJ = 16385 +
10 ⋅ TEMP _ X ⋅ PPMC
214
+
100 ⋅ TEMP _ X 2 ⋅ PPMC 2
2 23
式中,TEMP_X 为相对于标称值或校准温度的偏差,以 0.1 °C 的整数倍表示。例如,由于 71M654x 校准
(基准)温度为 22 oC,实测温度为 27 oC,所以 TEMP_X = (27-22) x 10 = 50 (十进制),表示相对于 22 oC
的偏差为+5 oC。
表 73 给出了 GAIN_ADJn 公式输出值,以及被补偿的电压或电流测量值。
•
•
•
GAIN_ADJ0 补偿 71M654x 中的 VA 和 VB (71M6542F/G)电压测量值,用于补偿 71M654x 中的 VREF。
设计者可选择把对分压电阻的补偿增加至该通道的 PPMC 和 PPMC2 系数。
GAIN_ADJ1 提供对 IA 电流通道的补偿和对 71M654x VREF 的补偿。设计者可选择把对锰铜分流器及
对应信号调理电路的补偿增加至该通道的 PPMC 和 PPMC2 系数。
GAIN_ADJ2 提供对远端连接的 IB 分流器电流传感器的补偿和对 71M654x VREF 的补偿。设计者可选
择将对连接至 71M6x01 的分流器的补偿增加至该通道的 PPMC 和 PPMC2 系数。
Rev 2
99
71M6541D/F/G 和 71M6542F/G 数据资料
表 73. GAIN_ADJn 补偿通道
增益调节输出
CE RAM 地址
71M6541D/F/G
71M6542F/G
GAIN_ADJ0
GAIN_ADJ1
GAIN_ADJ2
0x40
0x41
0x42
VA
IA
IB
VA, VB
IA
IB
在演示代码中,温度补偿由储存在 PPMC 和 PPMC2 的系数决定,MPU 演示代码在初始化时,从之前储存
在 EEPROM 的数值设置。
为了禁用演示代码中的温度补偿,将每个 GAIN_ADJn 通道的 PPMC 和 PPMC2 设为零。为使能温度补偿,
PPMC 和 PPMC2 系数设置为与对应通道的预期温度变动相匹配的值。
对于 VREF 补偿,线性系数 PPMC 和二次系数 PPMC2 按第 4.7.2 节 71M654x 的温度系数的介绍确定。关
于 71M6x01 VREF 确定 PPMC 和 PPMC2 系数的信息,请参阅 71M6xxx 数据资料。
对外部误差源的补偿通过将与 VREF 相关的 PPMC 值和与外部误差源相关的 PPMC 值求和,得到该传感器
通道最终的 PPMC 值。同理,将与 VREF 相关的 PPMC2 值和与外部误差源相关的 PPMC2 值相加。
为了确定分流器传感器对 PPMC 和 PPMC2 系数的影响,设计者必须通过分流器或 CT 的数据资料获得其温
度系数,或者通过实验室测量获得。设计者必须考虑批量生产元件的差异,确保产品在生产过程中满足其
精度要求。
4.8
连接I2C EEPROM
I2C EEPROM 或其它 I2C 兼容器件应连接至 DIO 引脚 SEGDIO2 和 SEGDIO3,如图 39 所示。
SDCK 和 SDATA 信号应该使用大约 10 kΩ 的上拉电阻拉至 V3P3D (确保工作于 BRN 模式)。I/O RAM 中
的 DIO_EEX[1:0] (I/O RAM 0x2456[7:6])字段必须设为 01,以便将 DIO 引脚 SEGDIO2 和 SEGDIO3 转换至
硬件 I2C 引脚 SDCK 和 SDATA。
100
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
10 kΩ
V3P3D
10 kΩ
EEPROM
SEGDIO2/SDCK
SDCK
SEGDIO3/SDATA
SDATA
71M654x
图 39. I2C EEPROM 连接
4.9
连接 3 线EEPROM
μWire EEPROM 和其它兼容器件应连接至 DIO 引脚 SEGDIO2/SDCK 和 SEGDIO3/SDATA,如第 2.5.9 节
EEPROM 接口所述。
4.10
UART0 (TX/RX)
UART0 RX 引脚应由 10kΩ 电阻拉低,另外由 100pF 陶瓷电容保护,如图 40 所示。
71M654x
RX
100 pF 10 k Ω
TX
RX
TX
图 40. UART0 连接
4.11
光接口(UART1)
OPT_TX 和 OPT_RX 引脚可用于普通的串行接口(例如,连接一个 RS_232 收发器),或者用于直接控制光
元件(例如,红外二极管和光电晶体管实现 FLAG 接口)。图 41 所示为 UART1 的基本连接。I/O RAM 控制
字段 OPT_TXE (I/O RAM 0x2456[3:2])设为 00 时,OPT_TX 引脚有效。
OPT_TX 和 OPT_RX 引脚的极性可分别由配置位 OPT_TXINV (I/O RAM 0x2456[0])和 OPT_RXINV (I/O RAM
0x2457[1])控制翻转。
系统电源供电时,OPT_TX 可以使能 38 kHz 调制功能。BRN 模式下调制功能不可用。OPT_TXMOD 位(I/O
RAM 0x2456[1])使能调制。占空比由 OPT_FDC[1:0] (I/O RAM 0x2457[5:4])控制,可选择 50%、25%、12.5%
和 6.25%占空比。6.25%占空比意味着 OPT_TX 在 6.25%周期内为低电平。OPT_RX 引脚采用数字信号门
限。接收调制光信号时,它可能需要一个模拟滤波器。
调制时,光发射器工作电流比标称值高,使其延长光通路距离。
Rev 2
101
71M6541D/F/G 和 71M6542F/G 数据资料
如果希望工作于 BRN 模式,外部元件应连接至 V3P3D。然而,建议将电流限制为几个 mA。
V3P3SYS
R1
71M654x
OPT_RX
100 pF
10 kΩ
Phototransistor
V3P3SYS
R2
LED
OPT_TX
图 41. 光元件连接
4.12
连接复位引脚
即使正常工作的电表不需要复位开关,开发时提供一个复位按钮非常有用,如图 42 左侧所示。RESET 信
号可源于 V3P3SYS (MSN 模式)、V3P3D (MSN 和 BRN 模式)或 VBAT (所有模式,如果有电池),或者是
这些供电电源的组合,取决于具体应用。
对于生产型电表,RESET 引脚应由外部元件保护,如图 42 右侧所示。R1 应在 100Ω 范围之内,安
装在尽量靠近 IC 的位置。
由于 71M6541D/F/G 和 71M6542F/G 产生自身的上电复位,所以只有测试和开发时才需要复位按钮或电路,
如图 42 所示。
VBAT/
V3P3D
V3P3D
R2
71M6533
71M654x
71M654x
1kΩ
Reset
Switch
RESET
RESET
0.1µF
10kΩ
R1
100Ω
R1
GNDD
DGND
GNDD
图 42. RESET 引脚外部电路:按钮(左侧)、生产电路(右侧)
4.13
连接仿真器端口
即使不使用仿真器,也应该使用一个对地短路小电容(22pF),用于 EMI 防护,如图 43 所示。成品板应使
ICE_E 引脚连接至地。
102
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
LCD Segments
(optional)
V3P3D
71M654x
ICE_E
62 Ω
E_RST
62 Ω
E_RXT
E_TCLK
62 Ω
22 pF 22 pF 22 pF
图 43. 仿真器接口的外部电路
Rev 2
103
71M6541D/F/G 和 71M6542F/G 数据资料
4.14
闪存编程
4.14.1 通过ICE端口编程闪存
利用在线仿真器或 Teridian 提供的 FLASH 编程模块(TFP-2),将操作或测试程序载入 FLASH。FLASH 编
程采用 E_RST、E_RXTX 和 E_TCLK 引脚。
4.14.2 通过SPI端口编程闪存
通过 SPI 端口可擦除、读和编程 FLASH,详细说明请参见第 2.5.10 节 SPI 从机端口。
4.15
MPU固件库
Teridian 提供的演示用 C 程序(源代码)包括了第 4 章应用信息提及的所有相关 MPU 函数。这些代码作为
71M6541D/F/G 和 71M6542F/G 演示工具包的一部分提供。随演示工具包提供预编程的演示固件,安装在
实验样品演示板上。演示板有助于快速、有效地评估 IC,同时无需编写固件或提供仿真器(ICE)。
4.16
晶振
71M6541D/F/G 和 71M6542F/G 的振荡器为标准 32.768 kHz 钟表晶振。经过特殊设计振荡器电路,可处
理此类晶振,同时兼容其高阻抗和有限功率处理能力。振荡器功耗非常低,有助于延长 VBAT_RTC 电池的
寿命。
电路板布局使 XIN 至 XOUT 的电容最小化,需要的电池电流很小。良好的布局使 XIN 和 XOUT 彼此隔离,
并且与 LCD 和数字信号隔离。
由于振荡器为自偏压,所以不能在晶振上连接外部电阻。
4.17
电表校准
Teridian 71M654x 电能表器件安装在电表系统后,必须对其校准。完整的校准包括以下内容:
•
•
建立基准温度(例如,典型为 22 °C)。
在基准温度(例如,典型为 22 °C)下校准计量电路,即校准电流传感器、分压和信号调理元件以及内部基
准电压(VREF)的容差。
•
利用 RTCA_ADJ[7:0] I/O RAM 寄存器(I/O RAM 0x2504)校准振荡器频率。
可利用 CE 的增益和相位调节系数校准计量部分。增益调节用于补偿信号调理使用的元件的容差,尤其是
电阻性元件。相位调整用于补偿电流传感器或无功功率引起的相位漂移。
由于 MPU 固件的灵活性,能够实现任意校准方法,例如基于能量或电流和电压进行校准。还可能实现分段
校准(取决于电流范围)。
71M6541D/F/G 和 71M6542F/G 支持常见的工业标准校准技术,例如单点(仅限能量)、多点(能量、Vrms、
Irms)和自动校准。
Teridian 提供一份校准电子表格文件,以方便校准过程。请联系当地的 Teridian 代表处,索取最新的
71M654x 校准电子表格文件。
104
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5
固件接口
5.1
I/O RAM映射—按功能排序
表 74 和表 75 中,无效(U)位和保留(R)位以浅灰色阴影表示。无效位用“U”表示。无效位没有物理存储单元,对其写操作没任何影响,读取时总是返
回 0。保留位用“R”表示,只能写 0。对保留位写入非 0 值,可能会产生负作用,必须避免。非易失位以深灰色阴影表示。如果系统有电池连接至
VBAT 引脚,非易失位在主电源故障期间不会丢失。
表 74 中按地址顺序列出 I/O RAM 位置,方便 MPU 读取(例如,按照验证内容的顺序)。这些 I/O RAM 位置通常仅在启动时更改。表 74 所列地址是
表 75 所列地址的替代选择,在本文通篇中都使用表 75 所列地址。例如,EQU[2:0]可在地址 I/O RAM 0x2000[7:5]或地址 I/O RAM 0x2106[7:5]操作。
表 74. I/O RAM 映射—按功能排序,基本配置
名称
地址
CE6
CE5
CE4
CE3
CE2
CE1
CE0
RCE0
RTMUX
保留
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
TEMP
LCD0
LCD1
LCD2
LCD_MAP6
LCD_MAP5
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
200A
200B
200C
200D
200E
200F
2010
2011
2012
2013
2014
2015
Rev 2
第7位
第6位
EQU[2:0]
U
第5位
第4位
第3位
第2位
第1位
第0位
U
CHOP_E[1:0]
RTM_E
CE_E
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
U
U
CE_LCTN[5:0]
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
R
R
DIFFB_E
DIFFA_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
CHOPR[1:0]
R
R
RMT_E
R
R
R
U
TMUXRB[2:0]
U
TMUXRA[2:0]
U
U
R
U
U
U
U
U
MUX_DIV[3:0]
MUX10_SEL
MUX9_SEL
MUX8_SEL
MUX7_SEL
MUX6_SEL
MUX5_SEL
MUX4_SEL
MUX3_SEL
MUX2_SEL
MUX1_SEL
MUX0_SEL
TEMP_BSEL
TEMP_PWR
OSC_COMP
TEMP_BAT TBYTE_BUSY
TEMP_PER[2:0]
LCD_E
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_CLK[1:0]
LCD_VMODE[1:0]
LCD_BLNKMAP23[5:0]
LCD_BAT
R
LCD_BLNKMAP22[5:0]
LCD_MAP[55:48]
LCD_MAP[47:40]
105
71M6541D/F/G and 71M6542F/G Data Sheet
名称
地址
LCD_MAP4
LCD_MAP3
LCD_MAP2
LCD_MAP1
LCD_MAP0
DIO_R5
DIO_R4
DIO_R3
DIO_R2
DIO_R1
DIO_R0
DIO0
DIO1
DIO2
INT1_E
INT2_E
WAKE_E
SFMM
SFMS
2016
2017
2018
2019
201A
201B
201C
201D
201E
201F
2020
2021
2022
2023
2024
2025
2026
2080
2081
第7位
第6位
U
U
U
U
U
U
U
DIO_EEX[1:0]
DIO_PW
DIO_PV
DIO_PX
DIO_PY
EX_EEX
EX_XPULSE
EX_SPI
EX_WPULSE
第5位
第4位
第3位
第2位
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
U
U
U
DIO_R11[2:0]
U
DIO_R9[2:0]
U
DIO_R7[2:0]
U
DIO_R5[2:0]
U
DIO_R3[2:0]
U
U
U
OPT_TXE[1:0]
OPT_FDC[1:0]
U
OPT_RXDIS
U
U
U
U
EX_YPULSE
EX_RTCT
U
EX_RTC1M
EX_VPULSE
EW_RX
EW_PB
EW_DIO4
SFMM[7:0]*
SFMS[7:0]*
第1位
第0位
DIO_RPB[2:0]
DIO_R10[2:0]
DIO_R8[2:0]
DIO_R6[2:0]
DIO_R4[2:0]
DIO_R2[2:0]
OPT_TXMOD
OPT_RXINV
U
EX_RTC1S
OPT_TXINV
OPT_BB
U
EX_XFER
EW_DIO52†
EW_DIO55
注:
*SFMM 和 SFMS 只能通过 SPI 从端口访问。详情请参见激活 SFM (第 78 页)
†
仅限 71M6542F/G。
106
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
表 75 列出了可能需要频繁访问的位和寄存器。保留位的灰色背景较浅,非易失位的灰色背景较深。
表 75. I/O RAM 映射—按功能排序
名称
CE 和 ADC
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
CE6
CE5
CE4
CE3
CE2
CE1
CE0
RTM0
RTM0
RTM1
RTM2
RTM3
地址
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
210A
210B
210C
210D
210E
210F
2110
2111
第7位
U
第6位
第5位
MUX_DIV[3:0]
MUX9_SEL[3:0]
MUX7_SEL[3:0]
MUX5_SEL[3:0]
MUX3_SEL[3:0]
MUX1_SEL[3:0]
EQU[2:0]
U
U
U
U
R
U
R
U
DIFFB_E
U
U
U
ADC_DIV
第4位
第3位
第2位
第1位
第0位
MUX10_SEL[3:0]
MUX8_SEL[3:0]
MUX6_SEL[3:0]
MUX4_SEL[3:0]
MUX2_SEL[3:0]
MUX0_SEL[3:0]
U
CHOP_E[1:0]
RTM_E
CE_E
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
CE_LCTN[5:0]
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
DIFFA_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
U
U
U
RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
时钟发生
CKGN
2200
LCD/DIO
VREF 调节熔丝器件
TRIMT
2309
LCD/DIO
LCD0
2400
LCD1
2401
LCD2
2402
LCD_MAP6
2405
LCD_MAP5
2406
Rev 2
PLL_FAST
RESET
MPU_DIV[2:0]
TRIMT[7:0]
LCD_E
LCD_VMODE[1:0]
LCD_BAT
R
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_CLK[1:0]
107
71M6541D/F/G and 71M6542F/G Data Sheet
名称
地址
LCD_MAP4
LCD_MAP3
LCD_MAP2
LCD_MAP1
LCD_MAP0
LCD4
LCD_DAC
SEGDIO0
…
SEGDIO15
SEGDIO16
…
SEGDIO45
SEGDIO46
…
SEGDIO50
SEGDIO51
…
SEGDIO55
2407
2408
2409
240A
240B
240C
240D
2410
…
241F
2420
…
243D
243E
…
2442
2443
…
2447
DIO_R5
DIO_R4
DIO_R3
DIO_R2
DIO_R1
DIO_R0
DIO0
DIO1
DIO2
NV BITS
保留
保留
TMUX
108
2450
2451
2452
2453
2454
2455
2456
2457
2458
第7位
U
U
U
U
U
U
U
U
U
U
U
U
U
U
第6位
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
DIO_EEX[1:0]
DIO_PW
DIO_PV
DIO_PX
DIO_PY
第5位
U
U
第4位
第3位
第2位
第1位
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
U
U
LCD_RST
LCD_BLANK
LCD_DAC[4:0]
LCD_SEG0[5:0]
…
LCD_SEG15[5:0]
LCD_SEGDIO16[5:0]
…
LCD_SEGDIO45[5:0]
LCD_SEG46[5:0]
…
LCD_SEG50[5:0]
LCD_SEGDIO51[5:0]
…
LCD_SEGDIO55[5:0]
U
U
DIO_R11[2:0]
DIO_R9[2:0]
DIO_R7[2:0]
DIO_R5[2:0]
DIO_R3[2:0]
U
U
OPT_FDC[1:0]
U
U
U
U
U
U
U
U
OPT_TXE[1:0]
U
OPT_RXDIS
U
U
DIO_RPB[2:0]
DIO_R10[2:0]
DIO_R8[2:0]
DIO_R6[2:0]
DIO_R4[2:0]
DIO_R2[2:0]
OPT_TXMOD
OPT_RXINV
U
第0位
LCD_ON
OPT_TXINV
OPT_BB
U
2500
U
U
U
U
R
R
R
R
2501
U
U
U
U
R
U
U
U
U
U
2502
TMUX[5:0]
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
名称
地址
TMUX2
2503
RTC1
2504
71M6x01 接口
REMOTE2
2602
REMOTE1
2603
RBITS
INT1_E
2700
INT2_E
2701
SECURE
2702
Analog0
2704
VERSION
2706
INTBITS
2707
FLAG0
SFR E8
FLAG1
SFR F8
STAT
SFR F9
REMOTE0 SFR FC
SPI1
SFR FD
SPI0
2708
RCE0
2709
RTMUX
270A
INFO_PG
270B
DIO3
270C
NV RAM 和 RTC
2800NVRAMxx
287F
WAKE
2880
STEMP1
2881
STEMP0
2882
BSENSE
2885
LKPADDR
2887
LKPDATA
2888
LKPCTRL
2889
RTC0
2890
Rev 2
第7位
第6位
第5位
U
U
U
U
第4位
第3位
第2位
第1位
第0位
EX_RTC1M
U
FLSH_RDE
EX_RTC1S
U
FLSH_WRE
SPARE[2:0]
EX_XFER
U
R
INT2
IE_RTC1M
U
INT1
IE_RTC1S
U
VSTAT[2:0]
INT0
IE_XFER
PB_STATE
R
U
U
R
TMUXRA[2:0]
U
U
INFO_PG
U
U
U
U
U
U
LKP_RD
U
LKP_WR
U
TMUX2[4:0]
RTCA_ADJ[6:0]
RMT_RD[15:8]
RMT_RD[7:0]
EX_EEX
EX_SPI
VREF_CAL
U
IE_EEX
IE_SPI
U
EX_XPULSE EX_YPULSE
EX_WPULSE EX_VPULSE
FLSH_UNLOCK[3:0]
VREF_DIS
PRE_E
INT6
IE_XPULSE
IE_WPULSE
U
PERR_RD
CHOPR[1:0]
U
U
U
R
U
U
INT5
IE_YPULSE
IE_VPULSE
U
PERR_WR
R
R
U
PORT_E
EX_RTCT
U
U
U
R
ADC_E
BCURR
VERSION[7:0]
INT4
INT3
IE_RTCT
U
U
U
PLL_OK
U
RCMD[4:0]
SPI_CMD[7:0]
SPI_STAT[7:0]
R
RMT_E
R
U
U
U
SPI_E
SPI_SAFE
R
NVRAM[0] – NVRAM[7F] – Direct Access
STEMP[2:0]
LKPAUTOI
U
RTC_WR
U
RTC_RD
U
U
WAKE_TMR[7:0]
STEMP[10:3]
U
U
BSENSE[7:0]
LKPADDR[6:0]
LKPDAT[7:0]
U
U
RTC_FAIL
U
109
71M6541D/F/G and 71M6542F/G Data Sheet
名称
RTC2
RTC3
RTC4
RTC5
RTC6
RTC7
RTC8
RTC9
RTC10
RTC11
RTC12
RTC13
RTC14
TEMP
WF1
WF2
MISC
WAKE_E
WDRST
MPU 端口
P3
P2
P1
P0
FLASH
ERASE
FLSHCTL
PGADR
2
IC
EEDATA
EECTRL
地址
2892
2893
2894
2895
2896
2897
2898
2899
289B
289C
289D
289E
289F
28A0
28B0
28B1
28B2
28B3
28B4
第7位
SFR 9E
SFR 9F
第5位
第4位
第3位
第2位
第1位
第0位
RTC_SBSC[7:0]
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
U
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
U
U
RTC_YR[7:0]
U
U
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
U
U
U
U
TEMP_BSEL TEMP_PWR
WF_CSTART
WF_RST
U
U
SLEEP
LCD_ONLY
U
U
WD_RST
TEMP_START
SFR B0
SFR A0
SFR 90
SFR 80
SFR 94
SFR B2
SFR B7
第6位
U
OSC_COMP
WF_RSTBIT
WF_TMR
WAKE_ARM
U
U
RTC_Q[1:0]
TEMP_BAT
WF_OVF
WF_RX
EW_RX
U
RTC_TMIN[5:0]
RTC_THR[4:0]
TBYTE_BUSY
TEMP_PER[2:0]
WF_ERST
WF_BADVDD
WF_PB
WF_DIO4
WF_DIO52
WF_DIO55
EW_PB
U
DIO_DIR[15:12]
DIO_DIR[11:8]
DIO_DIR[7:4]
DIO_DIR[3:0]
PREBOOT
SECURE
EW_DIO4
U
EW_DIO52 †
U
EW_DIO55
U
DIO[15:12]
DIO[11:8]
DIO[7:4]
DIO[3:0]
FLSH_ERASE[7:0]
U
U
FLSH_PEND
FLSH_PGADR[5:0]
FLSH_PSTWR FLSH_MEEN
U
FLSH_PWE
U
EEDATA[7:0]
EECTRL[7:0]
†
仅限 71M6542F/G。
110
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5.2
I/O RAM映射—按字母排序
表 76 按字母顺序列出了 I/O RAM 和寄存器。
可写位(在方向栏中用 W 表示)由 MPU 写入配置 RAM。通常情况下,典型应用是:由 MPU 从 FLASH 复制到配置 RAM。部分更常用的操作位被映
射至 MPU SFR 存储器空间。其它位被映射至地址空间 0x2XXX。MPU 读取 R (读)位。复位和唤醒栏分别说明复位和唤醒时的默认值。“-”意味着
该位为只读或由 NV 电源供电,不进行初始化。读取“只写位”时返回 0。
灰色阴影部分为非易失(电池供电)。
表 76. I/O RAM 映射—按功能排序
名称
位置
复位 唤醒 方向 说明
ADC_E
2704[4]
0
0
ADC_DIV
2200[5]
0
0
R/W 使能 ADC 和 VREF。禁用时,减小偏置电流。
ADC_DIV 控制 ADC 和 FIR 时钟的速率。
ADC_DIV 设置决定 MCK 是被 4 或 8 除:
0 = MCK/4
1 = MCK/8
R/W 产生的 ADC 和 FIR 时钟如下所示。
PLL_FAST = 0
MCK
6.291456MHz
ADC_DIV = 0
1.572864MHz
ADC_DIV = 1
0.786432MHz
PLL_FAST = 1
19.660800MHz
4.9152MHz
2.4576MHz
R/W 将 100μA 负载连接至 TEMP_BSEL 所选的电池。
2704[3]
0
0
2885[7:0]
–
–
2106[0]
0
0
R/W CE 使能。
CE_LCTN[5:0]
CHIP_ID[15:8]
CHIP_ID[7:0]
2109[5:0]
2300[7:0]
2301[7:0]
31
0
0
31
0
0
CHOP_E[1:0]
2106[3:2]
0
0
R/W CE 程序位置。CE 程序的起始地址为 1024*CE_LCTN。
R
这些字节包含芯片标识。
R
使能基准带隙电路的斩波功能。CHOP 值在 MUXSYNC 的上升沿根据 CHOP_E
的设定而改变:
R/W
00 = 自动切换 1 01 = 正极性 10 = 反极性 11 = 自动切换
1
累积周期的最后 mux sync 沿除外(不切换极性)。
BCURR
BSENSE[7:0]
CE_E
Rev 2
R
电池测量结果。参见第 2.5.6 节 71M654x 电池检测器。
111
71M6541D/F/G and 71M6542F/G Data Sheet
名称
CHOPR[1:0]
DIFFA_E
DIFFB_E
DIO_R2[2:0]
DIO_R3[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_RPB[2:0]
DIO_DIR[15:12]
DIO_DIR[11:8]
DIO_DIR[7:4]
DIO_DIR[3:0]
DIO[15:12]
DIO[11:8]
DIO[7:4]
DIO[3:0]
位置
复位 唤醒 方向 说明
2709[7:6]
00
00
用于远端传感器的 CHOP 设置。
00 = 自动斩波。每个复用帧变化。
R/W 01 = 正
10 = 负
11 = 自动斩波。同 00。
210C[4]
0
0
R/W 使能 IA 电流输入(IAP-IAN)的差分配置。
210C[5]
2455[2:0]
2455[6:4]
2454[2:0]
2454[6:4]
2453[2:0]
2453[6:4]
2452[2:0]
2452[6:4]
2451[2:0]
2451[6:4]
2450[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W 使能 IB 电流输入(IBP-IBN)的差分配置。
将 PB 和专用 I/O 引脚 DIO2 至 DIO11 连接至内部资源。如果多个输入连接至相
同源,下方的 MULTIPLE 栏制定如何组合。
DIO_Rx
–
R/W
资源
MULTIPLE
0
无
1
保留
OR
2
T0 (定时器 0 时钟或选通)
OR
3
T1 (定时器 1 时钟或选通)
OR
4
IO 中断(int0)
OR
5
IO 中断(int1)
OR
–
F
F
设置前 16 个 DIO 引脚的方向,1 表示输出。如果该引脚未配置为 I/O,则忽略。
关于 SEGDIO0 和 SEGDIO1 的特殊选项,请参见 DIO_PV 和 DIO_PW 。关于
R/W
SEGDIO2 和 SEGDIO3 的特殊选项,请参见 DIO_EEX。注意,DIO15 以上的引
脚方向由 SEGDIOx[1]设置。参见 PORT_E 避免上电毛刺。
SFR B0[3:0]
SFR A0[3:0] SFR F
90[3:0] SFR 80[3:0]
F
设置前 16 个 DIO 引脚的数值,配置为 LCD 的引脚读取时为 0。写入时,更改配
R/W 置为输出的引脚的数据,配置为 LCD 或输入的引脚忽略写操作。注意,DIO15
以上的引脚数据由 SEGDIOx[0]设置。
SFR B0[7:4]
SFR A0[7:4]
SFR 90[7:4]
SFR 80[7:4]
置位时,将引脚 SEGDIO3/SEGDIO2 转换为带外部 EEPROM 的接口。
SEGDIO2 变为 SDCK,SEGDIO3 变为双向 SDATA,但是只有 LCD_MAP[2] 和
LCD_MAP[3]清除时,该功能可用。
DIO_EEX[1:0]
DIO_EEX[1:0]
112
2456[7:6]
0
–
R/W
功能
00
禁用 EEPROM 接口
01
2 线 EEPROM 接口
10
3 线 EEPROM 接口
11
3 线 EEPROM 接口,带独立的 DO (DIO3)和 DI (DIO8)引脚。
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
名称
位置
复位 唤醒 方向 说明
DIO_PV
2457[6]
0
–
R/W 如果 LCD_MAP[1] = 0,使 VARPULSE 在引脚 SEGDIO1 输出。
DIO_PW
2457[7]
0
–
R/W 如果 LCD_MAP[0] = 0,使 VARPULSE 在引脚 SEGDIO1 输出。
DIO_PX
2458[7]
0
–
R/W 如果 LCD_MAP[6] = 0,使 XPULSE 在引脚 SEGDIO6 输出。
DIO_PY
2458[6]
0
–
R/W 如果 LCD_MAP[7] = 0,使 YPULSE 在引脚 SEGDIO7 输出。
EEDATA[7:0]
SFR 9E
0
0
R/W 串行 EEPROM 接口数据。
串行 EEPROM 接口控制。
EECTRL[7:0]
SFR 9F
0
0
R/W
状态
位
名称
读/写
复位
状态
7
6
ERROR
BUSY
R
R
0
0
5
RX_ACK
R
1
极性 说明
正
正
正
接收到合法命令后为 1。
串行数据总线忙时为 1。
1 表示 EEPROM 发送了 ACK 位。
指定计量公式。
EQU
0
EQU[2:0]
2106[7:5]
0
0
R/W
1
2†
Watt & VAR 公式
(WSUM/VARSUM)
VA*IA
1 器件,2 表,1Ф
VA*(IA-IB)/2
1 器件,3 表,1Ф
VA*IA + VB*IB
2 器件,3 表,3Ф Δ
用于计算能量/电流的输入
W0SUM/
W1SUM/
I0SQ
VAR0SUM
VAR1SUM SUM
I1SQ
SUM
VA*IA
VA*IB1
IA
IB1
VA*(IA-IB)/2
–
IA-IB
IB
VA*IA
VB*IB
IA
IB
注:
1. 可选,IB 可用于测量零线电流。
†
仅限 71M6542F/G。
Rev 2
113
71M6541D/F/G and 71M6542F/G Data Sheet
名称
位置
复位 唤醒 方向 说明
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
2700[0]
2700[1]
2700[2]
2700[3]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
0
0
中断使能位。这些位使能 XFER_BUSY、RTC_1SEC 等。注意,如果这些中断位
R/W 中某一项被使能,其对应的 8051 EX 使能位也应该置位。详情参见第 2.4.8 节中
断。
EW_DIO4
28B3[2]
0
–
R/W
连接 SEGDIO52 至 WAKE 逻辑,允许 SEGDIO52 上升沿唤醒器件。SEGDIO52
R/W 配置为数字输入时,该位无效。
SEGDIO52 引脚仅在 71M6542F/G 中可用。
连接 SEGDIO4 至 WAKE 逻辑,允许 SEGDIO4 上升沿唤醒器件。DIO4 配置为
数字输入时,该位无效。
EW_DIO52
28B3[1]
0
–
EW_DIO55
28B3[0]
0
–
R/W
连接 SEGDIO55 至 WAKE 逻辑控制,允许 SEGDIO55 上升沿唤醒器件。
EGDIO55 配置为数字输入时,该位无效。
EW_PB
28B3[3]
0
–
R/W
连接 PB 至 WAKE 逻辑控制,允许 PB 上升沿唤醒器件。PB 由硬件配置为输入,
软件无法修改。
EW_RX
28B3[4]
0
–
R/W
210C[2:1]
0
0
FIR_LEN[1:0]
114
连接 RX 至 WAKE 逻辑控制,允许 RX 上升沿唤醒器件。去抖信息请参见第 87
页 WAKE 说明。
ADC 采样周期的 FIR 滤波器长度。
PLL_FAST = 1:
FIR_LEN[1:0]
ADC 周期
00
141
01
288
10
384
PLL_FAST
=
0:
R/W
FIR_LEN[1:0]
ADC 周期
00
135
01
276
10
Not Allowed
ADC LSB 大小和满幅值取决于 FIR_LEN[1:0]设置。请参见第 149 页第 6.4.15 节
ADC 转换器。
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
名称
FLSH_ERASE[7:0]
位置
SFR 94[7:0]
复位 唤醒 方向 说明
0
0
W
FLASH 擦除启动
FLSH_ERASE 用于发起 FLASH 整体擦除或 FLASH 页擦除。为了启用相应的擦除
过程,FLSH_ERASE 需要特定的命令字。
(默认 = 0x00).
0x55 = 发起 FLASH 页擦除。之前必须向 FLSH_PGADR[5:0] (SFR 0xB7[7:2])写
入要擦除的页。
0xAA = 发起 FLASH 整体擦除。之前必须向 FLSH_MEEN 写 1,同时 ICE 端口必
须使能。
向 FLSH_ERASE 写其它任意命令字均无效。
FLSH_MEEN
SFR B2[1]
0
0
W
整体擦除使能
0 = 禁用整体擦除(默认)。
1 = 使能整体擦除。
必须针对每次新整体擦除重写。
FLSH_PEND
SFR B2[3]
0
0
R
表示一次写 FLASH 被挂起(写操作未完成)。后续的 FLASH 写操作被忽略。因此
用户必须判断上次写操作的状态,然后决定本次写操作是否需要等待。
W
FLASH 页擦除地址
FLSH_PGADR[5:0] — 页擦除中被擦除的 FLASH 页地址(页 0 至 63)。(默认=
0x00)。
必须针对每次新页擦除重写。
FLSH_PGADR[5:0]
FLSH_PSTWR
SFR B7[7:2]
0
0
SFR B2[2]
0
0
使能定时写 FLASH。为 1 时,如果 CE_E = 1,写 FLASH 请求储存到一个单位深
R/W 度的 FIFO 中,等待 CE_BUSY 变低时执行。可通过读 FLSH_PEND 确定此 FIFO
的状态。如果 FLSH_PSTWR = 0 或如果 CE_E = 0,立即执行写 FLASH 操作。
程序写使能
0 = MOVX 命令针对外部 RAM 空间,常规工作(默认)。
R/W
1 = MOVX @DPTR,A 将 A 移至外部程序空间(Flash) @ DPTR。
该位在每个字节写入 FLASH 后自动复位。使能中断时,禁止该位写操作。
FLSH_PWE
SFR B2[0]
0
0
FLSH_RDE
2702[2]
–
–
2702[7:4]
0
0
2702[1]
–
–
FLSH_UNLOCK[3:0]
FLSH_WRE
Rev 2
R
表示 FLASH 通过 ICE 或 SPI 接口读取。FLSH_RDE = (!SECURE)。
R/W 必须为 2 才能允许 FLASH 更改,更多详情参见 FLASH 安全说明。
R
表示 FLASH 通过 ICE 或 SPI 接口写入。
115
71M6541D/F/G and 71M6542F/G Data Sheet
名称
位置
复位 唤醒 方向 说明
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR E8[0]
SFR E8[1]
SFR E8[2]
SFR E8[4]
SFR F8[7]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[4]
SFR F8[3]
0
0
INTBITS
2707[6:0]
–
–
LCD_ALLCOM
2400[3]
0
–
R/W 将 SEG/COM 位配置为 COM。不影响 LCD_MAP 位为 0 的引脚。
LCD_BAT
2402[7]
0
–
R/W
任何模式下,VBAT 为 LCD 供电。注意:此设置会使 MSN 模式下也消耗电池电
能。
2401[5:0]
2402[5:0]
0
–
R/W
连接至 SEG23 和 SEG22 的段闪烁控制,1 表示“闪烁”。最高有效位对应
COM5,最低有效位对应 COM0。
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
用于中断 2 和 6 的中断标识。这些标识监测 int6 和 int2 中断源(MPU 核心的外部
中断)。这些标识由硬件置位,必须由软件清除。IEX2 (SFR 0xC0[1])和 IEX6 (SFR
R/W
0xC0[5])中断标识由 MPU 内核响应中断后自动清除。SFR E8 和 SFR F8 必须进
行字节清除,即向它们对应的位写 0、并向其它非清零位写 1 清除。
R
中断输入。MPU 可读取这些位,检查外部中断 INT0~INT6 的输入。这些位没有
任何存储器,主要用于调试。
设置 LCD 时钟频率,注意:fw = 32768Hz
LCD_CLK
LCD_CLK[1:0]
2400[1:0]
0
–
R/W
00
01
LCD_DAC[4:0]
LCD_E
116
LCD 时钟频率
fW
= 64 Hz
29
fW
= 128 Hz
28
LCD_CLK
10
11
LCD 时钟频率
fW
= 256 Hz
27
fW
= 512 Hz
26
240D[4:0]
0
–
LCD 对比度调节 DAC。该 DAC 控制 VLCD 电压,输出范围为 2.5V 至 5V。
VLCD 电压为:
R/W
VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31
所以,DAC 的 LSB 为 80.6mV。最大 DAC 输出电压受限于 V3P3SYS、VBAT,
以及 LCD_BSTE 是否置位。
2400[7]
0
–
R/W
使能 LCD 显示。禁用时,VLC2、VLC1、VLC0、COM 和 SEG (如果其
LCD_MAP 位为 1)均为 GND 电位。
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
名称
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
位置
2405[7:0]
2406[7:0]
2407[7:0]
2408[7:0]
2409[7:0]
240A[7:0]
240B[7:0]
复位 唤醒 方向 说明
0
0
0
0
0
0
0
–
–
–
–
–
–
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
使能 SEGDIO 引脚的 LCD 段驱动器模式。LCD_MAP[50:48]位为 0 时,SEG48
至 SEG50 只能配置成内部上拉输入。此外,注意,SEG48 至 SEG50 与在线仿
真器信号复用。ICE_E 引脚为高电平时,ICE 接口使能,SEG48 至 SEG50 分别
为 E_RXTX、E_TCLK 和 E_RST。
选择 LCD 偏压和复用模式。
LCD_MODE[2:0]
2400[6:4]
0
–
R/W
LCD_MODE
输出
LCD_MODE
输出
000
4 COM,1/3 偏
100
静态显示
001
3 COM,1/3 偏压
101
5 COM,1/3 偏压
010
2 COM,½偏压
110
6 COM,1/3 偏压
011
3COM,½偏压
R/W 点亮或关闭所有 LCD_MAP 配置成的 LCD 段,不会改变 LCD 数据。如果两位均
R/W 被置位,LCD 显示全亮。
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
–
LCD_ONLY
28B2[6]
0
0
W
将 IC 置于休眠模式,但 LCD 显示仍然有效。如果系统电源供电,则忽略。唤醒
定时器超时、特定 DIO 引脚变高或系统电源恢复时唤醒。参见第 3.2 节电池模
式。
LCD_RST
240C[2]
0
–
R/W
清除 LCD 数据的所有位。这些位影响被配置为 LCD 驱动器的 SEGDIO 引脚,该
位不自动清除。
2410[5:0] to
241F[5:0]
0
–
R/W SEG0 至 SEG15 的 SEG 数据。这些引脚的 DIO 数据位于 SFR 空间。
2420[5:0] to
243D[5:0]
0
–
R/W
SEGDIO16 至 SEGDIO45 的 SEG 和 DIO 数据。如果配置为 DIO,第 1 位为方向
(1 为输出,0 为输入),第 0 位为数据,其它位忽略。
243E[5:0] to
2442[5:0]
0
–
R/W
SEG46 至 SEG50 的 SEG 数据,这些引脚不可配置为 DIO。SEG47 和 SEG46
分别对应 TMUXOUT 和 TMUXOUT2 引脚。
–
SEGDIO51 至 SEGDIO55 的 SEG 和 DIO 数据。如果配置为 DIO,第 1 位为方向
R/W (1 为输出,0 为输入),第 0 位为数据,其它位忽略。
SEGDIO52 至 SEDIO54 仅在 71M6542F/G 可用。
LCD_SEG0[5:0]
to
LCD_SEG15[5:0]
LCD_SEGDIO16[5:0]
to
LCD_SEGDIO45[5:0]
LCD_SEG46[5:0]
to
LCD_SEG50[5:0]
LCD_SEGDIO51[5:0]
to
LCD_SEGDIO55[5:0]
Rev 2
2443[5:0] to
2447[5:0]
0
117
71M6541D/F/G and 71M6542F/G Data Sheet
名称
位置
复位 唤醒 方向 说明
指定 VLCD 来源,V3P3L 的定义请参见第 2.5.8.4 节。
LCD_VMODE
LCD_VMODE[1:0]
LCD_Y
LKPADDR[6:0]
LKPAUTOI
LKPDAT[7:0]
LKP_RD
LKP_WR
2401[7:6]
00
00
R/W
说明
11
外部 VLCD
10
使能 LCD 升压和 LCD DAC
01
使能 LCD DAC
00
无升压和 DAC,VLCD=V3P3L
2400[2]
0
–
2887[6:0]
0
0
LCD 闪烁频率(如果禁用闪烁则忽略)。
1 = 1Hz, 0 = 0.5Hz
R/W RTC 查找 RAM 的读/写地址。
2887[7]
0
0
R/W
2888[7:0]
0
0
2889[1]
2889[0]
0
0
0
0
R/W RTC 查找 RAM 的读/写数据。
用于 RTC 查找 RAM 读和写的选通位。置位时,LKPADDR[6:0]字段和 LKPDAT
R/W 寄存器用于读或写操作。选通位置位时,将保持到完成操作,然后清除选通;如
R/W 果 LKPAUTOI 置位,则递增 LKPADDR[6:0]。
R/W
地址自动递增使能。置位时,LKPADDR[6:0]在 LKP_RD 或 LKP_WR 每次产生脉
冲时自动递增。递增地址可从 LKPADDR[6:0]读取。
MPU 时钟频率为:
MPU Rate = MCK Rate * 2-(2+MPU_DIV[2:0]).
MPU_DIV[2:0]
2200[2:0]
0
0
R/W MPU_DIV[2:0]的最大值为 4。基于 PLL_FAST 位和 MPU_DIV[2:0]的默认值,上
电 MPU 速率为 6.29MHz / 4 = 1.57MHz。PLL_FAST = 0 时,最小 MPU 时钟速率
为 98.3kHz。
MUX0_SEL[3:0]
2105[3:0]
0
0
R/W 选择在时隙 0 转换的 ADC 输入。
MUX1_SEL[3:0]
2105[7:4]
0
0
R/W 选择在时隙 1 转换的 ADC 输入。
MUX2_SEL[3:0]
2104[3:0]
0
0
R/W 选择在时隙 2 转换的 ADC 输入。
MUX3_SEL[3:0]
2104[7:4]
0
0
R/W 选择在时隙 3 转换的 ADC 输入。
MUX4_SEL[3:0]
2103[3:0]
0
0
R/W 选择在时隙 4 转换的 ADC 输入。
MUX5_SEL[3:0]
2103[7:4]
0
0
R/W 选择在时隙 5 转换的 ADC 输入。
MUX6_SEL[3:0]
2102[3:0]
0
0
R/W 选择在时隙 6 转换的 ADC 输入。
MUX7_SEL[3:0]
2102[7:4]
0
0
R/W 选择在时隙 7 转换的 ADC 输入。
MUX8_SEL[3:0]
2101[3:0]
0
0
R/W 选择在时隙 8 转换的 ADC 输入。
MUX9_SEL[3:0]
2101[7:4]
0
0
R/W 选择在时隙 9 转换的 ADC 输入。
MUX10_SEL[3:0]
2100[3:0]
0
0
R/W 选择在时隙 10 转换的 ADC 输入。
118
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
名称
MUX_DIV[3:0]
OPT_BB
位置
复位 唤醒 方向 说明
2100[7:4]
0
0
2457[0]
0
–
R/W MUX_DIV[3:0]为每个复用帧内 ADC 时隙的数量。最大时隙数量为 11。
将光端口的输入配置为 DIO 引脚,使其能够为位脉冲。这种情况下,DIO5 变为
R/W 第三个高速 UART。请参见第 58 页第 2.5.7 节 UART 和光接口下的“位脉冲,光
接口 UART (第三个 UART)”。
选择 OPT_TX 调制占空比。
OPT_FDC
OPT_FDC[1:0]
2457[5:4]
0
–
R/W
功能
00
50%低
01
25%低
10
12.5%低
11
6.25%低
OPT_RXDIS
2457[2]
0
–
OPT_RX 可配置为光 UART 的输入或 SEGDIO55。
OPT_RXDIS = 0 且 LCD_MAP[55] = 0:OPT_RX
R/W OPT_RXDIS = 1 且 LCD_MAP[55] = 0: DIO55
OPT_RXDIS = 0 且 LCD_MAP[55] = 1: SEG55
OPT_RXDIS = 1 且 LCD_MAP[55] = 1: SEG55
OPT_RXINV
2457[1]
0
–
R/W
为 1 时,反转 OPT_RX 比较器的结果。仅影响 UART 输入。OPT_RX 作为 DIO
输入时,该位无效。
配置 OPT_TX 输出引脚。
2456[3:2]
00
–
OPT_TXINV
2456[0]
0
–
如果 LCD_MAP[51] = 0:
00 = DIO51, 01 = OPT_TX, 10 = WPULSE, 11 = VARPULSE
如果 LCD_MAP[51] = 1:
xx = SEG51
R/W 为 1 时反转 OPT_TX。反转发生在调制之前。
OPT_TXMOD
2456[1]
0
–
R/W
OSC_COMP
28A0[5]
0
–
R/W 使能 RTC_P 和 RTC_Q 在每次温度测量时被自动更新。
PB_STATE
SFR F8[0]
0
0
R
PERR_RD
PERR_WR
SFR FC[6]
SFR FC[5]
0
0
R/W
PLL_OK
SFR F9[4]
0
0
R
OPT_TXE [1:0]
Rev 2
R/W
使能 OPT_TX 调制。OPT_TXMOD 置位时,OPT_TX 被调制。在 OPT_TXINV 造
成的任意反转之后,应用调制。
去抖后的 PB 引脚状态。
IC 将这些位置位,表示在远端传感器上检测到奇偶校验错误。这些位一旦置位,
则被记忆,直到由 MPU 清除。
表示系统倍频电路 PLL 已稳定。
119
71M6541D/F/G and 71M6542F/G Data Sheet
名称
位置
复位 唤醒 方向 说明
2200[4]
0
0
PLS_MAXWIDTH[7:0]
210A[7:0]
FF
FF
PLS_INTERVAL[7:0]
210B[7:0]
0
0
PLL_FAST
控制 PLL 和 MCK 的速率。
R/W 1 = 19.66 MHz (XTAL * 600)
0 = 6.29 MHz (XTAL * 192)
PLS_MAXWIDTH[7:0]决定最大脉宽(如果 PLS_INV=0,为负向脉冲;如果
PLS_INV=1,为正向脉冲)。最大脉宽为(2*PLS_MAXWIDTH[7:0] + 1)*TI。式中,
R/W TI 为 PLS_INTERVAL[7:0],单位为 CK_FIR 时钟周期。如果 PLS_INTERVAL[7:0]
= 0 或 PLS_MAXWIDTH[7:0] = 255,则不执行脉宽检查,输出脉冲的占空比为
50%。参见第 2.3.6.2 节 VPULSE 和 WPULSE。
PLS_INTERVAL[7:0]决定脉冲之间的间隔时间。输出脉冲之间的时间为
PLS_INTERVAL[7:0] *4,单位为 CK_FIR 时钟周期。如果 PLS_INTERVAL[7:0] =
0,不使用 FIFO,只要 CE 发出命令,则立即输出脉冲。PLS_INTERVAL[7:0]计
算如下:
PLS_INTERVAL[7:0] = Floor ( Mux frame duration in CK_FIR cycles / CE pulse updates
R/W
per Mux frame / 4 )
例如,由于编写的 71M654x CE 代码在一个积分周期内产生 6 个脉冲,使能
FIFO 时(即 PLS_INTERVAL[7:0] ≠ 0,帧持续时间为 1950 个 CK_FIR 时钟周期,
PLS_INTERVAL[7:0]应写入 Floor(1950 / 6 / 4) = 81,所以 5 个脉冲均匀分布在积
分间隔内,最后一个脉冲恰好在间隔结束之前。参见第 2.3.6.2 节 VPULSE 和
WPULSE。
PLS_INV
210C[0]
0
0
R/W
反转 WPULSE、VARPULSE、XPULSE 和 YPULSE 极性。这些脉冲通常为低电
平有效。反转时,它们变为高电平有效。
PORT_E
270C[5]
0
0
R/W
使能引脚 SEGDIO0 至 SEGDIO15 输出。上电复位后,PORT_E = 0,防止
SEGDIO0 至 SEGDIO15 引脚因上电输出的瞬间干扰脉冲。
PRE_E
2704[5]
0
0
R/W 使能 8x 前置放大器。
PREBOOT
SFRB2[7]
–
–
R
RCMD[4:0]
SFR FC[4:0]
0
0
R/W
RESET
2200[3]
0
0
W
RFLY_DIS
210C[3]
0
0
R/W
设定 IC 对 71M6x01 供电方式。置位时,电源脉冲交替驱动为高电平和低电平。
清除时,以回扫间隔驱动至高电平。
RMT_E
2709[3]
0
0
R/W
使能远端数字隔离接口,它将 IBP-IBN 引脚转换为数字平衡差分对。所以,使能
后即可将 71M6x01 远端传感器接入 71M654x 主芯片。
120
表示预引导程序有效。
MPU 向 RCMD[4:0]写非零值时,IC 向相应远端传感器发出该命令。完成命令
后,IC 清除 RCMD[4:0]。
置位后,IC 将 WF_RSTBIT 置位,然后复位。
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
名称
位置
复位 唤醒 方向 说明
RMT_RD[15:8]
RMT_RD[7:0]
RTC_FAIL
2602[7:0]
2603[7:0]
2890[4]
0
0
0
0
R/W 表示 RTC 中发生计数错误,时间不可信。该位可通过写 0 清除。
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
289B[2:0]
289C[7:0]
289D[7:2]
4
0
0
4
0
0
RTC 调节。参见第 2.5.4 节实时时钟(RTC)。
R/W 0x0FFBF ≤ RTC_P ≤ 0x10040
注:RTC_P[16:0]和 RTC_Q[1:0]组成一个 19 位有符号 RTC 调整值。
RTC_Q[1:0]
289D[1:0]
0
0
R/W
RTC 调节。参见第 2.5.4 节实时时钟(RTC)。
注:RTC_P[16:0]和 RTC_Q[1:0]组成一个 19 位有符号 RTC 调整值。
2890[6]
0
0
R/W
冻结 RTC 影子寄存器,以便 RTC 读取。读 RTC_RD 时,返回影子寄存器的状
态:0 = 更新,1 = 冻结。
RTC_SBSC[7:0]
2892[7:0]
–
–
R
RTC_TMIN[5:0]
289E[5:0]
0
–
R/W 闹铃分钟寄存器。参见下文的 RTC_THR。
RTC_THR[4:0]
289F[4:0]
0
–
R/W
2890[7]
0
0
冻结 RTC 影子寄存器,以便 MPU 写操作。RTC_WR 清除时,在下一个 RTC 时
R/W 钟(~500Hz)将影子寄存器的内容写入至 RTC 计数器。读 RTC_WR 时,只要
RTC_WR 置位,则返回 1。在 RTC 计数器实际更新之前,它将继续返回 1。
RTC_RD
RTC_WR
R
远端读请求的响应。
到下个 1 秒边界剩余的时间。LSB = 1/256 秒。
闹铃小时寄存器。RTC_MIN 等于 RTC_TMIN 且 RTC_HR 等于 RTC_THR 时,发生
RTC_T 中断。
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2893[5:0]
2894[5:0]
2895[4:0]
2896[2:0]
2897[4:0]
2898[3:0]
2899[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
RTC 接口寄存器。这些是 RTC 的年、月、日、时、分和秒参数。通过写这些寄
存器设置 RTC。00 年以及其它能够被 4 整除的年份定义为闰年。
SEC 00 to 59
MIN 00 to 59
HR
00 to 23 (00 = 午夜)
R/W
DAY 01 to 07 (01 = 周日)
DATE 01 to 31
MO
01 to 12
YR
00 to 99
对这些寄存器的每次写操作必须首先对 0x20A0 进行写操作。
RTCA_ADJ[6:0]
2504[7:0]
40
–
R/W 模拟 RTC 频率微调寄存器。
RTM_E
RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
2106[1]
210D[1:0]
210E[7:0]
210F[7:0]
2110[7:0]
2111[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
R/W 使能实时监测器。为 0 时,RTM 输出为低电平。
Rev 2
四个 RTM 监测器。每一 CE 执行周期之前,这些寄存器的值在 RTM 引脚上顺序
R/W 输出。RTM_E = 0 时,忽略 RTM 寄存器。注意,RTM0 为 10 位宽。其它 RTM
的高 2 位假定为 00。
121
71M6541D/F/G and 71M6542F/G Data Sheet
名称
位置
复位 唤醒 方向 说明
禁止擦除 0 页及 CE_LCTN[5:0]定义的 CE 代码开始地址以上部分。也禁止通过
SPI 和 ICE 端口读取 FLASH。
SFR B2[6]
0
0
R/W
28B2[7]
0
0
W
将器件置于 SLP 模式。如果有系统电源,则忽略。唤醒定时器超时、唤醒按钮被
按下或系统电源恢复时,器件唤醒。
SFR FD[7:0]
–
–
R
来自主控制器的 8 位 SPI 命令寄存器。
SPI_E
270C[4]
1
1
R/W
SPI 端口使能。使能引脚 SEGDIO36 至 SEGDIO39 的 SPI 接口。要求
LCD_MAP[36-39] = 0。
SPI_SAFE
270C[3]
0
0
R/W
将 SPI 写操作限值为 SPI_CMD 及 XRAM 中的 16 字节区域。不允许进行其它地
址写操作。
SECURE
SLEEP
SPI_CMD[7:0]
SPI_STAT[7:0]
2708[7:0]
0
0
R
SPI_STAT 前一次 SPI 通信的状态结果。
第 7 位:就绪错误:71M654x 未准备好按照前一命令读或写。
第 6 位:读数据奇偶性:该位是前一命令从 71M654x 读取的全部字节的奇偶校
验。不包括 SPI_STAT 字节。
第 5 位:写数据奇偶性:该位是前一命令写入 71M654x 的全部字节的奇偶校验。
它包括 CMD 和 ADDR 字节。
第 4 至 2 位:字节数的最低 3 位。不包括 ADDR 和 CMD 字节。1、2 和 3 字节指
令返回 111。
第 1 位:SPIFLASH 模式:TEST 引脚为零时,该位为零。
第 0 位:SPIFLASH 模式就绪:用于 SPIFLASH 模式。表示 FLASH 已准备好接
收另一条写指令。
STEMP[10:3]
STEMP[2:0]
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
2881[7:0]
2882[7:5]
2107[4:0]
2108[7:0]
–
–
–
–
R
R
温度测量结果。
0
0
28A0[3]
0
0
R
表示硬件仍然在写 0x28A0 字节。为 1 时,不允许对该字节进行写操作。写操作
持续时间可长达 6ms。
R
22°C 时的 STEMP 储存地址。STEMP 为 11 位字。
TBYTE_BUSY
R/W 每一个 XFER_BUSY 中断的复用帧周期数量。最大值为 8191 个周期。
230A[2:0]
230B[7:0]
28A0[4]
0
–
0
–
R/W 只要进行温度测量,则测量 VBAT。
TEMP_BSEL
28A0[7]
0
–
TBYTE_BUSY
28A0[3]
0
0
R/W 选择测量哪个电池引脚:1 = VBAT,0 = VBAT_RTC。
表示硬件仍然在写 0x28A0 字节。为 1 时,不允许对该字节进行写操作。写操作
R
持续时间可长达 6ms。
TEMP_22[10:8]
TEMP_22[7:0]
TEMP_BAT
122
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
名称
位置
复位 唤醒 方向 说明
设置两次温度测量的时间间隔。任何模式(MSN、BRN、LCD 或 SLP)下均可使能
自动测量。TEMP_PER = 0 禁用自动温度更新,此时,MPU 可利用 TEMP_START
启动单次温度测量。
TEMP_PER[2:0]
28A0[2:0]
0
–
R/W
TEMP_PER
0
1-6
7
时间(秒)
无温度更新
2(3+TEMP_PER)
连续更新
TEMP_PWR
28A0[6]
0
–
选择温度传感器的供电电源:
R/W 1 = V3P3D, 0 = VBAT_RTC。SLP 和 LCD 模式下忽略该位,而总是由
VBAT_RTC 供电。
TEMP_START
28B4[6]
0
0
TEMP_PER = 0 时,禁用自动温度更新,MPU 可利用 TEMP_START 启动单次温
R/W 度测量。每次测量需要 30ms。完成温度测量时,硬件清除 TEMP_START。因此
固件需要判断该位,为 0 后方可读取 STEMP 温度值。
TMUX[5:0]
2502[5:0]
–
–
R/W TMUXOUT 选择的 32 个信号之一,详情参见第 2.5.12 节。
TMUX2[4:0]
2503[4:0]
–
–
R/W TMUX2OUT 选择的 32 个信号之一,详情参见第 2.5.12 节。
TMUXRA[2:0]
270A[2:0]
000 000
R/W 用于远端传感器的 TMUX 设置(71M6x01)。
芯片版本号。固件可通过读取该字确定芯片版本。
VERSION[7:0]
2706[7:0]
–
–
R
VERSION[7:0]
0001 0011
0010 0010
芯片版本
B01
B02
使 ADC 基准电压输出到 VREF 引脚,VREF_DIS = 1 时禁用该功能。推荐禁止输
出。
VREF_CAL
2704[7]
0
0
R/W
VREF_DIS
2704[6]
0
1
R/W 禁用内部 ADC 电压基准。
Rev 2
123
71M6541D/F/G and 71M6542F/G Data Sheet
名称
位置
复位 唤醒 方向 说明
该字说明电源及 VDD 的状态。
VSTAT[2:0]
SFR F9[2:0]
–
–
R
WAKE_ARM
28B2[5]
0
–
R/W
2880[7:0]
28B4[7]
0
0
–
0
WF_DIO4
28B1[2]
0
–
WF_DIO52
28B1[1]
0
–
WF_DIO55
28B1[0]
0
–
WF_TMR
WF_PB
WF_RX
WF_CSTART
WF_RST
WF_RSTBIT
WF_OVF
WF_ERST
WF_BADVDD
28B1[5]
28B1[3]
28B1[4]
28B0[7]
28B0[6]
28B0[5]
28B0[4]
28B0[3]
28B0[2]
0
0
0
0
1
0
0
0
0
–
–
–
WAKE_TMR[7:0]
WD_RST
124
–
VSTAT 说明
000
系统电源就绪,V3P3A>3.0V。模拟电路工作正常、准确测量。
[V3AOK,V3OK] = 11
001
系统电源电压较低,2.8V<V3P3A<3.0V,模拟电路测量不准确。即将
切换至电池电源。[V3AOK,V3OK] = 01
010
电池电源和 VDD 就绪,VDD>2.25V,所有数字功能正常工作。
[V3AOK,V3OK] = 00,[VDDOK,VDDgt2] = 11
011
电池电源和 VDD>2.0,禁止 FLASH 写操作。如果 TRIMVDD[5]熔丝
熔断,PLL_FAST (I/O RAM 0x2200[4])清零。
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 01
101
电池电源和 VDD< 2.0V。VSTAT=101 时,处理器接近掉电。将引发
处理器故障。
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 00
准备好 WAKE 定时器,并向其装载 WAKE_TMR[7:0]。MPU 触发 SLEEP 或
LCD_ONLY 有效时,WAKE 定时器开始启动。
R/W 定时器唤醒间隔为 WAKE_TMR+1 秒。
W 复位 WD 定时器。向该位写 1 时,WD 复位(喂狗)
DIO4 唤醒标识位。DIO4 配置为唤醒器件时,只要去抖后的 DIO4 变高,该位置
R
位。如果 DI04 未配置为唤醒,它保持在复位状态。
DIO52 唤醒标识位。DIO52 配置为唤醒器件时,只要去抖后的 DIO52 变高,该位
R
置位。如果 DI052 未配置为唤醒,它保持在复位状态。
DIO55 唤醒标识位。DIO55 配置为唤醒器件时,只要去抖后的 DIO55 变高,该位
R
置位。如果 DI055 未配置为唤醒,它保持在复位状态。
R 唤醒定时器唤醒标识位。
R PB 唤醒标识位。
R RX 唤醒标识位。
R
RESET 引脚、RESET 位、E_RST 引脚、看门狗定时器、冷启动检测器或 VBAT
失效引起复位的标识位。
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
5.3
CE接口说明
5.3.1
CE程序
CE 执行准确计量所需的精密计算。这些计算包括消除失调、相位补偿、乘积平滑、乘积求和、频率检测、
VAR 计算、电压跌落检测和电压相位测量。CE 计算得到的所有数据均依赖于 EQU[2:0] (I/O RAM
0x2106[7:5])选择的计量公式。
CE 程序由 Teridian 作为数据映像提供,可与 MPU 操作码整合,用于表计设计。一般随 CE 程序提供演示
代码,无需修改即可用于多数应用。Teridian 也可提供其它类型的 CE 代码。本节介绍的内容适用于表 77
所示的 CE 代码版本,请联系当地的 Teridian 代表处,索取满足特定应用所需的最新 CE 代码。
表 77. 标准 CE 代码
器件
本地传感器
远端传感器
71M6541D/F/G
CE41A01 (Eq. 0 or 1)
CE41B016601
CE41A01 (Eq. 0 or 1)
CE41B016201
CE41A04 (Eq. 2)
(Eq. 0, 1 or 2)
71M6542F/G
5.3.2
CE数据格式
所有 CE 字为 4 个字节。除非特别说明,其格式为 32 位 2 的补码(-1 = 0xFFFFFFFF)。校准参数一般存放
在 EEPROM (或内部 FLASH)中,启动 CE 之前,必须由 MPU 复制到 CE 的校准寄存器。“内部”变量用
于 CE 的内部运算;“输入”变量使 MPU 能够控制 CE 操作;“输出”变量是 CE 计算结果的输出。最高
字节的对应 MPU 地址由 0x0000 + 4*CE_address 地址给出,0x0003 + 4*CE_address 给出最低字节。
5.3.3
常量
与 CE 输出计量数据有关的常量有:
•
•
•
•
•
•
•
•
采样频率:FS = 32768Hz/13 = 2520.62Hz。
F0 为电网的基波频率。
IMAX 为外部电流有效值,对应于输入 IA 和 IB 处的 250 mV pk (176.8mV rms)。例如:对于 250μΩ 锰
铜分流器, IMAX =176.8mV rms / 250μΩ = 707.2A rms)。如果前置放大器对于 IAP-IAN 输入有效,需
要对 IMAX 进行调整。
VMAX 为外部电压有效值,对应于输入 VA 和 VB 处的 250mV pk。计算方法如上。
NACC,电能累积周期内的采样点数,即 SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0], 0x2108[7:0])。
电能累积时间 SUM_SAMPS[12:0] / FS。即 XFER 中断频率。
X 为脉冲发生器的增益常数。由 CECONFIG 寄存器的 PULSE_FAST 和 PULSE_SLOW 位组合控制(见表
83)。
电压 LSB (用于跌落门限) = VMAX * 7.8798*10-9 V。
系统常数 IMAX 和 VMAX 是供 MPU 使用,将内部数字量(CE 使用)转换为外部参量,即表计参量。其值由
实际电表使用的电压和电流传感器的缩放比例决定。本文使用的 LSB 值将 CE 或 MPU 接口处的数字量与
外部电表输入参量关联起来。例如,如果希望电表输入 SAG 门限为 80 V rms,那么编程至 SAG_THR (CE
RAM 0x24)的数字值应为 80 Vrms * SQRT(2)/ SAG_THRLSB,其中 SAG_THRLSB 为 SAG_THR 说明中的 LSB
值(见表 84)。
参数 EQU[2:0] (I/O RAM 0x2106[7:5])、CE_E (I/O RAM 0x2106[0])和 SUM_SAMPS[12:0]对于 CE 工作是必
不可少的(详情请参见见第 5.2 节 I/O RAM 映射—按字母排序)。
Rev 2
125
71M6541D/F/G 和 71M6542F/G 数据资料
5.3.4
环境
在利用 CE_E 位(I/O RAM 0x2106[0])启动 CE 之前,MPU 必须通过以下步骤对 CE 进行必要的配置:
•
•
•
•
•
•
利用 CE_LCTN[5:0] (I/O RAM 0x2109[5:0])定位 CE 代码在 FLASH 中的起始地址
初始化 CE RAM 区
在 EQU[2:0] (I/O RAM 0x2106[7:5])中确定应用的计量公式
在 SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0], 0x2108[7:0])中确定每累积周期的采样点数
在(MUX_DIV[3:0] (I/O RAM 0x2100[7:4]))中确定每 ADC 复用帧的周期数量
为 MUXn_SEL 应用合适的值,以及为 DIFFn_E (I/O RAM 0x210C[5:4])和 RMT_E (I/O RAM 0x2709[3])应
用合适的选项,以配置模拟输入
配置 CE 对 MPU 的中断。例如 CE_BUSY、XFER_BUSY,或者电源故障检测中断
假设默认配置为 VMAX = 600V,IMAX = 707A,kH = 1Wh/脉冲
按照应用,可能还需要配置脉冲常数(WRATE 为脉冲常数的关联寄存器,具体参见 WRATE 说明)
•
•
•
使用不同的 CE 代码时,需要确定不同组的环境参数。这些参数的准确值列在随 CE 代码提供的应用笔记和
其它文档中。
如果 CE 代码运行时的环境参数不同于 Teridian 指定的数值,会产生不可预知的结果。请参见表
1 和表 2。
通常情况下,每个复用帧有 13 个 32768Hz 周期(见第 2.2.2 节输入复用器)。这意味着每个转换时隙中周期
的 数 量 与 每 帧 中 转 换 数 量 的 乘 积 必 须 为 12 ( 每 帧 加 一 个 稳 定 周 期 , 见 图 6 和 图 7) 。 默 认 配 置 为
FIR_LEN[1:0] = 01,I/O RAM 0x210C[2:1] (每次转换需 4 个周期)和 MUX_DIV[3:0] = 3 (每复用循环 3 次转
换)。
可从 Teridian 随演示工具包提供的演示代码中复制采样配置。
5.3.5
CE计算
参见表 78,MPU 通过写 EQU[2:0] (I/O RAM 0x2106[7:5])选择相应的公式。
表 78. CE EQU 公式和单元输入映射
EQU
0
1
2†
Watt & VAR 公式
(WSUM/VARSUM)
VA IA – 1 元件,2 线,1 相
VA*(IA-IB)/2 – 1 元件,3 线,1 相
VA*IA + VB*IB –2 元件,3 线,3 相 Δ
用于计算能量/电流的输入
W0SUM/
VAR0SUM
W1SUM/
VAR1SUM
I0SQ
SUM
I1SQ
SUM
VA*IA
VA*IB
–
IA
–
VA*(IA-IB)/2
IA-IB
IB
VA*IA
VB*IB
IA
IB
注:
†
仅限 71M6542F/G。
126
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
5.3.6
CE前端数据(原始数据)
通过读取表 79 所示地址 0 至 3、9 和 10 (十进制),访问 AFE 提供的原始 ADC 数据。
表 79 中的 MUX_SEL 栏显示不同传感器输入引脚的 MUX_SEL 序号。例如,如果通过控制位 DIFFA_E = 1
(I/O RAM 0x210C[4])使能差分模式,那么输入 IAP 和 IAN 被组合在一起形成一个差分输入,对应的
MUX_SEL 序号为 0。类似地,CE RAM 位置栏提供储存采样数据的 CE RAM 地址。仍用以上例子说明,
如果 DIFFA_E = 1,储存 IAP-IAN 差分输入的采样对应 CE RAM 位置为 0,CE RAM 位置不受影响。
IB 输入可配置为直接连接传感器(即直接连接至 71M654x)或远端传感器(即采用 71M6x01 远端传感器)。如
果通过 RMT_E = 0 禁用远端传感器,通过 DIFFB_E = 1 (I/O RAM 0x210C[5])使能差分模式,那么 IBP 和
IBN 形成一个差分输入,MUX_SEL 序号为 2,对应采样值储存在 CE RAM 地址 2 (CE RAM 地址 3 不受影
响)。如果远端传感器使能位 RMT_E = 1,以及 DIFFB_E = 0 或 1,那么 MUX_SEL 序号未定义(即传感器未
连接至 71M654x,所以 MUX_SEL 不适用,参见第 12 页的第 2.2 节模拟前端(AFE),对应于该远端差分
IBP-IBN 输入的采样被储存在 CE RAM 地址 2 (CE RAM 地址 3 不受影响)。
电压传感器输入(VA 和 VB)没有任何关联的配置位。VA 的 MUX_SEL 序号值为 10,其采样值储存在 CE
RAM 地址 10。VB 的 MUX_SEL 序号为 9,其采样储存在 CE RAM 地址 9。
表 79. CE 原始数据访问地址
引
脚
ADC
位置
ADC0
ADC1
IAP
IAP
ADC2
ADC3
IBP
IBN
MUX_SEL 序号
CE RAM 位置
DIFFA_E
DIFFA_E
0
1
0
1
0
0
0
0
1
1
RMT_E, DIFFB_E
RMT_E, DIFFB_E
0,0
0,1
1,0
1,1
0,0
0,1
1,0
1,1
2
2
2
–
–
2
2*
2*
3
3
ADC9、ADC10 没有配置位
9
9
10
10
ADC9
VB†
ADC10
VA
注:
*远端接口数据。
†
仅限 71M6542F/G。
5.3.7
FCE状态和控制
CE 状态字 CESTATUS 可以为 MPU 提供早期掉电报警(见表 80),这点非常有用。它包含 A 和 B 相的跌落报
警,以及用基波过零脉冲 F0。MPU 可在每个 CE_BUSY 中断读取 CE 状态字。由于 CE_BUSY 中断发生
频率为 2520.6Hz,因此中断服务程序执行时间应减量最小化。
表 80. CESTATUS 寄存器
CE 地址
名称
0x80
CESTATUS
Rev 2
说明
参见表 81 中的 CESTATUS 位说明。
127
71M6541D/F/G 和 71M6542F/G 数据资料
CESTATUS 提供关于电压状态及输入交流信号频率的信息,对于产生电源故障预警,从而启动必要的数据
存储非常有用。CESTATUS 在每次 CE 代码运行结束后更新(CE_BUSY 中断)。CESTATUS 中位的说明见表
81。
表 81. CESTATUS (CE RAM 0x80)位定义
CESTATUS
位
名称
31:4
3
2
未使用
F0
未使用
1
SAG_B
0
SAG_A
说明
未使用的位始终为 0。
F0 为方波,频率为电网的基波频率。
未使用的位始终为 0。
正常时为 0。VB 保持低于 SAG_THR,经过 SAG_CNT 个采样后变为 1;
直到 VB 升高至 SAG_THR 以上才清 0。
正常时为 0。VA 保持低于 SAG_THR,经过 SAG_CNT 个采样后变为 1;
直到 VA 升高至 SAG_THR 以上才清 0。
MPU 利 用 CECONFIG 配 置 CE( 表 82) 。 该 寄 存 器 含 有 SAG_CNT 、 FREQSEL[1:0] 、 EXT_PULSE 、
PULSE_SLOW 和 PULSE_FAST。CECONFIG 位定义如表 83 所示。
表 82. CECONFIG 寄存器
CE
地址
名称
数据
说明
1
0x0030DB00
参见表 83 中 CECONFIG 位说明。
0x00B0DB002
1. CE41A01 (71M6541D/F/G)或 CE41A04 (71M6542F/G) CE 的默认值用于本地传感器。
2. CE41B016201 和 CE41B016601 代码的默认值分别支持 71M6201 和 71M6601 远端传感器。
0x20
CECONFIG
表 83. CECONFIG (CE RAM 0x20)位定义
CECONFIG
位
名称
默认值
23
保留
0
22
EXT_TEMP
0
21
EDGE_INT
1
20
SAG_INT
1
19:8
SAG_CNT
252
(0xFC)
说明
该位置位时,使能对 71M6x01 远端传感器接口的温度补偿控制。
为 1 时,MPU 通过 GAIN_ADJn 寄存器(CE RAM 0x40-0x42)控制
温度补偿。
为 1 时,XPULSE 在 FREQSEL[1:0]所选相电压过零时产生一个
脉冲,可用于中断 MPU。
为 1 时,检测到跌落条件时激活 YPULSE 输出。
发出电压跌落警告之前,在 SAG_THR (CE RAM 0x24)以下的电压
连续采样数量。默认值等效于 100ms。
FREQSEL[1:0]选择用于频率监测、电压跌落检测以及过零计数
(MAINEDGE_X, CE RAM 0x83)的相。
FREQ SEL[1:0]
7:6
FREQSEL[1:0]
0
0
1
128
所选相
0
5
EXT_PULSE
1
4:2
保留
0
0
1
X
A
B*
不允许
*仅限 71M6542F/G
为 0 时,使脉冲发生器自动响应内部数据(WPULSE = WSUM_X
(CE RAM 0x84),VPULSE = VARSUM_X (CE RAM 0x88))。否则,
发生器响应 MPU 置于 APULSEW 和 APULSER (CE RAM 0x45 and
0x49)中的值。
保留。
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
1
PULSE_FAST
0
PULSE_SLOW
PULSE_FAST = 1 时,脉冲发生器输入增加 16 倍。PULSE_SLOW
= 1 时,脉冲发生器输入缩减 64 倍。这两个参数控制脉冲增益因
子 X (见下表)。允许值为 1 或 0。两个参数的默认值均为 0 (X =
6)。
0
PULSE_FAST PULSE_SLOW
0
0
1
0
0
1
1
1
0
X
1.5 * 22 = 6
1.5 * 26 = 96
1.5 * 2-4 = 0.09375
不使用
CECONFIG (CE RAM 0x20[7:6])中的 FREQSEL[1:0]字段选择用于产生电压跌落中断的相。这样,当所选的
相电压满足 SAG_THR (CE RAM 0x24)寄存器和 CECONFIG (CE RAM 0x20[19:8])中 SAG_CNT 字段设定的电
压跌落事件条件时,发生 SAG_INT 事件。SAG_INT 位(CE RAM 0x20[20])设为 1 时,跌落事件在 YPULSE
输出产生一个跳变。2 相系统中(71M6542F/G),跌落中断之后,MPU 应更改 FREQSEL[1:0]设置,选择另
一相(如果系统还有电)。即使只在所选相上发生电压跌落中断,两相应同时检查跌落。通过直接检查
CESTATUS (CE RAM 0x80[0:1])中 SAG_A 和 SAG_B 位,可检测给定相的电源电压。
为 1 时,EXT_TEMP 位使能 MPU 进行的温度补偿。为 0 时,使能内部(CE)温度补偿。
CE 脉冲发生器可由 MPU (外部)或 CE (内部)变量控制。如果 EXT_PULSE 位= 1 (CE RAM 0x20[5]),由
MPU 控制。这种情况下,MPU 通过将数值放入 APULSEW 和 APULSER (CE RAM 0x45 and 0x49),控制脉
冲速率(外部脉冲发生)。通过设置 EXT_PULSE = 0,CE 用 WSUM_X (CE RAM 0x84)和 VARSUM_X (CE
RAM 0x88)控制脉冲速率。
71M6541D/F/G 和 71M6542F/G 演示代码在电压跌落时关闭内部和外部脉冲发生器。
表 84. 跌落门限和增益调节控制
CE
地址
名称
默认值
说明
7
电压跌落报警门限。如果 VMAX = 600 Vrms,默认值相当于
113Vpk 或 80 Vrms。
 ∙ √2
_ =
 ∙ 7.8798 ∙ 10−9
该寄存器按比例缩放电压测量通道 VA 和 VB*。默认值 16384 相
当于单位增益(1.000)。
*仅限 71M6542F/G。
0x24
SAG_THR
2.39*10
0x40
GAIN_ADJ0
16384
0x41
GAIN_ADJ1
16384
该寄存器为 A 相按比例缩放 IA 电流通道,默认值 16384 相当于
单位增益(1.000)。
0x42
GAIN_ADJ2
16384
该寄存器为 B 相按比例缩放 IB 电流通道,默认值 16384 相当于
单位增益(1.000)。
5.3.8
CE传递变量
MPU 接收到 XFER_BUSY 中断时,表示传输变量中的数据已更新。CE 传输变量在 XFER_BUSY 中断发
生的那次 CE 运行中修改。它们在下个 XFER_BUSY 中断之前保持不变。本数据资料中,CE 传输变量的
名称末尾总为“_X”。传输变量可分类为:
•
•
•
基本能量测量数据
瞬态(RMS)值数据
其它测量参数
Rev 2
129
71M6541D/F/G 和 71M6542F/G 数据资料
5.3.8.1 基本能量测量数据
表 85 和表 86 介绍基本的能量测量数据。所有变量均为有符号的 32 位整数。累积变量,例如 WSUM,经
内部缩放。所以当积分时间为 1 秒时,它们在溢出之前至少有 2 倍裕量。此外,硬件上不会允许在溢出时
造成数据翻转问题。
表 85. CE 传递变量(本地传感器)
CE
地址
名称
说明
0x84†
WSUM_X
累积周期内的有功能量和:W0SUM_X+W1SUM_X。
EQU[2:0] = 0 (I/O RAM 0x2106[7:5])和 EQU[2:0] =
1 时不使用。
0x85
0x86
W0SUM_X
W1SUM_X
各相累积周期内的有功能量和。
LSBW = 9.4045*10-13 * VMAX * IMAX Wh.
0x88†
VARSUM_X
符号和:VAR0SUM_X+VAR1SUM_X。EQU[2:0] = 0
和 EQU[2:0] = 1 时不使用。
0x89
0x8A
VAR0SUM_X
VAR1SUM_X
各相累积周期内的无功能量和。
LSBW = 9.4045*10-13 * VMAX * IMAX VARh.
配置
图 35 (93 页)
图 37 (95 页)
注:
†
仅限 71M6542。
表 86. CE 传递变量(隔离传感器)
CE
地址
名称
说明
0x84†
WSUM_X
累积周期内的有功能量和:W0SUM_X+W1SUM_X。
EQU[2:0] = 0 (I/O RAM 0x2106[7:5])和 EQU[2:0] =
1 时不使用。
0x85
0x86
W0SUM_X
W1SUM_X
各相累积周期内的有功能量和。
LSB = 1.55124*10-12 * VMAX* IMAX Wh.
0x88†
VARSUM_X
符号和:VAR0SUM_X+VAR1SUM_X。EQU[2:0] = 0
和 EQU[2:0] = 1 时不使用。
0x89
0x8A
VAR0SUM_X
VAR1SUM_X
各相累积周期内的无功能量和。
LSB = 1.55124*10-12 *VMAX* IMAX VARh.
配置
图 36 (94 页)
图 38 (96 页 96)
注:
†
仅限 71M6542。
WSUM_X (CE RAM 0x84)和 VARSUM_X (CE RAM 0x88)是 A 相和 B 相的 Wh 或 VARh 有符号代数和,同时
取决于 I/O RAM 控制字段 EQU[2:0] (I/O RAM 0x2106[7:5])中指定的计量公式。WxSUM_X (x = 0 或 1,CE
RAM 0x85 和 0x86)是 x 相在上一累积间隔内累积的 Wh 值,可根据规定的 LSB 值计算得到。
130
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
5.3.8.2 瞬态能量测量数据
IxSQSUM_X 和 VxSQSUM (见表 87)是上一累积间隔采集的平方电流和电压采样之和。
表 87: CE 能量测量变量(使用本地传感器)
CE
地址
名称
0x8C
I0SQSUM_X
0x8D
I1SQSUM_X
0x90
V0SQSUM_X
0x91†
V1SQSUM_X
说明
配置
各相电流采样平方之和。
LSBI = 9.4045*10-13 IMAX2 A2h
EQU = 1 时,I0SQSUM_X 基于 IA 和 IB。
各相电压采样平方之和。
LSBV= 9.4045*10-13 VMAX2 V2h
图 35 (93 页)
图 37 (95 页)
†
仅限 71M6542。
表 88. CE 能量测量变量(隔离传感器)
CE
地址
名称
0x8C
I0SQSUM_X
0x8D
I1SQSUM_X
0x90
V0SQSUM_X
†
V1SQSUM_X
0x91
说明
配置
各相电流采样平方之和。
LSBI = 2.55872*10-12 * IMAX2 A2h
EQU = 1 时,I0SQSUM_X 基于 IA 和 IB。
各相电压采样平方之和。
LSBV= 9.40448*10-13 * VMAX2 V2h
图 36 (94 页)
图 38 (96 页 96)
†
仅限 71M6542。
MPU 可利用平方电流和电压采样计算得到 RMS 值,如下所示:
Ix RMS =
IxSQSUM ⋅ LSBI ⋅ 3600 ⋅ FS
N ACC
VxRMS =
VxSQSUM ⋅ LSBV ⋅ 3600 ⋅ FS
N ACC
注:NACC = SUM_SAMPS[12:0] (CE RAM 0x23).
其它传递变量包括可用于频率和相位测量的变量,以及反映电网电压和电池电压过零次数的变量。这些传
递变量在表 89 中列出。
MAINEDGE_X (CE RAM 0x83)反映上一累积间隔内对 CECONFIG (CE RAM 0x20[7:6])中 FREQSEL[1:0]字段
规定相上的交流信号的半周期数量(即过零次数)。MAINEDGE_X 对于根据输入交流信号实现实时时钟非常
有用。
Rev 2
131
71M6541D/F/G 和 71M6542F/G 数据资料
表 89. 其它传递变量
CE
地址
名称
说明
2520.6 Hz
≈ 0.509 ⋅ 10− 6 Hz(本地)
232
2520.6 Hz
LSB ≡
≈ 0.587 ⋅ 10− 6 Hz(远端)
32
2
所选电压在上一累积间隔内的过零数量。过零包括任意方向,并去抖。
基波频率: LSB ≡
0x82
FREQ_X
0x83
MAINEDGE_X
5.3.9
脉冲发生器
表 90 列出了 CE 脉冲发生器、参数。
CECONFIG PULSE_SLOW 和 PULSE_FAST 位(CE RAM 0x20[0:1])的组合控制脉冲速率。默认值为 00,此时
保持 Kh 公式给定的脉冲速率。
WRATE (CE RAM 0x21)控制每个实测 Wh 和 VARh 产生的脉冲数量。WRATE 越低,实测能量参量的脉冲速
率越低。表计常数 Kh 源于 WRATE,为每个脉冲所代表的能量值。也就是说,如果 Kh = 1Wh/脉冲,120 V
和 30 A 加到电表时,可以每秒产生一个脉冲。如果负载为 240V,150A,则每秒产生 10 个脉冲。以上假
定功率因数为 1。
如果 EXT_PULSE = 1 (CE RAM 0x20[5]),脉冲控制权交给 MPU。这种情况下,脉冲速率由 APULSEW 和
APULSER (CE RAM 0x45 and 0x49)决定。MPU 必须将产生脉冲的源加载至 APULSEW 和 APULSER,以产生
脉 冲 。 如 果 EXT_PULSE = 0 (CE RAM 0x20[5]) , 脉 冲 由 CE 控 制 。 W0SUM_X (CE RAM 0x85) 和
VAR0SUM_X (CE RAM 0x89)为默认的脉冲发生源。这种情况下,潜动/启动功能不太好控制。
最大脉冲率为 3*FS = 7.56kHz。
关于如何调节输出脉冲定时的详细信息,请参见第 2.3.6.2 节 VPULSE 和 WPULSE。
最大时间抖动为复用循环周期的 1/6(即 397/6=67μs),与测得的脉冲数量无关。所以,如果监测脉冲发生
器 1 秒,峰值抖动为 67ppm;10 秒后,峰值抖动为 6.7ppm。平均抖动总为零。如果试图以高于其最大值
的速率驱动脉冲发生器,它仅仅是以最大速率输出。实际脉冲速率(以 WSUM 为例)为:
RATE =
WRATE ⋅ WSUM ⋅ FS ⋅ X
Hz ,
2 46
式中,FS = 采样率(2520.6Hz),X = 从 CE 变量 PULSE_SLOW (CE RAM 0x20[0])和 PULSE_FAST (CE RAM
0x20[1])获得的脉冲速率因子。
132
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
表 90. CE 脉冲发生参数
CE
地址
名称
默认值
说明
Kh =
0x21
WRATE
547
0x22
KVAR
6444
0x23
SUM_SAMPS
2520
0x45
APULSEW
0
VMAX ⋅ IMAX ⋅ K
⋅ Wh / pulse
WRATE ⋅ N ACC ⋅ X
式中:
K = 66.1782 (本地传感器)
K = 109.1587 (远端传感器)
NACC = SUM_SAMPS[12:0] (CE RAM 0x23)
X 的定义请参见表 83。
VMAX = 600V 和 IMAX = 208A 时,默认值形成 1.0Wh/脉冲。
WRATE 的最大值为 32,768 (215)。
VAR 测量缩放因子。
SUM_SAMPS (NACC).
Wh 脉冲(WPULSE)发生器输入,使用外部脉冲发生时,由 MPU
更新。输出脉冲率为:
APULSEW * FS * 2-32 * WRATE * X * 2-14.
该输入经过缓冲,可由 MPU 在转换间隔期间更新。更改在下一
个周期开始时生效。
0x46
WPULSE_CTR
0
WPULSE 计数器。
0x47
WPULSE_FRAC
0
无符号分子,小数脉冲。该寄存器数值总是向下一个整脉冲累加
计数。
0x48
WSUM_ACCUM
0
WPULSE 的翻转累加器。
0x49
APULSER
0
VARh (VPULSE)脉冲发生器输入。
0x4A
VPULSE_CTR
0
VPULSE 计数器。
0x4B
0x4C
VPULSE_FRAC
0
0
无符号分子,小数脉冲。该寄存器总是向下一个脉冲计数。
Rev 2
VSUM_ACCUM
VPULSE 的翻转累加器。
133
71M6541D/F/G 和 71M6542F/G 数据资料
5.3.10 其它CE参数
表 91 所示 CE 参数用于抑制由于缩放和截断效应所引起的噪声。
表 91. 用于噪声抑制和代码版本的 CE 参数
CE
地址
名称
默认值
说明
QUANT_VA
0x25
0
QUANT_IA
0x26
0
A 相的电压、电流、有功能量和无功能量截断误差和噪声的补偿
因子。
QUANT_A
0x27
0
QUANT_VARA
0x28
0
QUANT_VB
0x29 †
0
B 相的电压、电流、有功能量和无功能量截断误差和噪声的补偿
QUANT_IB
0x2A
0
因子。
QUANT_B
0x2B
0
†
仅限 71M6542。
QUANT_VARB
0x2C
0
0x38
0x43453431
CE 文件及版本号标识符,ASCII 格式(CE41a01f)。只要 CE 启
0x39
0x6130316B
动,这些值将被覆盖。
0x3A
0x00000000
以下是在使用本地传感器时,各补偿参数的 LSB:
QUANT _ Ix _ LSB = 5.08656 ⋅ 10 −13 ⋅ IMAX 2 ( Amps 2 )
QUANT _ Wx _ LSB = 1.04173 ⋅ 10 −9 ⋅ VMAX ⋅ IMAX (Watts )
QUANT _ VARx _ LSB = 1.04173 ⋅ 10 −9 ⋅ VMAX ⋅ IMAX (Vars )
以下是在使用 71M6x01 远端传感器时,各补偿参数的 LSB:
QUANT _ Ix _ LSB = 1.38392 ⋅ 10−12 ⋅ IMAX 2 ( Amps 2 )
QUANT _ Wx _ LSB = 1.71829 ⋅ 10−9 ⋅ VMAX ⋅ IMAX (Watts )
QUANT _ VARx _ LSB = 1.71829 ⋅ 10−9 ⋅ VMAX ⋅ IMAX (Vars )
134
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
5.3.11 CE校准参数
表 92 列出了通常输入用以影响电表校准精度的参数。
表 92. CE 校准参数
CE
地址
名称
默认值
说明
0x10
0x11
0x13
0x14†
CAL_IA
CAL_VA
CAL_IB
CAL_VB
16384
16384
16384
16384
这些常量控制各自通道的增益,每个通道的标称值为 214 = 16384,
每个通道的增益与 CAL 参数成正比。所以,如果通道增益减小
1%,CAL 应增大 1%。关于计算这些校准参数的公式,请参阅
71M6541 演示板用户手册。
†
仅限 71M6542。
0x12
PHADJ_A
0
这些常数控制在使用本地传感器时的相位补偿。PHADJ_X = 0 时,
不做补偿。当 PHADJ_X 增大时,补偿量(滞后)增大。范围为±215 –
1,如果将电流延迟 φ 相位角,公式为:
PHADJ _ X = 2 20
0x15
PHADJ_B
0
0.02229 ⋅ TANΦ
,60Hz 时
0.1487 − 0.0131 ⋅ TANΦ
0.0155 ⋅ TANΦ
,50Hz 时
0.1241 − 0.009695 ⋅ TANΦ
使用远端隔离器时的相位补偿公式:
PHADJ _ X = 2 20
0x12
DLYADJ_A
0
 2πf 
 2πf
 + 2ab cos
a 2 cos 2 
2π
 fs 
 fs
DLYADJ _ X = ∆ deg rees (1 + 0.1∆ deg rees )214
360
 2πf 

c sin 
 fs 
式中:

 + b

a = 2A
b = A2 + 1
0x15
DLYADJ_B
0
 = 22 + 4 �
式中,f 为电网频率,fs 为采样频率。下表为每个电流通道提供了 A
值:
通道
DLYADJ_A
DLYADJ_B
Rev 2
2
�+2

A 值(十进制)
Eq. 0 或 2
15811 / 214
-1384 / 214
Eq. 1
6811 / 214
-1384 / 214
135
71M6541D/F/G 和 71M6542F/G 数据资料
5.3.12 CE流程图
图 44 至图 46 所示为通过 CE 的数据流简图。未显示的功能包括:延迟补偿、电压跌落检测、缩放和计量
公式(EQU)处理。
图 44. CE 数据流:复用器和 ADC
图 45. CE 数据流:缩放、增益控制、中间变量
136
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
SUM
Σ
W0
W1
Σ
VAR0
Σ
VAR1
Σ
W0SUM_X
MPU
W1SUM_X
VAR0SUM_X
VAR1SUM_X
SUM_SAMPS=2520
SQUARE
I0
SUM
I0SQ
I2
V0SQ
V0
V2
I1
I2
I1SQ
Σ
I0SQSUM_X
Σ
V0SQSUM_X
Σ
I1SQSUM_X
F0
图 46. CE 数据流:平方、求和运算级
Rev 2
137
71M6541D/F/G 和 71M6542F/G 数据资料
6
电气规格
本节介绍 71M654x 的电技术指标。关于 71M6x01 的电技术指标、引脚输出和封装数据,请参阅 71M6xxx
的数据资料。
器件在室温下经过100%的生产测试,在全温范围内工作时可保证性能。
6.1
绝对最大额定值
表 93 列出了器件的绝对最大额定值。超出绝对最大额定值时,有可能会造成器件永久损坏。这些仅仅是耐
压额定值,器件在这些条件下工作,或者在其它任何超出推荐工作条件(见第 6.3 节推荐工作条件)的条件下
工作都是不可取的。长时间工作在绝对最大额定值条件下,可能影响器件可靠性。以下所有电压以 GNDA
为基准。
表 93. 绝对最大额定值
电压和电流
电源和地引脚
V3P3SYS, V3P3A
−0.5V 至 4. V
VBAT, VBAT_RTC
-0.5V 至 4.6V
GNDD
-0.1V 至+0.1V
模拟输出引脚
VREF
-10mA 至+10mA,
-0.5V 至 V3P3A+0.5V
VDD
-10mA 至 10mA,
-0.5V 至 3.0V
V3P3D
-10mA 至 10mA,
-0.5V 至 4.6V
VLCD
-10mA 至 10mA,
-0.5V 至 6V
模拟输入引脚
IAP-IAN, VA, IBP-IBN, VB† († 仅限 71M6542F/G)
-10mA 至+10mA
-0.5V 至 V3P3A+0.5V
XIN, XOUT
-10mA 至+10mA
-0.5V 至 3.0V
SEG 和 SEGDIO 引脚
配置为 SEG 或 COM 驱动
-1mA 至 1mA,
-0.5V 至 VLCD+0.5V
配置为数字输入
-10mA 至 10mA,
-0.5V 至 6V
配置为数字输出
-10mA 至 10mA,
-0.5V 至 V3P3D+0.5V
数字引脚
输入(PB, RESET, RX, ICE_E, TEST)
-10mA 至 10mA,
-0.5V 至 6V
输出(TX)
-10mA 至 10mA,
-0.5V 至 V3P3D+0.5V
温度和 ESD 等级
工作结温(峰值,100ms)
138
140°C
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
工作结温(连续)
125°C
储存温度
焊接温度—10 秒持续时间
−45°C 至+165°C
+250°C
所有引脚的 ESD 保护等级
±4kV
推荐外部元件
6.2
表 94. 推荐外部元件
名称
从
至
C1
V3P3A
GNDA
C2
V3P3D
GNDD
CSYS
V3P3SYS
CVDD
CVLCD
功能
值
单位
3.3V 电源旁路电容
≥0.1 ±20%
µF
3.3V 输出旁路电容
0.1 ±20%
µF
GNDD
V3P3SYS 旁路电容
≥1.0 ±30%
µF
VDD
GNDD
VDD 旁路电容
0.1 ±20%
µF
VLCD
GNDD
VLCD 旁路电容(使用电荷泵时)
≥0.1 ±20%
µF
32.768
kHz
15 ±10%
pF
10 ±10%
pF
XTAL
XIN
XOUT
32.768kHz 晶振—电气特性类似于
ECS .327-12.5-17X、Vishay XT26T 或
Suntsu SCP6–32.768kHz TR (负载电容
12.5pF)。
CXS
XIN
GNDA
CXL
XOUT
GNDA
晶振负载电容,取决于晶振技术指标和电
路板寄生影响。标称值基于 4pF 电路板寄
生电容和芯片电容容差。
6.3
推荐工作条件
除非另外说明,第 6.4 节性能技术指标 和第 6.5 节定时技术指标所列的全部参数在表 95 给出的推荐工作条
件范围内有效。
表 95. 推荐工作条件
参数
条件
V3P3SYS 和 V3P3A 为精密表计工作提供
电压(MSN 模式)。VBAT 和 VBAT_RTC 无
电压。
VBAT=0V 至 3.8V
VBAT_RTC =0V 至
3.8V
V3P3SYS < 2.8V
和
Max (VBAT_RTC,
V3P3SYS) > 2.0V
VBAT 电压(BRN 模式)。V3P3SYS 低于
2.8V 比较器门限。V3P3SYS 或
VBAT_RTC 必须足够高,以便为 RTC 模
块供电。
VBAT_RTC 电压。在 V3P3SYS < 2.0V 时
VBAT_RTC 对 RTC 和非易失存储器供
电。
V3P3SYS<2.0V
工作温度
最小值
典型值
最大值
单位
3.0
3.6
V
2.5
3.8
V
2.0
3.8
V
-40
+85
ºC
注:
1. GNDA 和 GNDD 必须连接在一起。
2. V3P3SYS 和 V3P3A 必须连接在一起。
Rev 2
139
71M6541D/F/G 和 71M6542F/G 数据资料
6.4
性能指标
6.4.1
输入逻辑电平
表 96. 输入逻辑电平
参数
条件
最小值
1
数字高电平输入电压 ,VIH
典型值
2
数字低电平输入电压 ,VIL
输入下拉电流,IIH
ICE_E, RESET, TEST
其它数字输入
VIN=0V,
ICE_E=3.3V
单位
V
1
输入上拉电流,IIL
E_RXTX, E_RST, E_TCLK
OPT_RX, OPT_TX
SPI_CSZ (SEGDIO36)
其它数字输入
最大值
0.8
V
µA
µA
µΩ
µA
µA
µA
10
10
10
-1
0
100
100
10
1
10
-1
0
100
1
VIN=V3P3D
注:
1. 电池供电模式下,数字输入应低于 0.1V 或高于 VBAT – 0.1V,将电池电流降至最小。
6.4.2
输出逻辑电平
表 97. 输出逻辑电平
参数
数字高电平输出电压,VOH
数字低电平输出电压,VOL
条件
ILOAD = 1mA
ILOAD = 15mA
(见注释 1、2)
ILOAD = 1mA
ILOAD = 15mA
(见注释 1)
最小值
V3P3D–0.4
V3P3D-0.6
0
0
典型值
最大值
单位
V
V
0.4
0.8
V
V
注:
1. 由设计保证,非产品测试。
2. 注意:全部上拉电流之和必须与内部 V3P3D 开关的导通电阻匹配。请参见第 143 页第 6.4.6 节
V3P3D 开关。
140
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
6.4.3
电池监测器
表 98. 电池监测器技术指标(TEMP_BAT= 1)
参数
条件
最小值
MSN 模式,TEMP_PWR = 1
BV:电池电压(定义)
测量误差
 BV

100 ⋅ 
− 1
 VBAT

BRN 模式,
TEMP_PWR=TEMP_BSEL
 = 3.291 + ( − 142) ∙ 0.0255 +  ∙ 328
-7.5
-5
-3
-3
V3P3 = 3.3 V,
TEMP_BSEL = 0,
TEMP_PER = 111,
VBAT_RTC = 3.6 V,
施加到 BCURR 的负载
V3P3 = 3.3 V
6.4.4
最大值
 = 3.3 + ( − 142) ∙ 0.0246 +  ∙ 297
VBAT =
2.0 V
2.5 V
3.0 V
4.0 V
输入阻抗,连续测量,MSN
模式。
V(VBAT_RTC)/I(VBAT_RTC)
IBAT(BCURR=1) - IBAT(BCURR=0)
典型值
7.5
5
3
5
1
单位
V
%
MΩ
50
100
140
µA
温度监测器
表 99. 温度监测器
参数
条件
最小值
典型值
最大值
单位
MSN 模式下,TEMP_PWR=1:
温度测量公式
 = 0.325 ∙  + 22
 = 0.325 ∙  + 0.00218 ∙  2 − 0.609 ∙  + 64.4
温度误差
TA=+22°C
VBAT_RTC 电荷/测量
TEMP_BSEL = 0,
TEMP_PWR=0,
SLP 模式,
VBAT_RTC = 3.6 V
设置 TEMP_START 之后温度测
量的持续时间(见注释 1)
°C
BRN 模式下,TEMP_PWR = TEMP_BSEL:
-2
+2
16
°C
µC
TEMP_PWR = 0,
TEMP_PER = 7,
SLP 模式,
VBAT_RTC = 3.6 V
Force V3P3D = 1.0 V
15
60
ms
注:
1. 由设计保证,非产品测试。
Rev 2
141
71M6541D/F/G 和 71M6542F/G 数据资料
6.4.5
电源电流
表 100 中提供的供电电流仅包括 71M654x 消耗的电流。关于使用 71M6x01 远端传感器时需要的额外电流,
请参阅 71M6xxx 数据资料。
表 100. 电源电流指标
参数
条件
最小
值
典型
值
最大
值
单位
5.5
6.7
mA
2.6
3.5
mA
I1b:
V3P3A + V3P3SYS 电流,半 除 PRE_E = 1 外,同 I1
速(ADC_DIV =1) (见注释 1)
5.7
6.9
mA
I1c:
V3P3A + V3P3SYS 电流,半 除 PLL_FAST = 0 和 PRE_E = 1 外,同 I1
速(ADC_DIV =1) (见注释 1)
2.6
3.6
mA
0.4
0.6
mA/
MHz
0
2.4
0.4
24
3.0
1.1
0
300
3.2
108
36
11
3.4
+300
nA
mA
nA
µA
µA
µA
nA
0
240
1.8
0.7
1.5
300
320
4.1
1.7
3.2
nA
nA
µA
µA
µA
7.1
8.7
mA
单相:2 路电流,1 路电压
V3P3A = V3P3SYS = 3.3 V,
I1:
MPU_DIV [2:0]= 3 (614kHz MPU 时钟),
V3P3A + V3P3SYS 电流,半 无 FLASH 写操作,
速(ADC_DIV=1) (见注释 1)
RTM_E=0, PRE_E=0, CE_E=1, ADC_E=1,
ADC_DIV=1, MUX_DIV[3:0]=3,
FIR_LEN[1:0]=1, PLL_FAST=1
I1a:
V3P3A + V3P3SYS 电流,半 除 PLL_FAST = 0 外,同 I1
速(ADC_DIV =1) (见注释 1)
除 MPU_DIV[2:0] 变动外,同 I1
I2:
V3P3A + V3P3SYS 动态电流
I MPU_DIV = 0 - I MPU_DIV = 3
4.3
VBAT 电流
I3: MSN 模式
I4: BRN 模式
I5: LCD 模式 (ext. VLCD)
I6: LCD 模式 (boost, DAC) 注 1
I7: LCD 模式 (DAC) 注 1
I8: LCD 模式(VBAT) 注 1
I9: SLP 模式
-300
CE_E=0
LCD_VMODE[1:0]=3,参见注释 2
LCD_VMODE[1:0]=2,参见注释 3
LCD_VMODE[1:0]=1,参见注释 3
LCD_VMODE[1:0]=0,参见注释 3
SLP 模式
-300
VBAT_RTC 电流
I10: MSN
I11: BRN
I12: LCD 模式
I13: SLP 模式
I14: SLP 模式(参见注释 1)
I15:
V3P3A + V3P3SYS 电流,
通过 ICE 写 FLASH
-300
LCD_VMODE[1:0]=2,参见注释 2
TA ≤ 25 °C
TA = 85 °C
除了以最大速率写 FLASH 外,同 I1,
CE_E=0, ADC_E=0.
注:
1.
2.
3.
142
由设计保证,非产品测试。
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, 所有 LCD_MAPn bits = 1, LCD_BLANK=0,
LCD_ON=1。
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, 所有 LCD_MAPn bits = 0。
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
6.4.6
V3P3D开关
表 101. V3P3D 开关技术指标
参数
条件
导通电阻 – V3P3SYS 至 V3P3D
| IV3P3D | ≤ 1 mA
导通电阻 – VBAT 至 V3P3D
| IV3P3D | ≤ 1 mA,
VBAT>2.5V
V3P3SYS = 3V
V3P3D = 2.9V
VBAT = 2.6V
V3P3D = 2.5V
V3P3D IOH, MSN
V3P3D IOH, BRN
6.4.7
最小值
典型值
最大值
单位
10
Ω
10
Ω
10
mA
10
mA
内部电源故障比较器
表 102. 内部电源故障比较器技术指标
参数
100mV 过载,下降
100mV 过载,上升
总响应时间
下降门限
3.0V 比较器
2.8V 比较器
3.0V 和 2.8V 差分比较器
V3P3 下降
下降门限
2.25V 比较器
2.0V 比较器
VDD (@VBAT=3.0V) – 2.25V 比较器
2.25V 和 2.0V 差分比较器
VDD 下降
滞回
(上升门限 - 下降门限)
3.0V 比较器
2.8V 比较器
2.25V 比较器
2.0V 比较器
TA = 22°C
6.4.8
最小 典型
值
值
条件
20
最大
值
单位
200
200
µs
µs
2.83
2.75
50
2.93
2.81
136
3.03
2.87
220
V
V
mV
2.2
1.90
0.25
0.15
2.25
2.00
0.35
0.25
2.5
2.20
0.45
0.35
V
V
V
V
22
25
10
10
45
42
33
28
65
60
60
60
mV
mV
mV
mV
2.5V稳压器—系统电源
表 103. 2.5V 稳压器技术指标
参数
V2P5
V2P5 负载调整率
压差 V3P3SYS-V2P5
Rev 2
条件
V3P3 = 3.0V - 3.8V
ILOAD = 0mA
VBAT = 3.3V , V3P3 = 0V
ILOAD = 0mA 至 1mA
ILOAD = 5 mA,
减小 V3P3D,直到 V2P5
下降 200mV
最小值
典型值
最大值
单位
2.55
2.65
2.75
V
40
mV
440
mV
143
71M6541D/F/G 和 71M6542F/G 数据资料
6.4.9
2.5V稳压器—电池供电
除非另外说明,V3P3SYS = V3P3A = 0,PB=GND (BRN)。
表 104. 低功耗稳压器技术指标
参数
条件
VBAT = 3.0V - 3.8V,
V3P3 = 0V, ILOAD = 0mA
VBAT = 3.3V, V3P3 = 0V,
ILOAD = 0 mA 至 1 mA
ILOAD = 0mA, VBAT = 2.0V,
V3P3 = 0V
V2P5
V2P5 负载调整率
压差 2V − VBAT-VDD
最小
值
典型
值
最大
值
单位
2.55
2.65
2.75
V
40
mV
200
mV
最大
值
单位
1
μW
3
pF
6.4.10 晶振
测量条件:晶振断开,测试负载 200pF/100kΩ,XOUT 和 GNDD 之间。
表 105. 晶振指标
参数
条件
至晶振的最大输出功率
晶振断开,见注释 1
最小
值
典型
值
XIN 至 XOUT 电容(见注释 1)
XOUT 电容变化
RTC_ADJ = 7F 至 0,
偏压 = 不偏压,
Vpp = 0.1V
15
pF
注:
1. 由设计保证,非产品测试。
6.4.11 锁相环(PLL)
表 106. PLL 技术指标
参数
条件
PLL 上电稳定时间(见注释 1)
PLL_FAST = 0, V3P3 = 0V 至 3.3V
步进,测得 MCK 第一个沿的时间
最
小
值
典
型
值
最
大
值
单位
5
ms
5
5
ms
ms
PLL_FAST 稳定时间
PLL_FAST 上升(见注释 1)
PLL_FAST 下降(见注释 1)
V3P3 = 0V, VBAT = 3.8V 至 2.0V
PLL SLP 至 MSN 稳定时间(见注释 1)
PLL_FAST = 0
5
ms
PLL 上电过冲(见注释 1)
PLL_FAST = 0
2.5
MHz
注:
1. 由设计保证,非产品测试。
144
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
6.4.12 LCD驱动器
表 107. LCD 驱动器技术指标
参数
VLCD 电流
(见注释 1 至 4)
注:
1.
2.
3.
4.
Rev 2
条件
最小值
典型值
VLCD=3.3,全部 LCD 映射位=0
VLCD=5.0,全部 LCD 映射位=0
最大值
2
3
单位
uA
uA
这些技术指标适用于所有 COM 和 SEG 引脚。
VLCD = 2.5V 至 5V。
LCD_VMODE=3, LCD_ON=1, LCD_BLANK=0, LCD_MODE=6, LCD_CLK=2。
输出负载为每 SEG 和 COM 引脚 74pF。
145
71M6541D/F/G 和 71M6542F/G 数据资料
6.4.13 VLCD发生器
表 108. LCD 驱动器技术指标 1
参数
条件
VSYS 至 VLCD 开关阻抗
VBAT 至 VLCD 开关阻抗
LCD 升压频率
VLCD IOH 电流
(VLCD(0)-VLCD(IOH)<0.25)
V3P3 = 3.3V,
RVLCD = 断开, LCD_BAT=0,
LCD_VMODE[1:0]=0,
∆ILCD=10µA
V3P3 = 0V, VBAT = 2.5V,
RVLCD = 断开, LCD_BAT =1,
LCD_VMODE[1:0]=0,
∆ILCD=10µA
LCD_VMODE[1:0] = 2,
RVLCD = 断开,
CVLCD = 断开
PLL_FAST=1
PLL_FAST=0
LCD_VMODE[1:0] = 2,
LCD_CLK[1:0] = 2,
RVLCD = 断开,
V3P3 = 3.3V,
LCD_DAC[4:0] = 1F
最小值 典型值 最大值
单位
750
Ω
700
Ω
820
786
kHz
kHz
10
µA
从 LCDADJ0 和 LCDADJ12 熔丝:
12 − 0
_�
12
_
 (_) = 2.65 + 2.65
+ (_)
31
以上公式说明指定 LCD_DAC 值下的 VLCD 标称值。以下技术指标列出实际 VLCD 和 VLCDnom 之间的
最大偏差。注意,VCC 和升压足够时,LCD DAC 不会达到其目标值,将发生大的负误差。
(_) = 5 �0 +
LCD_DAC 误差。VLCD-VLCDnom
(见注释 2)
满幅,升压
V3P3 =3.6V
V3P3 =3.0V
VBAT=4.0V, V3P3=0, BRN 模式
VBAT=2.5V, V3P3=0, BRN 模式
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
LCD_DAC 误差。VLCD-VLCDnom
DAC=12,升压
V3P3 = 3.6V
V3P3 = 3.0V
VBAT = 2.5V, V3P3 = 0V, BRN 模式
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] = C,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
LCD_DAC 误差。VLCD-VLCDnom
零幅,升压
V3P3 = 3.6V
V3P3 = 3.0V
VBAT = 4.0V, V3P3 = 0V, BRN 模式
(见注释 2)
VBAT = 2.5V, V3P3 = 0V, BRN 模式
LCD_DAC 误差。VLCD-VLCDnom
满幅,无升压
V3P3 = 3.6V (见注释 2)
V3P3 = 3.0V (见注释 2)
VBAT = 4.0V, V3P3 = 0V, BRN 模式
VBAT = 2.5V, V3P3 = 0V, BRN 模式
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] =0,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
146
LCD_VMODE[1:0] = 1,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-0.4
-0.15
-1.3
0.15
0.15
0.15
V
V
V
V
-0.15
-0.15
-0.15
0.15
0.15
0.15
V
V
V
-0.15
-0.15
-0.15
0.15
0.15
0.15
V
V
V
-0.15
0.15
V
-2.1
-2.8
-1.8
-3.2
V
V
V
V
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
参数
条件
最小值 典型值 最大值
LCD_VMODE[1:0] = 1,
LCD_DAC 误差。VLCD-VLCDnom
LCD_DAC[4:0] = C,
DAC=12,无升压
LCD_CLK[1:0]=2,
-0.5
V3P3 = 3.6V
LCD_MODE[2:0]=6
-1.1
V3P3 = 3.0V
-0.152
0.152
2
VBAT = 4.0V, V3P3 = 0V, BRN 模式
-1.5
VBAT = 2.5V, V3P3 = 0V, BRN 模式
LCD_VMODE[1:0] = 1,
LCD_DAC 误差。VLCD-VLCDnom
LCD_DAC[4:0] = 0,
零幅,无升压
LCD_CLK[1:0]=2,
-0.15
0.15
V3P3 = 3.6V
LCD_MODE[2:0]=6
-0.15
0.15
V3P3 = 3.0V
-0.15
0.15
VBAT = 4.0V, V3P3 = 0V, BRN 模式
-0.45
0.15
VBAT = 2.5V, V3P3 = 0V, BRN 模式
LCD_VMODE[1:0] = 2,
LCD_DAC 误差。VLCD-VLCDnom
LCD_DAC[4:0] = 1F,
满幅,升压,LCD 模式
LCD_CLK[1:0]=2,
-0.15
0.15
VBAT = 4.0V, V3P3 = 0V
LCD_MODE[2:0]=6
-1.3
VBAT = 2.5V, V3P3 = 0V
注:
1. 以下测试条件也适用于本表中提供的全部技术指标:旁路电容 CVLCD ≥ 0.1μF,测试负载 RVLCD =
500kΩ,无显示,全部 SEGDIO 引脚配置为 DIO。
2. 由设计保证,非产品测试。
Rev 2
单位
V
V
V
V
V
V
V
V
V
V
147
71M6541D/F/G 和 71M6542F/G 数据资料
6.4.14 VREF
表 109 所示为 ADC 基准电压(VREF)的性能技术指标。
表 109. VREF 技术指标
参数
条件
最小值
典型值
最大值
单位
1.193
1.195
1.197
V
VREF 输出电压,VREF(22)
TA = 22ºC
VREF 输出电压,VREF(22)
PLL_FAST=0
VREF 输出阻抗
VREF_CAL = 1,
ILOAD = 10µA, -10µA
VREF 电源灵敏度
ΔVREF / ΔV3P3A
V3P3A = 3.0V 至 3.6V
-1.5
VREF 输入阻抗
VREF_DIS = 1,
VREF = 1.3V 至 1.7V
100
VREF 斩波步距,调节
VREF(CHOP=01) −
VREF(CHOP=10)
-10
VNOM 定义(见注释 2)
VNOM (T ) = VREF (22) + (T − 22)TC1 + (T − 22) 2 TC 2
VNOM 温度系数:
TC1 =
TC2 =
VREF(T) 相对于 VNOM(T)的偏
差(见注释 1):
VREF (T ) − VNOM (T ) 106
VNOM (T )
62
VREF 老化
1.195
V
3.2
kΩ
1.5
mV/V
kΩ
0
10
275 − 4.95 ⋅ TRIMT
+40
±25
V
µV/°C
µV/°C2
−0.557 + 0.00028 ⋅ TRIMT
-40
mV
ppm/°C
ppm/年
注:
1. 由设计保证,非产品测试。
2. 这一关系说明 VREF 在不同温度下的变化,受 1 次和 2 次系数 TC1 和 TC2 的二阶多项式控制。
3. 对于本表中的参数,除非另外说明,VREF_DIS = 0,PLL_FAST = 1。
148
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
6.4.15 ADC转换器
表 110. ADC 转换器技术指标
参数
条件
最大值
单位
-250
250
mV
peak
Vin = 200mV 峰值,
65Hz,VADC10 (VA)或
VADC9 (VB)上†
†仅限 71M6542F/G。
Vcrosstalk = IAP-IAN 或
IBP-IBN 上的最大测量值
-10
10
μV/V
输入阻抗,无前置放大器
Vin=65 Hz
40
90
kΩ
ADC 增益误差与%电源偏差变动
10 6 ∆Nout PK 357nV / VIN
100 ∆V 3P3 A / 3.3
Vin=200mV pk, 65Hz
V3P3A=3.0V, 3.6V
50
ppm / %
输入偏移
IADC0=IADC1=V3P3A
IADC0=V3P3A
THD @ 250mVpk
DIFF0_E=1, PRE_E=0
DIFF0_E=0, PRE_E=0
10
10
mV
mV
推荐输入范围
(Vin - V3P3A)
电压至电流串扰
6
10 *Vcrosstalk
cos(∠Vin − ∠Vcrosstalk )
Vin
(见注释 1)
名称
A
B
C
D
E
F
G
H
J
FIR_LEN
0
1
0
1
2
0
0
1
2
ADC_DIV
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
THD @ 20mVpk
名称
A
B
C
D
E
F
G
H
J
FIR_LEN
0
1
0
1
2
0
0
1
2
ADC_DIV
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
VIN = 65Hz, 250mVpk,
64kpts FFT, Blackman
Harris 窗
VIN = 65Hz, 20mVpk,
64kpts FFT, Blackman
Harris 窗
最小值
典型值
-10
-10
A
B
C
D
E
F
G
H
J
-82
-84
-83
-86
A
B
C
D
E
F
G
H
J
-75
-75
-75
-75
-75
-75
-75
-75
-75
dB
A
B
C
D
E
F
G
H
J
-85
-91
-85
-91
-93
-85
-85
-91
-93
dB
A
B
C
D
E
F
G
H
J
3470
406
3040
357
151
3470
3040
357
151
nV
LSB 大小:
名称
A
B
C
D
E
F
G
H
J
FIR_LEN
0
1
0
1
2
0
0
1
2
ADC_DIV
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
数字满幅:
名称
A
B
C
D
E
F
G
H
J
Rev 2
FIR_LEN
0
1
0
1
2
0
0
1
2
ADC_DIV
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
Vin=65Hz, 20mVpk,
64kpts FFT, BlackmanHarris 窗
A: ±91125
B: ±778688
C: ±103823
D: ±884736
E:
±2097152
F: ±91125
G: ±103823
H: ±884736
J: ±2097152
LSB
149
71M6541D/F/G 和 71M6542F/G 数据资料
注:
1. 由设计保证,非产品测试。
2. 除非特别说明,以下测试条件适用于本表中的全部参数:FIR_LEN[1:0]=1,VREF_DIS=0,
PLL_FAST=1,ADC_DIV=0,MUX_DIV=6,LSB 值不包括 CE 输入处的 9 位左移位。
6.4.16 IAP-IAN前置放大器
表 111. 前置放大器技术指标
参数
差分增益
Vin=30mV 差分
Vin=15mV 差分(参见注释 1)
增益与 V3P3 的关系
Vin=30mV 差分(参见注释 1)
增益随温度的变化关系
Vin=30mV 差分(参见注释 1)
相移
Vin=30mV 差分(参见注释 1)
前置放大器输入电流
IADC0
IADC1
前置放大器+ADC THD
Vin=30mV 差分
Vin=15mV 差分
前置放大器失调
IADC0=IADC1=V3P3+30mV
IADC0=IADC1= V3P3+15mV
IADC0=IADC1= V3P3
IADC0=IADC1= V3P3-15mV
IADC0=IADC1= V3P3-30mV
注:
1. 由设计保证,非产品测试。
150
条件
TA= +25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz 采样率
V3P3 =
2.97 V, 3.63 V
TA = -40⁰C, 85⁰C
TA=25⁰C,
V3P3=3.3 V
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1
2520Hz 采样率,
IADC0=IADC1=V3
P3
TA=25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz 采样率
TA=25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz 采样率
最小值
典型值
最大值
单位
7.8
7.8
7.92
7.92
8.0
8.0
V/V
V/V
100
ppm/%
-80
ppm/C
6
mº
16
16
μA
μA
-100
10
-25
-6
4
4
9
9
-82
-86
dB
dB
-0.63
-0.57
-0.56
-0.56
-0.55
mV
mV
mV
mV
mV
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
6.5
时序规格
6.5.1
闪存
表 112. 闪存时序指标
参数
条件
最小值
典型值
最大值
单位
FLASH 写循环
-40°C 至+85°C
20,000
循环
FLASH 数据保持
25°C
85°C
100
10
年
页或整体擦除之间的 FLASH 字节写
2
循环
写时间/字节
21
µs
页擦除(1024 字节)
21
ms
整体擦除
21
Ms
6.5.2
SPI从机
表 113. SPI 从机指标
参数
SPI 建立时间
SPI 保持时间
SPI 输出延迟
SPI 恢复时间
SPI 断开时间
SPI 时钟高电平
SPI 时钟低电平
SPI 时钟频率
SPI 通信间隔
6.5.3
条件
SPI_DI 至 SPI_CK 上升
SPI_CK 上升至 SPI_DI
SPI_CK 下降至 SPI_D0
SPI_CSZ 下降至 SPI_CK
SPI_CK 至 SPI_CSZ 上升
最小值
10
10
SPI 频率/MPU 频率
SPI_CSZ 上升至 SPI_CSZ 下降
典型值
最大值
40
10
15
40
40
2.0
4.5
单位
ns
ns
ns
ns
ns
ns
ns
MHz/MHz
MPU 周期
EEPROM接口
表 114. EEPROM 接口时序
参数
条件
CKMPU = 4.9 MHz,
使用中断
写时钟频率(I2C)
写时钟频率(3 线)
Rev 2
CKMPU = 4.9 MHz,
逐位仿真:DIO2/3
PLL_FAST = 0
CKMPU = 4.9 MHz
PLL_FAST = 0
PLL_FAST = 1
最小值
典型值
最大值
单位
310
kHz
100
kHz
160
500
kHz
151
71M6541D/F/G 和 71M6542F/G 数据资料
6.5.4
RESET引脚
表 115. RESET 引脚时序
参数
条件
复位脉冲宽度
最小值
典型值
单位
1
µs
µs
5
复位脉冲下降时间(见注释 1)
注:
1. 由设计保证,非产品测试。
6.5.5
最大值
RTC
表 116. RTC 的日期范围
参数
日期范围
152
条件
最小值
典型
值
最大值
单位
2000
-
2255
年
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
6.6
封装图
6.6.1
64 引脚LQFP封装图
11.7
12.3
11.7
+
12.3
PIN No. 1 Indicator
9.8
10.2
0.50 Typ.
0.60 Typ.
0.00
0.20
0.14
0.28
1.40
1.60
图 47. 64 引脚 LQFP 封装
Rev 2
153
71M6541D/F/G 和 71M6542F/G 数据资料
6.6.2
100 引脚LQFP封装图
尺寸单位为 mm。
15.7(0.618)
16.3(0.641)
1
15.7(0.618)
16.3(0.641)
Top View
14.000 +/- 0.200
MAX. 1.600
1.50 +/- 0.10
0.225 +/- 0.045
0.50 TYP.
0.10 +/- 0.10
0.60 TYP>
Side View
图 48. 100 引脚 LQFP 封装图
154
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
封装标识
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
6.7
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
71M6542G-IGT
110124TK
445AP
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
71M6541DIGT.428AB
104224TH
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
图 49. 封装标识(示例)
图 49 给出了 64 引脚和 100 引脚封装的标识示例。封装标识由三行文字组成,参见表 117 和表 118 的说明。
表 117. 71M6541 封装标识
行数
标识
说明
1
71M6541D-
2
IGT.428AB
器件型号(‘IGT’位于下一行)
参见表 122。
小数点右侧的五个字符(即 428AB)为批次
代码。
3
104224TH
左侧前四个数字为生产年份和星期(YYWW
格式)。此例中,日期代码为 1042,表示
2010 年第 42 个星期。
最后四个字符(即 24TH)保留为 Maxim 内
部使用。
表 118. 71M6542 封装标识
行数
标识
1
71M6542G-IGT
2
110124TK
说明
器件型号,参见表 122。
左侧前四个数字为生产年份和星期(YYWW
格式)。此例中,日期代码为 1101,表示
2011 年第 1 个星期。
最后四个字符(即 24TK)保留为 Maxim 内
部使用。
3
Rev 2
445AP
五个字符表示批次代码。
155
71M6541D/F/G 和 71M6542F/G 数据资料
引脚图
6.8.1
71M6541D/F/G LQFP-64 封装引脚排列
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SPI_CKI/SEGDIO39
SEGDIO44
SEGDIO45
TMUX2OUT/SEG46
TMUXOUT/SEG47
RESET
PB
VLCD
VREF
IAP
IAN
V3P3A
VA
TEST
GNDA
XOUT
6.8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Teridian
71M6541D
71M6541F
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
XIN
VBAT_RTC
VBAT
V3P3SYS
IBP
IBN
GNDD
V3P3D
VDD
ICE_E
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
RX
TX
OPT_TX/SEGDIO51
SEGDIO14
SEGDIO13
SEGDIO12
SEGDIO11
SEGDIO10
SEGDIO9
SEGDIO8/DI
SEGDIO7/YPULSE
SEGDIO6/XPULSE
SEGDIO5
SEGDIO4
SEGDIO3/SDATA
SEGDIO2/SDCK
SEGDIO1/VPULSE
SEGDIO0/WPULSE
OPT_RX/SEGDIO55
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SPI_DI/SEGDIO38
SPI_DO/SEGDIO37
SPI_CSZ/SEGDIO36
COM0
COM1
COM2
COM3
SEGDIO27/COM4
SEGDIO26/COM5
SEGDIO25
SEGDIO24
SEGDIO23
SEGDIO22
SEGDIO21
SEGDIO20
SEGDIO19
图 50. 71M6541D/F/G (LQFP-64 封装)引脚排列
156
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
71M6542F/G LQFP-100 封装引脚排列
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SPI_CKI/SEGDIO39
SEGDIO40
SEGDIO41
SEGDIO42
SEGDIO43
SEGDIO44
SEGDIO45
TMUX2OUT/SEG46
TMUXOUT/SEG47
RESET
PB
VLCD
VREF
IAP
IAN
V3P3A
NC
VB
VA
TEST
GNDA
NC
NC
NC
XOUT
6.8.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Teridian
71M6542F
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
XIN
NC
NC
GNDA
VBAT_RTC
VBAT
V3P3SYS
IBP
IBN
NC
NC
NC
NC
GNDD
V3P3D
VDD
ICE_E
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
RX
TX
OPT_TX/SEGDIO51
SEGDIO52
SEGDIO53
NC
SEGDIO17
SEGDIO16
SEGDIO15
SEGDIO14
SEGDIO13
SEGDIO12
SEGDIO11
SEGDIO10
SEGDIO9
SEGDIO8/DI
SEGDIO7/YPULSE
SEGDIO6/XPULSE
SEGDIO5
NC
SEGDIO4
SEGDIO3/SDATA
SEGDIO2/SDCK
SEGDIO1/VPULSE
SEGDIO0/WPULSE
OPT_RX/SEGDIO55
SEGDIO54
NC
NC
NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SPI_DI/SEGDIO38
SPI_DO/SEGDIO37
SPI_CSZ/SEGDIO36
SEGDIO35
SEGDIO34
SEGDIO33
SEGDIO32
SEGDIO31
SEGDIO30
SEGDIO29
SEGDIO28
COM0
COM1
COM2
COM3
SEGDIO27/COM4
SEGDIO26/COM5
SEGDIO25
SEGDIO24
SEGDIO23
SEGDIO22
SEGDIO21
SEGDIO20
SEGDIO19
SEGDIO18
图 51. 71M6542F/G (LQFP-100 封装)引脚排列
Rev 2
157
71M6541D/F/G 和 71M6542F/G 数据资料
6.9
引脚说明
6.9.1
电源和接地引脚
引脚类型:P = 电源,O = 输出,I = 输入,I/O = 输入/输出。
电路编号表示等效电路,如第 6.9.4 节的 I/O 等效电路。
.
表 119. 电源和接地引脚
引脚
引脚
(64 引脚)
(100 引脚)
50
72, 80
42
名称
类型
电路
说明
GNDA
P
–
模拟地:该引脚应直接连接至接地区域。
62
GNDD
P
–
数字地:该引脚应直接连接至接地区域。
53
85
V3P3A
P
–
模拟电源:将一路 3.3V 电源连接至该引脚。V3P3A
必须与 V3P3SYS 电压相同。
45
69
V3P3SYS
P
–
系统 3.3V 电源,该引脚连接至 3.3V 电源。
41
61
V3P3D
O
13
芯片辅助电压输出。MSN 模式下,该引脚通过内部选
择开关连接至 V3P3SYS;BRN 模式下,内部连接至
VBAT;LCD 和休眠模式下,V3P3D 浮空。该引脚和
地之间必须连接 0.1μF 旁路电容。
40
60
VDD
O
–
2.5V 稳压器输出。MSN 和 BRN 模式下,该引脚供
电。在该引脚和地之间连接 0.1μF 旁路电容。
57
89
VLCD
O
–
LCD DAC 输出。在该引脚和地之间连接 0.1μF 旁路
电容。
46
70
VBAT
P
12
备份电池引脚,支持电池模式(BRN、LCD)。VBAT
和 GNDD 之间连接电池或超级电容。如果未使用电
池,将 VBAT 连接至 V3P3SYS。
47
71
VBAT_RTC
P
12
RTC 和振荡器电源。VBAT 和 GNDD 之间接电池或
超级电容。如果未使用电池,将 VBAT_RTC 连接至
V3P3SYS。
158
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
6.9.2
模拟电路引脚
表 120. 模拟电路引脚
引脚
引脚
(64 引脚)
(100 引脚)
电路
说明
I
6
VA
VB†
I
6
电网电压检测输入:这些引脚为电压输入,送入内部 A/D
转换器。通常情况下,连接到电阻分压输出。未使用的
引脚必须连接至 V3P3A。
VREF
O
9
ADC 电压基准。该引脚应保持浮空,同时将 VREF_CAL
清 0。
8
晶振输入:在这些引脚之间应连接 32kHz 晶体。通常情
况下,在 XIN 和 GNDA 之间连接 15pF 电容,在 XOUT
和 GNDA 之间连接 10pF 电容。将这些引脚之间的电容
最小化非常重要,详细信息请参见晶体制造商的数据资
料。如果使用外部时钟,应将 150mV (p-p)时钟信号加至
XIN,XOUT 应保持浮空。
87
86
IAPIAN
44
43
68
67
IBPIBN
52
--
82
83
56
88
75
76
类型
差分或单端电网电流检测输入。这些引脚为电压输入,
至内部 A/D 转换器。通常情况下,连接至电流传感器输
出。未使用的引脚必须连接至 V3P3A。
IBP-IBN 可配置为与远端传感器接口(71M6x01)通信。
RMT_E = 1 (I/O RAM 0x2709[3])时,IBP-IBN 引脚变为平
衡差分对。如果未使用,必须将 RMT_E 清 0,且 IBPIBN 必须连接至 V3P3A。
55
54
48
49
†
名称
XIN
XOUT
I
O
VB 引脚仅在 71M6542F/G 可用。
Rev 2
159
71M6541D/F/G 和 71M6542F/G 数据资料
6.9.3
数字电路引脚
表 121 列出了数字引脚。引脚类型:P = 电源,O = 输出,I = 输入,I/O = 输入/输出,N/C = 没有连接。
电路编号表示等效电路,如第 6.9.4 节的 I/O 等效电路。
表 121. 数字电路引脚
引脚
(64 引脚)
引脚
(100 引脚)
名称
类型
电路
4-7
12–15
COM0–COM3
O
5
31
45
SEGDIO0/WPULSE
30
44
SEGDIO1/VPULSE
29
43
SEGDIO2/SDCK
28
42
SEGDIO3/SDATA
27
41
SEGDIO4
26
39
SEGDIO5
25
38
SEGDIO6/XPULSE
24
37
SEGDIO7/YPULSE
23
36
SEGDIO8/DI
22-17
35–30
SEGDIO[9:14]
--
29-27
SEGDIO[15:17]
--
25
SEGDIO[18]
16-10
24–18
SEGDIO[19:25]
--
11–4
SEGDIO[28:35]
63-62
95-94
SEGDIO[44:45]
--
99–96
SEGDIO[40:43]
--
52
SEGDIO52
--
51
SEGDIO53
--
47
SEGDIO54
9
17
SEGDIO26/COM5
8
16
SEGDIO27/COM4
3
3
SPI_CSZ/SEGDIO36
2
2
SPI_DO/SEGDIO37
1
1
SPI_DI/SEGDIO38
64
100
SPI_CKI/SEGDIO39
33
53
OPT_TX/SEGDIO51
32
46
OPT_RX/SEGDIO55
38
36
37
58
56
57
E_RXTX/SEG48
E_RST/SEG50
E_TCLK/SEG49
160
I/O
3, 4, 5
功能
LCD 共用输出,这四个引脚为 LCD 显示提供选择信号。
多功能引脚,配置为 LCD 段驱动器或 DIO。复用功能引脚
(需要配置相关 I/O RAM 寄存器启用):
SEGDIO0 = WPULSE
SEGDIO1 = VPULSE
SEGDIO2 = SDCK
SEGDIO3 = SDATA
SEGDIO6 = XPULSE
SEGDIO7 = YPULSE
SEGDIO8 = DI
未使用的引脚必须配置为输出或端接至 V3P3/GNDD。
I/O
3, 4, 5
多功能引脚,配置为 LCD 段驱动器或第二功能 DIO (LCD
共用驱动器)。
I/O
3, 4, 5
多功能引脚,配置为 LCD 段驱动器或第二功能 DIO (SPI
接口)。
I/O
3, 4, 5
多功能引脚,配置为 LCD 段驱动器或第二功能 DIO (光端
口/UART1)。
I/O
1, 4, 5
O
4, 5
多功能引脚,配置为仿真端口(ICE_E 拉高时)或 LCD 段驱
动器(ICE_E 接 GND)。
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
引脚
(64 引脚)
引脚
(100 引脚)
名称
类型
电路
功能
I
2
CE 使能。为低电平时,E_RST、E_TCLK 和 E_RXTX 分
别变为 SEG50、SEG49 和 SEG48。对于生产单元,该引
脚应拉低至 GND,禁用仿真端口。
O
4, 5
多功能引脚。配置为复用器/时钟输出或 LCD 段驱动器(使
用 I/O RAM 寄存器)。
39
59
ICE_E
60
92
TMUXOUT/SEG47
61
93
TMUX2OUT/SEG46
59
91
RESET
I
2
芯片复位引脚,高有效。该输入引脚用于将芯片复位至已
知状态。为正常工作,该引脚拉低。该引脚具有内部 30μA
(标称值)电流源拉低。无需外部复位电路。
35
55
RX
I
3
UART0 输 入 。 如 果 不 使 用 该 引 脚 , 必 须 将 其 端 接 至
V3P3D 或 GNDD。
34
54
TX
O
4
UART0 输出。
51
81
TEST
I
7
芯片生产测试引脚,正常工作时,该引脚必须接地。
58
90
PB
I
3
按键输入。不使用时接地。上升沿置位 WF_PB 标识。如果
器件处于 SLP 或 LCD 模式,亦使器件唤醒。PB 没有内部
上拉或下拉电阻。
--
26, 40, 48,
49, 50, 63,
64, 65,
66, 73, 74,
77, 78, 79,
84
NC
N/C
—
未连接。请勿连接该引脚。
Rev 2
161
71M6541D/F/G 和 71M6542F/G 数据资料
6.9.4
I/O等效电路
V3P3D
V3P3A
V3P3D
110K
Digital
Input
Pin
CMOS
Input
from
internal
reference
LCD SEG
Output
Pin
LCD
Driver
VREF
Pin
GNDD
GNDA
GNDD
LCD Output Equivalent Circuit
Type 5:
LCD SEG or
pin configured as LCD SEG
Digital Input Equivalent Circuit
Type 1:
Standard Digital Input or
pin configured as DIO Input
with Internal Pull-Up
VREF Equivalent Circuit
Type 9:
VREF
V3P3A
V3P3D
V3P3D
Digital
Input
Pin
CMOS
Input
Analog
Input
Pin
GNDD
GNDD
Analog Input Equivalent Circuit
Type 6:
ADC Input
Digital Input
Type 2:
Pin configured as DIO Input
with Internal Pull-Down
V2P5 Equivalent Circuit
Type 10:
V2P5
V3P3A
V3P3D
Comparator
Input
Pin
To
Comparator
VLCD
Pin
LCD
Drivers
GNDA
Digital
Input
Pin
V2P5
Pin
GNDA
110K
GNDD
from
internal
reference
To
MUX
CMOS
Input
GNDD
Comparator Input Equivalent
Circuit Type 7:
Comparator Input
VLCD Equivalent Circuit
Type 11:
VLCD Power
GNDD
Oscillator
Pin
Digital Input Type 3:
Standard Digital Input or
pin configured as DIO Input
To
Oscillator
Power
Down
Circuits
VBAT
Pin
GNDD
GNDD
V3P3D
Oscillator Equivalent Circuit
Type 8:
Oscillator I/O
V3P3D
10
Digital
Output
Pin
CMOS
Output
from
V3P3SYS
V3P3D
Pin
GNDD
GNDD
VBAT Equivalent Circuit
Type 12:
VBAT Power
40
from
VBAT
Digital Output Equivalent Circuit
Type 4:
Standard Digital Output or
pin configured as DIO Output
V3P3D Equivalent Circuit
Type 13:
V3P3D
图 52. I/O 等效电路
162
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
7
定购信息
7.1
71M6541D/F/G和 71M6542F/G
表 122. 定购信息
器件说明
(封装,精度)
器件
71M6541D
64-pin LQFP Lead-Free, 0.5%
71M6541D
64-pin LQFP Lead-Free, 0.5%
71M6541F
64-pin LQFP Lead-Free, 0.5%
71M6541F
64-pin LQFP Lead-Free, 0.5%
71M6541G* 64-pin LQFP Lead-Free, 0.5%
71M6541G* 64-pin LQFP Lead-Free, 0.5%
71M6542F
100-pin LQFP Lead-Free, 0.5%
71M6542F
100-pin LQFP Lead-Free, 0.5%
71M6542G
100-pin LQFP Lead-Free, 0.5%
71M6542G
100-pin LQFP Lead-Free, 0.5%
FLASH
大小
封装
32 KB bulk
tape and
32 KB
reel
64 KB bulk
tape and
64 KB
reel
128 KB bulk
tape and
128 KB
reel
64 KB bulk
tape and
64 KB
reel
bulk
128 KB
tape and
128 KB
reel
型号
封装标记
71M6541D-IGT/F
71M6541D-IGT
71M6541D-IGTR/F 71M6541D-IGT
71M6541F-IGT/F
71M6541F-IGT
71M6541F-IGTR/F 71M6541F-IGT
71M6541G-IGT/F
71M6541G-IGT
71M6541G-IGTR/F 71M6541G-IGT
71M6542F-IGT/F
71M6542F-IGT
71M6542F-IGTR/F 71M6542F-IGT
71M6542G-IGT/F
71M6542G-IGT
71M6542G-IGTR/F 71M6542G-IGT
*未来产品—供货状况请与工厂联系。
相关信息
8
用户需使用以下与 71M6541D/F/G 和 71M6542F/G 相关的文档:
•
•
•
•
71M6541D/F/G 和 71M6542F/G 数据资料(本文档)
71M6xxx 数据资料
71M6541 演示板用户手册
71M654x 软件用户指南
9
联络信息
关于 Maxim 产品的更多信息,或了解 71M6541D/F/G 和 71M6542F/G 供货状况,请联系技术支持:
http://www.maxim-ic.com/cn/support。
Rev 2
163
71M6541D/F/G 和 71M6542F/G 数据资料
附录A:缩写符号
AFE
AMR
ANSI
CE
DIO
DSP
FIR
I2C
ICE
IEC
MPU
PLL
RMS
SFR
SOC
SPI
TOU
UART
164
模拟前端
自动抄表
美国国家标准学会
计算引擎
数字 I/O
数字信号处理器
有限冲激响应
内部 IC 总线
在线仿真器
国际电工委员会
微处理器单元(CPU)
锁相环
均方根
特殊功能寄存器
片上系统
串行外设接口
分时计费
通用异步收发器
Rev 2
71M6541D/F/G 和 71M6542F/G 数据资料
附录B:修订历史
修订号
修订日期
1.0
3/11
最初版本。
—
4/11
删除了特性部分关于休眠模式下 3.3V 典型功耗为 18mW 的信
息。
1
1.1
说明
更新表 99 中的温度测量公式和温度误差参数。
2
Rev 2
11/11
将 71M6542G 的状态改为生产中(表 122)。
在全文的适当位置增加了 71M6541G/2G 内容。
在奇数页和偶数页补充加入了数据资料标题页眉。
更正了之前 v1.1 版本中的错误(参见修改页)。
在第 155 页增加了 6.7 一节。
修改页
141
1, 9, 10, 27,
49, 54, 56,
62, 97, 120
165
71M6541D/F/G 和 71M6542F/G 数据资料
Maxim 不对 Maxim 产品以外的任何电路使用负责,也不提供其专利许可。Maxim 保留在任何时间、没有任何通报的前提下修改产品
资料和规格的权利。
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
 2011 Maxim Integrated Products
是 Maxim Integrated Products 的注册商标。
19-5376; Rev 2; 11/11
71M6541D/F/G and 71M6542F/G
Energy Meter ICs
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are
Teridian™ 4th-generation single-phase metering SoCs with a 5MHz
8051-compatible MPU core, low-power RTC with digital temperature
compensation, flash memory, and LCD driver. Our Single Converter
Technology® with a 22-bit delta-sigma ADC, three or four analog
inputs, digital temperature compensation, precision voltage reference,
and a 32-bit computation engine (CE) supports a wide range of
metering applications with very few external components.
The 71M6541/2 devices support optional interfaces to the Teridian
71M6x01 series of isolated sensors, which offer BOM cost reduction,
immunity to magnetic tamper, and enhanced reliability. Other
features include an SPI interface, advanced power management,
ultra-low-power operation in active and battery modes, 3/5KB shared
RAM and 32/64/128KB of flash memory that can be programmed in
the field with code and/or data during meter operation and the ability
to drive up to six LCD segments per SEG driver pin. High
processing and sampling rates combined with differential inputs offer
a powerful metering platform for residential meters.
A complete array of code development tools, demonstration code,
and reference designs enable rapid development and certification of
meters that meet all ANSI and IEC electricity metering standards
worldwide.
NEUTRAL
Shunt
LOAD
Note:
This system is referenced to LINE
Shunt
LINE
NEUTRAL
POWER SUPPLY
LINE
Resistor Divider
LINE
• 0.1% Accuracy Over 2000:1 Current Range
• Exceeds IEC 62053/ANSI C12.20 Standards
• Two Current Sensor Inputs with Selectable
Differential Mode
• Selectable Gain of 1 or 8 for One Current Input to
Support Shunts
• High-Speed Wh/VARh Pulse Outputs with
Programmable Width
• 32KB Flash, 3KB RAM (71M6541D)
• 64KB Flash, 5KB RAM (71M6541F/42F)
• 128KB Flash, 5KB RAM (71M6541G/42G)
• Up to Four Pulse Outputs with Pulse Count
• Four-Quadrant Metering
• Digital Temperature Compensation:
Metrology Compensation
Accurate RTC for TOU Functions with
Automatic Temperature Compensation for
Crystal in All Power Modes
• Independent 32-Bit Compute Engine
• 46-64Hz Line Frequency Range with the Same
Calibration
• Phase Compensation (±10°)
• Three Battery-Backup Modes:
Brownout Mode (BRN)
LCD Mode (LCD)
Sleep Mode (SLP)
• Wake-Up on Pin Events and Wake-On Timer
• 1µA in Sleep Mode
TERIDIAN
71M6xx1
MUX and ADC
V3P3A V3P3SYS GNDA GNDD
• Flash Security
PWR MODE
CONTROL
IAP
IAN
Pulse
Transformer
TERIDIAN
WAKE-UP
71M6541D/F
REGULATOR
• In-System Program Update
BATTERY
VBAT
VA
VBAT_RTC
IBP
IBN
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
AMR
IR
TX
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
RAM
COMPUTE
ENGINE
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
• Full-Speed MPU Clock in Brownout Mode
• LCD Driver:
2
V3P3D
OSCILLATOR/
PLL
XIN
• 8-Bit MPU (80515), Up to 5 MIPS
XOUT
11/5/2010
Teridian is a trademark and Single Converter Technology is a registered trademark of
Maxim Integrated Products, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
- Up to 6 Commons/Up to 56 Pins
• 5V LCD Driver with DAC
• Up to 51 Multifunction DIO Pins
• Hardware Watchdog Timer (WDT)
2
• I C/MICROWIRE® EEPROM Interface
• SPI Interface with Flash Program Capability
• Two UARTs for IR and AMR
• IR LED Driver with Modulation
• Industrial Temperature Range
• 64-Pin (71M6541D/F/G) and 100-pin
(71M6542F/G) Lead(Pb)-Free LQFP Package
Rev 2
1
71M6541D/F/G and 71M6542F/G Data Sheet
Table of Contents
1
2
3
2
Introduction ................................................................................................................................. 10
Hardware Description .................................................................................................................. 11
2.1 Hardware Overview............................................................................................................... 11
2.2 Analog Front End (AFE) ........................................................................................................ 12
2.2.1 Signal Input Pins ....................................................................................................... 14
2.2.2 Input Multiplexer ........................................................................................................ 15
2.2.3 Delay Compensation ................................................................................................. 19
2.2.4 ADC Pre-Amplifier ..................................................................................................... 20
2.2.5 A/D Converter (ADC) ................................................................................................. 20
2.2.6 FIR Filter ................................................................................................................... 20
2.2.7 Voltage References ................................................................................................... 20
2.2.8 71M6x01 Isolated Sensor Interface (Remote Sensor Interface).................................. 22
2.3 Digital Computation Engine (CE) ........................................................................................... 24
2.3.1 CE Program Memory ................................................................................................. 24
2.3.2 CE Data Memory ....................................................................................................... 24
2.3.3 CE Communication with the MPU .............................................................................. 25
2.3.4 Meter Equations ........................................................................................................ 25
2.3.5 Real-Time Monitor (RTM) .......................................................................................... 25
2.3.6 Pulse Generators ...................................................................................................... 27
2.3.7 CE Functional Overview ............................................................................................ 28
2.4 80515 MPU Core .................................................................................................................. 31
2.4.1 Memory Organization and Addressing ....................................................................... 31
2.4.2 Special Function Registers (SFRs) ............................................................................ 33
2.4.3 Generic 80515 Special Function Registers ................................................................ 34
2.4.4 Instruction Set ........................................................................................................... 36
2.4.5 UARTs ...................................................................................................................... 36
2.4.6 Timers and Counters ................................................................................................. 39
2.4.7 WD Timer (Software Watchdog Timer) ...................................................................... 40
2.4.8 Interrupts................................................................................................................... 40
2.5 On-Chip Resources............................................................................................................... 48
2.5.1 Physical Memory ....................................................................................................... 48
2.5.2 Oscillator ................................................................................................................... 50
2.5.3 PLL and Internal Clocks............................................................................................. 50
2.5.4 Real-Time Clock (RTC) ............................................................................................. 51
2.5.5 71M654x Temperature Sensor .................................................................................. 56
2.5.6 71M654x Battery Monitor........................................................................................... 57
2.5.7 UART and Optical Interface ....................................................................................... 58
2.5.8 Digital I/O and LCD Segment Drivers......................................................................... 59
2.5.9 EEPROM Interface .................................................................................................... 70
2.5.10 SPI Slave Port ........................................................................................................... 73
2.5.11 Hardware Watchdog Timer ........................................................................................ 78
2.5.12 Test Ports (TMUXOUT and TMUX2OUT Pins)........................................................... 78
Functional Description ................................................................................................................ 80
3.1 Theory of Operation .............................................................................................................. 80
3.2 Battery Modes....................................................................................................................... 81
3.2.1 BRN Mode ................................................................................................................ 83
3.2.2 LCD Mode ................................................................................................................. 83
3.2.3 SLP Mode ................................................................................................................. 84
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
3.3
4
5
6
Fault and Reset Behavior ...................................................................................................... 85
3.3.1 Events at Power-Down .............................................................................................. 85
3.3.2 IC Behavior at Low Battery Voltage ........................................................................... 86
3.3.3 Reset Sequence ........................................................................................................ 86
3.3.4 Watchdog Timer Reset .............................................................................................. 86
3.4 Wake Up Behavior ................................................................................................................ 87
3.4.1 Wake on Hardware Events ........................................................................................ 87
3.4.2 Wake on Timer .......................................................................................................... 90
3.5 Data Flow and MPU/CE Communication ............................................................................... 91
Application Information ............................................................................................................... 92
4.1 Connecting 5 V Devices ........................................................................................................ 92
4.2 Direct Connection of Sensors ................................................................................................ 92
4.3 71M6541D/F/G Using Local Sensors..................................................................................... 93
4.4 71M6541D/F/G Using 71M6x01and Current Shunts .............................................................. 94
4.5 71M6542F/G Using Local Sensors ........................................................................................ 95
4.6 71M6542F/G Using 71M6x01 and Current Shunts................................................................. 96
4.7 Metrology Temperature Compensation.................................................................................. 97
4.7.1 Voltage Reference Precision ..................................................................................... 97
4.7.2 Temperature Coefficients for the 71M654x ................................................................ 97
4.7.3 Temperature Compensation for VREF with Local Sensors ......................................... 98
4.7.4 Temperature Compensation for VREF with Remote Sensor ....................................... 99
4.8 Connecting I2C EEPROMs .................................................................................................. 100
4.9 Connecting Three-Wire EEPROMs ..................................................................................... 101
4.10 UART0 (TX/RX) .................................................................................................................. 101
4.11 Optical Interface (UART1) ................................................................................................... 101
4.12 Connecting the Reset Pin.................................................................................................... 102
4.13 Connecting the Emulator Port Pins ...................................................................................... 102
4.14 Flash Programming ............................................................................................................. 104
4.14.1 Flash Programming via the ICE Port ........................................................................ 104
4.14.2 Flash Programming via the SPI Port ........................................................................ 104
4.15 MPU Firmware Library ........................................................................................................ 104
4.16 Crystal Oscillator ................................................................................................................. 104
4.17 Meter Calibration................................................................................................................. 104
Firmware Interface ..................................................................................................................... 105
5.1 I/O RAM Map –Functional Order ......................................................................................... 105
5.2 I/O RAM Map – Alphabetical Order ..................................................................................... 111
5.3 CE Interface Description ..................................................................................................... 125
5.3.1 CE Program ............................................................................................................ 125
5.3.2 CE Data Format ...................................................................................................... 125
5.3.3 Constants ................................................................................................................ 125
5.3.4 Environment ............................................................................................................ 126
5.3.5 CE Calculations....................................................................................................... 126
5.3.6 CE Front End Data (Raw Data)................................................................................ 127
5.3.7 FCE Status and Control ........................................................................................... 127
5.3.8 CE Transfer Variables ............................................................................................. 129
5.3.9 Pulse Generation..................................................................................................... 132
5.3.10 Other CE Parameters .............................................................................................. 134
5.3.11 CE Calibration Parameters ...................................................................................... 135
5.3.12 CE Flow Diagrams .................................................................................................. 136
Electrical Specifications ............................................................................................................ 138
Rev 2
3
71M6541D/F/G and 71M6542F/G Data Sheet
6.1
6.2
6.3
6.4
Absolute Maximum Ratings ................................................................................................. 138
Recommended External Components ................................................................................. 139
Recommended Operating Conditions .................................................................................. 139
Performance Specifications ................................................................................................. 140
6.4.1 Input Logic Levels ................................................................................................... 140
6.4.2 Output Logic Levels................................................................................................. 140
6.4.3 Battery Monitor ........................................................................................................ 141
6.4.4 Temperature Monitor ............................................................................................... 141
6.4.5 Supply Current ........................................................................................................ 142
6.4.6 V3P3D Switch ......................................................................................................... 143
6.4.7 Internal Power Fault Comparators ........................................................................... 143
6.4.8 2.5 V Voltage Regulator – System Power ................................................................ 143
6.4.9 2.5 V Voltage Regulator – Battery Power ................................................................. 144
6.4.10 Crystal Oscillator ..................................................................................................... 144
6.4.11 Phase-Locked Loop (PLL) ....................................................................................... 144
6.4.12 LCD Drivers ............................................................................................................ 145
6.4.13 VLCD Generator...................................................................................................... 146
6.4.14 VREF ...................................................................................................................... 148
6.4.15 ADC Converter ........................................................................................................ 149
6.4.16 Pre-Amplifier for IAP-IAN ......................................................................................... 150
6.5 Timing Specifications .......................................................................................................... 151
6.5.1 Flash Memory ......................................................................................................... 151
6.5.2 SPI Slave ................................................................................................................ 151
6.5.3 EEPROM Interface .................................................................................................. 151
6.5.4 RESET Pin .............................................................................................................. 152
6.5.5 RTC ........................................................................................................................ 152
6.6 Package Outline Drawings .................................................................................................. 153
6.6.1 64-Pin LQFP Outline Package Drawing ................................................................... 153
6.6.2 100-Pin LQFP Package Outline Drawing ................................................................. 154
6.7 Package Markings .............................................................................................................. 155
6.8 Pinout Diagrams ................................................................................................................. 156
6.8.1 71M6541D/F/G LQFP-64 Package Pinout ............................................................... 156
6.8.2 71M6542F/G LQFP-100 Package Pinout ................................................................. 157
6.9 Pin Descriptions .................................................................................................................. 158
6.9.1 Power and Ground Pins........................................................................................... 158
6.9.2 Analog Pins ............................................................................................................. 159
6.9.3 Digital Pins .............................................................................................................. 160
6.9.4 I/O Equivalent Circuits ............................................................................................. 162
7
Ordering Information ................................................................................................................. 163
7.1 71M6541D/F/G and 71M6542F/G ....................................................................................... 163
8
Related Information ................................................................................................................... 163
9
Contact Information ................................................................................................................... 163
Appendix A: Acronyms ..................................................................................................................... 164
Appendix B: Revision History ........................................................................................................... 165
4
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Figures
Figure 2. 71M6541D/F/G AFE Block Diagram (Local Sensors) ............................................................... 12
Figure 3. 71M6541D/F/G AFE Block Diagram with 71M6x01.................................................................. 13
Figure 4. 71M6542F/G AFE Block Diagram (Local Sensors) .................................................................. 13
Figure 5. 71M6542F/G AFE Block Diagram with 71M6x01 ..................................................................... 14
Figure 6: States in a Multiplexer Frame (MUX_DIV[3:0] = 3) .................................................................. 17
Figure 7: States in a Multiplexer Frame (MUX_DIV[3:0] = 4) .................................................................. 17
Figure 8: General Topology of a Chopped Amplifier ............................................................................... 21
Figure 9: CROSS Signal with CHOP_E = 00........................................................................................... 21
Figure 10: RTM Timing .......................................................................................................................... 26
Figure 11: Timing relationship between ADC MUX, CE, and RTM Serial Transfer .................................. 26
Figure 12. Pulse Generator FIFO Timing ............................................................................................... 28
Figure 13: Accumulation Interval ............................................................................................................ 29
Figure 14: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 3)............................................................. 30
Figure 15: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 4)............................................................. 30
Figure 16: Interrupt Structure ................................................................................................................. 47
Figure 17: Automatic Temperature Compensation ................................................................................. 54
Figure 18: Optical Interface.................................................................................................................... 58
Figure 19: Optical Interface (UART1) ..................................................................................................... 59
Figure 20: Connecting an External Load to DIO Pins ............................................................................. 60
Figure 21: LCD Waveforms ................................................................................................................... 68
Figure 22: 3-wire Interface. Write Command, HiZ=0. ............................................................................. 72
Figure 23: 3-wire Interface. Write Command, HiZ=1 .............................................................................. 72
Figure 24: 3-wire Interface. Read Command. ........................................................................................ 72
Figure 25: 3-Wire Interface. Write Command when CNT=0 ................................................................... 73
Figure 26: 3-wire Interface. Write Command when HiZ=1 and WFR=1. ................................................. 73
Figure 27: SPI Slave Port - Typical Multi-Byte Read and Write operations.............................................. 75
Figure 28: Voltage, Current, Momentary and Accumulated Energy......................................................... 80
Figure 29: Operation Modes State Diagram ........................................................................................... 81
Figure 30: MPU/CE Data Flow ............................................................................................................... 91
Figure 31: Resistive Voltage Divider (Voltage Sensing) .......................................................................... 92
Figure 32. CT with Single-Ended Input Connection (Current Sensing) .................................................... 92
Figure 33: CT with Differential Input Connection (Current Sensing) ........................................................ 92
Figure 34: Differential Resistive Shunt Connections (Current Sensing)................................................... 92
Figure 35. 71M6541D/F/G with Local Sensors ....................................................................................... 93
Figure 36: 71M6541D/F/G with 71M6x01 isolated Sensor ...................................................................... 94
Figure 39: I2C EEPROM Connection.................................................................................................... 101
Figure 40: Connections for UART0 ...................................................................................................... 101
Figure 41: Connection for Optical Components .................................................................................... 102
Figure 42: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) ......... 102
Figure 43: External Components for the Emulator Interface ................................................................. 103
Figure 44: CE Data Flow: Multiplexer and ADC .................................................................................... 136
Figure 45: CE Data Flow: Scaling, Gain Control, Intermediate Variables .............................................. 136
Figure 46: CE Data Flow: Squaring and Summation Stages ................................................................. 137
Figure 47: 64-pin LQFP Package Outline ............................................................................................. 153
Figure 48: 100-pin LQFP Package Outline ........................................................................................... 154
Figure 49. Package Markings (Examples) ............................................................................................ 155
Figure 50: Pinout for the 71M6541D/F/G (LQFP-64 Package) .............................................................. 156
Figure 52: I/O Equivalent Circuits......................................................................................................... 162
Rev 2
5
71M6541D/F/G and 71M6542F/G Data Sheet
Tables
Table 1. Required CE Code and Settings for Local Sensors................................................................... 15
Table 2. Required CE Code and Settings for 71M6x01 isolated Sensor ................................................. 16
Table 3: ADC Input Configuration ......................................................................................................... 17
Table 4: Multiplexer and ADC Configuration Bits ................................................................................... 19
Table 5. RCMD[4:0] Bits ........................................................................................................................ 22
Table 6: Remote Interface Read Commands ........................................................................................ 23
Table 7: I/O RAM Control Bits for Isolated Sensor ................................................................................. 23
Table 8: Inputs Selected in Multiplexer Cycles ....................................................................................... 25
Table 9: CKMPU Clock Frequencies ...................................................................................................... 31
Table 10: Memory Map .......................................................................................................................... 32
Table 11: Internal Data Memory Map ..................................................................................................... 33
Table 12: Special Function Register Map ............................................................................................... 33
Table 13: Generic 80515 SFRs - Location and Reset Values ................................................................. 34
Table 14: PSW Bit Functions (SFR 0xD0)................................................................................................. 35
Table 15: Port Registers (SEGDIO0-15) ................................................................................................ 36
Table 16: Stretch Memory Cycle Width .................................................................................................. 36
Table 17: Baud Rate Generation............................................................................................................ 37
Table 18: UART Modes ......................................................................................................................... 37
Table 19: The S0CON (UART0) Register (SFR 0x98) ............................................................................. 38
Table 20: The S1CON (UART1) Register (SFR 0x9B) ............................................................................. 38
Table 21: PCON Register Bit Description (SFR 0x87) ............................................................................ 39
Table 22: Timers/Counters Mode Description ........................................................................................ 39
Table 23: Allowed Timer/Counter Mode Combinations ........................................................................... 39
Table 24: TMOD Register Bit Description (SFR 0x89) ............................................................................ 40
Table 25: The TCON Register Bit Functions (SFR 0x88) ........................................................................ 40
Table 26: The IEN0 Bit Functions (SFR 0xA8)........................................................................................ 41
Table 27: The IEN1 Bit Functions (SFR 0xB8)........................................................................................ 41
Table 28: The IEN2 Bit Functions (SFR 0x9A)........................................................................................ 42
Table 29: TCON Bit Functions (SFR 0x88) ............................................................................................. 42
Table 30: The T2CON Bit Functions (SFR 0xC8) ................................................................................... 42
Table 31: The IRCON Bit Functions (SFR 0xC0) .................................................................................... 42
Table 32: External MPU Interrupts ......................................................................................................... 44
Table 33: Interrupt Enable and Flag Bits ............................................................................................... 44
Table 34: Interrupt Priority Level Groups ................................................................................................ 45
Table 35: Interrupt Priority Levels .......................................................................................................... 45
Table 36: Interrupt Priority Registers (IP0 and IP1) ................................................................................. 45
Table 37: Interrupt Polling Sequence ..................................................................................................... 46
Table 38: Interrupt Vectors .................................................................................................................... 46
Table 39: Flash Memory Access ............................................................................................................ 48
Table 40: Flash Security ........................................................................................................................ 49
Table 41: Clock System Summary ......................................................................................................... 51
Table 42: RTC Control Registers ........................................................................................................... 52
Table 43: I/O RAM Registers for RTC Temperature Compensation ........................................................ 53
Table 44: NV RAM Temperature Table Structure ................................................................................... 54
Table 45: I/O RAM Registers for RTC Interrupts .................................................................................... 55
Table 46: I/O RAM Registers for Temperature and Battery Measurement .............................................. 56
Table 47: Selectable Resources using the DIO_Rn[2:0] Bits................................................................... 59
Table 48: Data/Direction Registers for SEGDIO0 to SEGDIO14 (71M6541D/F/G) .................................. 61
Table 49: Data/Direction Registers for SEGDIO19 to SEGDIO27 (71M6541D/F/G) ................................ 62
Table 50: Data/Direction Registers for SEGDIO36-39 to SEGDIO44-45 (71M6541D/F/G) ...................... 62
Table 51: Data/Direction Registers for SEGDIO51 and SEGDIO55 (71M6541D/F/G) ............................. 62
Table 52: Data/Direction Registers for SEGDIO0 to SEGDIO15 (71M6542F/G) ..................................... 63
6
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 53: Data/Direction Registers for SEGDIO16 to SEGDIO31 (71M6542F/G) ................................... 64
Table 54: Data/Direction Registers for SEGDIO32 to SEGDIO45 (71M6542F/G) ................................... 64
Table 55: Data/Direction Registers for SEGDIO51 to SEGDIO55 (71M6542F/G) ................................... 64
Table 56: LCD_VMODE[1:0] Configurations .......................................................................................... 65
Table 57: LCD Configurations ............................................................................................................... 67
Table 58: 71M6541D/F/G LCD Data Registers for SEG46 to SEG50 ..................................................... 69
Table 59: 71M6542F/G LCD Data Registers for SEG46 to SEG50......................................................... 70
Table 60: EECTRL Bits for 2-pin Interface............................................................................................... 71
Table 61: EECTRL Bits for the 3-wire Interface ....................................................................................... 71
Table 62: SPI Transaction Fields ........................................................................................................... 74
Table 63: SPI Command Sequences ..................................................................................................... 75
Table 64: SPI Registers ......................................................................................................................... 76
Table 65: TMUX[5:0] Selections ............................................................................................................ 79
Table 66: TMUX2[4:0] Selections........................................................................................................... 79
Table 67: Available Circuit Functions ..................................................................................................... 82
Table 68: VSTAT[2:0] (SFR 0xF9[2:0]) .................................................................................................... 85
Table 69: Wake Enables and Flag Bits .................................................................................................. 87
Table 70: Wake Bits .............................................................................................................................. 89
Table 71: Clear Events for WAKE flags.................................................................................................. 90
Table 72: GAIN_ADJn Compensation Channels .................................................................................... 98
Table 73: GAIN_ADJn Compensation Channels .................................................................................. 100
Table 74: I/O RAM Map – Functional Order, Basic Configuration ......................................................... 105
Table 75: I/O RAM Map – Functional Order ......................................................................................... 107
Table 76: I/O RAM Map – Functional Order ......................................................................................... 111
Table 77. Standard CE Codes ............................................................................................................. 125
Table 78: CE EQU Equations and Element Input Mapping ................................................................... 126
Table 79: CE Raw Data Access Locations ........................................................................................... 127
Table 80: CESTATUS Register .............................................................................................................. 127
Table 81: CESTATUS (CE RAM 0x80) Bit Definitions .............................................................................. 128
Table 82: CECONFIG Register ............................................................................................................. 128
Table 83: CECONFIG (CE RAM 0x20) Bit Definitions ............................................................................. 128
Table 84: Sag Threshold and Gain Adjust Control................................................................................ 129
Table 85: CE Transfer Variables (with Local Sensors).......................................................................... 130
Table 86: CE Transfer Variables (with Remote Sensor) ....................................................................... 130
Table 87: CE Energy Measurement Variables (with Local Sensors) ..................................................... 131
Table 88: CE Energy Measurement Variables (with Remote Sensor) ................................................... 131
Table 89: Other Transfer Variables ...................................................................................................... 132
Table 90: CE Pulse Generation Parameters......................................................................................... 133
Table 91: CE Parameters for Noise Suppression and Code Version..................................................... 134
Table 92: CE Calibration Parameters ................................................................................................... 135
Table 93: Absolute Maximum Ratings .................................................................................................. 138
Table 95: Recommended Operating Conditions ................................................................................... 139
Table 96: Input Logic Levels ................................................................................................................ 140
Table 97: Output Logic Levels ............................................................................................................. 140
Table 98: Battery Monitor Performance Specifications (TEMP_BAT= 1) ................................................ 141
Table 99. Temperature Monitor............................................................................................................ 141
Table 100: Supply Current Performance Specifications ........................................................................ 142
Table 101: V3P3D Switch Performance Specifications ......................................................................... 143
Table 102. Internal Power Fault Comparator Specifications ................................................................. 143
Table 103: 2.5 V Voltage Regulator Performance Specifications .......................................................... 143
Table 104: Low-Power Voltage Regulator Performance Specifications ................................................. 144
Table 105: Crystal Oscillator Performance Specifications ..................................................................... 144
Table 106: PLL Performance Specifications ......................................................................................... 144
Rev 2
7
71M6541D/F/G and 71M6542F/G Data Sheet
Table 107: LCD Driver Performance Specifications .............................................................................. 145
Table 108: LCD Driver Performance Specifications .............................................................................. 146
Table 109: VREF Performance Specifications...................................................................................... 148
Table 110. ADC Converter Performance Specifications ....................................................................... 149
Table 111: Pre-Amplifier Performance Specifications ........................................................................... 150
Table 112: Flash Memory Timing Specifications .................................................................................. 151
Table 113. SPI Slave Timing Specifications ......................................................................................... 151
Table 114: EEPROM Interface Timing ................................................................................................. 151
Table 115: RESET Pin Timing ............................................................................................................. 152
Table 116: RTC Range for Date........................................................................................................... 152
Table 117. 71M6541 Package Markings .............................................................................................. 155
Table 118. 71M6542 Package Markings .............................................................................................. 155
Table 119: Power and Ground Pins ..................................................................................................... 158
Table 120: Analog Pins........................................................................................................................ 159
Table 121: Digital Pins ......................................................................................................................... 160
Table 122. Ordering Information .......................................................................................................... 163
8
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
VREF
IAP
IAN
IBP
IBN
V3P3A
GNDA GNDD
VLCD
V3P3SYS
∆Σ
AD CONVERTER
VBIAS
MUX
and
PREAMP
VBIAS
VLCD
Voltage
Boost
FIR
V3P3A
-
V3P3D
+
VREF
VA
VB*
VREF
VBAT
MUX
MUX CTRL
CROSS
Voltage
Regulator
CK32
XIN
XOUT
MCK
PLL
RTCLK (32KHz)
Oscillator
CK32
32KHz
32 KHz
DIV
ADC
4.9 MHZ
CKADC
VDD
4.9 MHz
CKFIR
22
2.5V to logic
CLOCK GEN
CK_4X
MUX
LCD_GEN
CKMPU_2x
WPULSE
STRT
VARPULSE
CKCE
< 4.9MHz
LCD DRIVER
RTM
32-bit Compute
Engine
TEST
MODE
CEDATA
32 0x000...0x2FF
CE CONTROL
0x0000...0x13FF
COM0..5
6
SPI
TEST
VLC2
VLC1
VLC0
MEMORY SHARE
MPU RAM
3/5 KB
CE
MUX_SYNC
SEG Pins
8
PROG
0x000...0x3FF
SEGDIO Pins
DIGITAL I/O
16
XFER BUSY
EEPROM
INTERFACE
CKMPU
2
VARPULSE
I/O RAM
CE_BUSY
WPULSE
PB
VBAT_RTC
RTC
< 4.9MHz
RTCLK
SDCK
RX
MPU
(80515)
UART0
SDOUT
Non-Volatile
CONFIGURATION
RAM
SDIN
TX
OPT_RX/
SEGDIO55
OPTICAL
INTERFACE
CONFIGURATION
RAM
(I/O RAM)
DATA
0x0000...0xFFFF
0x2000...0x20FF
8
OPT_TX/
SEGDIO51/
WPULSE/
VARPULSE
PROGRAM
0x0000...0xFFFF
VBIAS
8
MEMORY
SHARE
0x0000…
0xFFFF
MPU_RSTZ
CKMPU_2x
16
CONFIGURATION
PARAMETERS
EMULATOR
PORT
WAKE
RTM
FAULTZ
3
VSTAT
* 71M6542F/G only
TEMP
SENSOR
FLASH
32/64/128 KB
8
POWER FAULT
DETECTION
RESET
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
BAT
TEST
TEST MUX
TEST MUX
2
E_RXTX
E_TCLK
E_RST
ICE_E
10/11/2011
Figure 1: IC Functional Block Diagram
Rev 2
9
71M6541D/F/G and 71M6542F/G Data Sheet
1
Introduction
This data sheet covers the 71M6541D (32KB), 71M6541F (64KB), 71M6541G (128KB), 71M6542F
(64KB), and 71M6542G (128KB) fourth generation Teridian energy measurement SoCs. The term
“71M654x” is used when discussing a device feature or behavior that is applicable to all four part
numbers. The appropriate part number is indicated when a device feature or behavior is being discussed
that applies only to a specific part number. This data sheet also covers basic details about the companion
71M6x01 isolated current sensor device. For more complete information on the 71M6x01 sensors, refer
to the 71M6xxx Data Sheet.
This document covers the use of the 71M654x with locally connected sensors as well when it is used in
conjunction with the 71M6x01 isolated current sensor. The 71M654x and 71M6x01 chipset make it
possible to use one non-isolated and one isolated shunt current sensor to create single-phase and twophase energy meters using inexpensive shunt resistors, while achieving unprecedented performance with
this type of sensor technology. The 71M654x SoCs also support configurations involving one locally
connected shunt and one locally connected Current Transformer (CT), or two CTs.
To facilitate document navigation, hyperlinks are often used to reference figures, tables and section
headings that are located in other parts of the document. All hyperlinks in this document are highlighted in
blue. Hyperlinks are used extensively to increase the level of detail and clarity provided within each
section by referencing other relevant parts of the document. To further facilitate document navigation, this
document is published as a PDF document with bookmarks enabled.
The reader is also encouraged to obtain and review the documents listed in 8 Related Information on
page 163 of this document.
10
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2
Hardware Description
2.1
Hardware Overview
The Teridian 71M6541D/F/G and 71M6542F/G single-chip energy meter ICs integrate all primary
functional blocks required to implement a solid-state residential electricity meter. Included on the chip
are:
•
•
•
•
•
•
•
•
•
•
•
•
•
An analog front end (AFE) featuring a 22-bit second-order sigma-delta ADC
An independent 32-bit digital computation engine (CE) to implement DSP functions
An 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515)
A precision voltage reference (VREF)
A temperature sensor for digital temperature compensation:
- Metrology digital temperature compensation (MPU)
- Automatic RTC digital temperature compensation operational in all power states
LCD drivers
RAM and Flash memory
A real time clock (RTC)
A variety of I/O pins
A power failure interrupt
A zero-crossing interrupt
Selectable current sensor interfaces for locally-connected sensors as well as isolated sensors (i.e.,
using the 71M6x01 companion IC with a shunt resistor sensor)
Resistive Shunt and Current Transformers are supported
Resistive Shunts and Current Transformers (CT) current sensors are supported. Resistive shunt current
sensors may be connected directly to the 71M654x device or isolated using a companion 71M6x01
isolator IC in order to implement a variety of single-phase / split-phase (71M6541D/F/G) or two-phase
(71M6542F/G) metering configurations. An inexpensive, small size pulse transformer is used to isolate
the 71M6x01 isolated sensor from the 71M654x. The 71M654x performs digital communications bidirectionally with the 71M6x01 and also provides power to the 71M6x01 through the isolating pulse
transformer. Isolated (remote) shunt current sensors are connected to the differential input of the
71M6x01. Included on the 71M6x01 companion isolator chip are:
•
•
•
•
•
•
•
Digital isolation communications interface
An analog front end (AFE)
A precision voltage reference (VREF)
A temperature sensor (for digital temperature compensation)
A fully differential shunt resistor sensor input
A pre-amplifier to optimize shunt current sensor performance
Isolated power circuitry obtains dc power from pulses sent by the 71M654x
In a typical application, the 32-bit compute engine (CE) of the 71M654x sequentially processes the samples
from the voltage inputs on analog input pins and from the external 71M6x01 isolated sensors and performs
2
2
calculations to measure active energy (Wh) and reactive energy (VARh), as well as A h, and V h for fourquadrant metering. These measurements are then accessed by the MPU, processed further and output
using the peripheral devices available to the MPU.
In addition to advanced measurement functions, the clock function allows the 71M6541D/F/G and
71M6542F/G to record time-of-use (TOU) metering information for multi-rate applications and to timestamp tamper or other events. Measurements can be displayed on 3.3 V LCDs commonly used in low-temperature environments. An on-chip charge pump is available to drive 5 V LCDs. Flexible mapping of LCD
display segments facilitate integration of existing custom LCDs. Design trade-off between the number of
LCD segments and DIO pins can be implemented in software to accommodate various requirements.
In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature
compensation mechanism includes a temperature sensor and associated controls for correction of unwanted
temperature effects on measurement and RTC accuracy, e.g., to meet the requirements of ANSI and IEC
Rev 2
11
71M6541D/F/G and 71M6542F/G Data Sheet
standards. Temperature-dependent external components such as crystal oscillator, resistive shunts, current
transformers (CTs) and their corresponding signal conditioning circuits can be characterized and their
correction factors can be programmed to produce electricity meters with exceptional accuracy over the
industrial temperature range.
One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense configuration
and can also function as a standard UART. The optical output can be modulated at 38 kHz. This flexibility
makes it possible to implement AMR meters with an IR interface. A block diagram of the IC is shown in
Figure 1.
2.2
Analog Front End (AFE)
The AFE functions as a data acquisition system, controlled by the MPU. When used with locally
connected sensors, as seen in Figure 2, the analog input signals (IAP-IAN, VA and IBP-IBN) are
multiplexed to the ADC input and sampled by the ADC. The ADC output is decimated by the FIR filter
and stored in CE RAM where it can be accessed and processed by the CE.
See Figure 6 for the multiplexer sequence corresponding to Figure 2. See Figure 35 for the meter
configuration corresponding to Figure 2.
VREF
ILINE
ILINE
CT
Local
or
Shunt
IAP
MUX
VREF
∆Σ ADC
CONVERTER
VREF
IAN
VADC
FIR
CE RAM
22
VADC10 (VA)
IN*
IBP
CT
IBN
71M6541D/F
*IN = Optional Neutral Current
11/5/2010
Figure 2. 71M6541D/F/G AFE Block Diagram (Local Sensors)
12
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Figure 3 shows the 71M6541D/F/G multiplexer interface with one local and one remote resistive shunt
sensor. As seen in Figure 3, when a remote isolated shunt sensor is connected via the 71M6x01, the
samples associated with this current channel are not routed to the multiplexer, and are instead
transferred digitally to the 71M6541D/F/G via the digital isolation interface and are directly stored in CE
RAM.
See Figure 6 for the multiplexer timing sequence corresponding to Figure 3. See Figure 36 for the meter
configurations corresponding to Figure 3.
VREF
ILINE
IAP
Local
Shunt
∆Σ ADC
CONVERTER
MUX
VREF
VREF
IAN
FIR
VADC
VADC10 (VA)
22
CE RAM
IN*
INP
SP
Remote
Shunt
IBP
71M6x01
SN
IBN
Digital
Isolation
Interface
22
INN
71M6541D/F
11/5/2010
* IN = Optional Neutral Current
Figure 3. 71M6541D/F/G AFE Block Diagram with 71M6x01
Figure 4 shows the 71M6542F/G AFE with locally connected sensors. The analog input signals (IAP-IAN,
VA, IBP-IBN and VB) are multiplexed to the ADC input and sampled by the ADC. The ADC output is
decimated by the FIR filter and stored in CE RAM where it can be accessed and processed by the CE.
See Figure 7 for the multiplexer timing sequence corresponding to Figure 4. See Figure 37 for the meter
configuration corresponding to Figure 4.
VREF
IA
IA
IAP
CT
Local
Shunt
or
MUX
VREF
∆Σ ADC
CONVERTER
VREF
IAN
VADC
FIR
CE RAM
22
VADC10 (VA)
VADC9 (VB)
IB
IBP
CT
IBN
71M6542F
11/5/2010
Figure 4. 71M6542F/G AFE Block Diagram (Local Sensors)
Rev 2
13
71M6541D/F/G and 71M6542F/G Data Sheet
Figure 5 shows the 71M6542F/G multiplexer interface with one local and one remote resistive shunt
sensor. As seen in Figure 5, when a remote isolated shunt sensor is connected via the 71M6x01, the
samples associated with this current channel are not routed to the multiplexer, and are instead
transferred digitally to the 71M6542F/G via the digital isolation interface and are directly stored in CE
RAM.
See Figure 6 for the multiplexer timing sequence corresponding to Figure 5. See Figure 38 for the meter
configurations corresponding to Figure 5.
VREF
IA
IAP
Local
Shunt
MUX
VREF
∆Σ ADC
CONVERTER
VREF
IAN
FIR
VADC
VADC10 (VA)
22
VADC9 (VB)
CE RAM
IB
INP
Remote
Shunt
SP
IBP
71M6x01
SN
IBN
Digital
Isolation
Interface
22
INN
71M6542F
11/5/2010
Figure 5. 71M6542F/G AFE Block Diagram with 71M6x01
2.2.1
Signal Input Pins
The 71M6541D/F/G features five ADC inputs. The 71M6542F/G features six ADC inputs.
IAP-IAN and IBP-IBN are intended for use as current sensor inputs. These four current sensor inputs can be
configured as four single-ended inputs, or can be paired to form two differential inputs. For best
performance, it is recommended to configure the current sensor inputs as differential inputs (i.e., IAP-IAN
and IBP-IBN). The first differential input (IAP-IAN) features a pre-amplifier with a selectable gain of 1 or 8,
and is intended for direct connection to a shunt resistor sensor, and can also be used with a Current
Transformer (CT). The remaining differential pair (i.e., IBP-IBN) may be used with CTs, or may be enabled
to interface to a remote 71M6x01 isolated current sensor providing isolation for a shunt resistor sensor using
a low cost pulse transformer.
The remaining input in the 71M6541D/F/G (VA) is single-ended, and is intended for sensing the line voltage
in a single-phase meter application using Equation 0 or 1 (see 2.3.4 Meter Equations on page 25). The
71M6542F/G features an additional single-ended voltage sensing input (VB) to support bi-phase
applications using Equation 2. These single-ended inputs are referenced to the V3P3A pin.
All analog signal input pins measure voltage. In the case of shunt current sensors, currents are sensed as a
voltage drop in the shunt resistor sensor. Referring to Figure 3, shunt sensors can be connected directly to
the 71M654x (referred to as a ‘local’ shunt sensor) or connected via an isolated 71M6x01 (referred to as a
‘remote’ shunt sensor). In the case of Current Transformers (CT), the current is measured as a voltage
across a burden resistor that is connected to the secondary winding of the CT. Meanwhile, line voltages are
sensed through resistive voltage dividers. The VA and VB pins (VB is available in the 71M6542F/G only)
are single-ended and their common return is the V3P3A pin.
Pins IAP-IAN can be programmed individually to be differential or single-ended as determined by the
DIFFA_E (I/O RAM 0x210C[4]) control bit. However, for most applications, IAP-IAN are configured as a
differential input to work with a shunt or CT directly interfaced to the IAP-IAN differential input with the
appropriate external signal conditioning components (see 4.2 Direct Connection of Sensors on page 92).
14
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
The performance of the IAP-IAN pins can be enhanced by enabling a pre-amplifier with a fixed gain of 8,
using the I/O RAM control bit PRE_E (I/O RAM 0x2704[5]). When PRE_E = 1, IAP-IAN become the inputs
to the 8x pre-amplifier, and the output of this amplifier is supplied to the multiplexer. The 8x amplification
is useful when current sensors with low sensitivity, such as shunt resistors, are used. With PRE_E set, the
IAP-IAN input signal amplitude is restricted to 31.25 mV peak.
For the 71M654x application utilizing two shunt resistor sensors (Figure 3), the IAP-IAN pins are configured
for differential mode to interface to a local shunt by setting the DIFFA_E control bit. Meanwhile, the IBP-IBN
pins are re-configured as digital balanced pair to communicate with a Teridian 71M6x01 Isolated Sensor
interface by setting the RMT_E control bit (I/O RAM 0x2709[3]). The 71M6x01 communicates with the
71M654x using a bi-directional digital data stream through an isolating low-cost pulse transformer. The
71M654x also supplies power to the 71M6x01 through the isolating transformer. This type of interface is
further described at the end of this chapter (see 2.2.8 71M6x01 Isolated Sensor Interface (Remote Sensor
Interface)).
For use with Current Transformers (CTs), as shown in Figure 2, the RMT_E control bit is reset, so that the
IBP-IBN pins are configured as local analog inputs. The IAP-IAN pins cannot be configured as a remote
sensor interface.
2.2.2
Input Multiplexer
When operating with local sensors, the input multiplexer sequentially applies the input signals from the analog
input pins to the input of the ADC (see Figure 2 and Figure 4). One complete sampling sequence is called a
multiplexer frame. The multiplexer of the 71M6541D/F/G can select up to three input signals (IAP-IAN, VA,
and IBP-IBN) per multiplexer frame as controlled by the I/O RAM control field MUX_DIV[3:0] (I/O RAM
0x2100[7:4]) (see Figure 6). The multiplexer of the 71M6542F/G adds the VB signal to achieve a total
of four inputs (see Figure 7). The multiplexer always starts at state 1 and proceeds until as many
states as determined by MUX_DIV[3:0] have been converted.
The 71M6541D/F/G and 71M6542F/G each require a unique CE code that is written for the specific
application. Moreover, each CE code requires specific AFE and MUX settings in order to function
properly. Table 1 provides the CE code and settings corresponding to the local sensor configurations
shown in Figure 2 and Figure 4. Table 2 provides the CE code and settings corresponding to the
local/remote sensor configuration utilizing the 71M6x01 as shown in Figure 3 and Figure 5.
Table 1. Required CE Code and Settings for Local Sensors
71M6542F/G
I/O RAM
I/O RAM
71M6541D/F/G
(hex)
Mnemonic
Location
(hex)
Eq. 0 or 1
Eq. 2
FIR_LEN[1:0]
210C[2:1]
1
1
2
ADC_DIV
2200[5]
1
1
0
PLL_FAST
2200[4]
1
1
1
MUX_DIV[3:0]
2100[7:4]
3
3
4
MUX0_SEL[3:0]
2105[3:0]
0
0
0
MUX1_SEL[3:0]
2105[7:4]
A
A
A
MUX2_SEL[3:0]
2104[3:0]
2
2
2
MUX3_SEL[3:0]
2104[7:4]
1
1
9
RMT_E
2709[3]
0
0
0
DIFFA_E
210C[4]
1
1
1
DIFFB_E
210C[5]
1
1
1
EQU[2:0]
2106[7:5]
0 or 1
0 or 1
2
CE41A01
CE Code
-CE41A01
CE41A04
Equations
-0 or 1
0 or 1
2
1 Shunt and 1 CT
1 Shunt and 1 CT 1 Shunt and 1 CT
-or
or
or
Current Sensor Types
Applicable Figure
--
2 CTs
2 CTs
2 CTs
Figure 2
Figure 4
Figure 4
Notes:
Teridian updates the CE code periodically. Please contact your local Teridian representative to obtain the latest CE
code and the associated settings. The configuration presented in this table is set by the MPU demonstration code
during initialization.
Rev 2
15
71M6541D/F/G and 71M6542F/G Data Sheet
Table 2. Required CE Code and Settings for 71M6x01 isolated Sensor
I/O RAM
I/O RAM
71M6541D/F/G
71M6542F/G
Mnemonic
Location
(hex)
(hex)
FIR_LEN[1:0]
210C[2:1]
1
1
ADC_DIV
2200[5]
1
1
PLL_FAST
2200[4]
1
1
MUX_DIV[3:0]
2100[7:4]
3
3
MUX0_SEL[3:0]
2105[3:0]
0
0
MUX1_SEL[3:0]
2105[7:4]
A
A
MUX2_SEL[3:0]1
2104[3:0]
1
9
MUX3_SEL[3:0]1
2104[7:4]
1
1
RMT_E
2709[3]
1
1
DIFFA_E
210C[4]
1
1
DIFFB_E
210C[5]
0
0
EQU[2:0]
2106[7:5]
0 or 1
0, 1 or 2
CE41B0162012
CE Code
-3
CE41B016601
Equations
-0, 1
0, 1 and 2
1 Local Shunt
1 Local Shunt
Current Sensor Type
-and
and
1 Remote Shunt
1 Remote Shunt
Applicable Figure
-Figure 3
Figure 5
Notes:
1. Although not used, set to 1 (the sample data is ignored by the CE)
2. 71M654x with 71M6201 remote sensor (200 Amps)
3. 71M654x with 71M6601 remote sensor (60 Amps)
Teridian updates the CE code periodically. Please contact your local Teridian representative to
obtain the latest CE code and the associated settings. The configuration presented in this table is
set by the MPU demonstration code during initialization.
Using settings for the I/O RAM Mnemonics listed in Table 1 and Table 2 that do not match
those required by the corresponding CE code being used results in undesirable side effects
and must not be selected by the MPU. Consult your local Teridian representative to obtain
the correct CE code and AFE / MUX settings corresponding to the application.
For a basic single-phase application, the IAP-IAN current input is configured for differential mode,
whereas the VA pin is single-ended and is typically connected to the phase voltage via a resistor divider.
The IBP-IBN differential input may be optionally used to sense the Neutral current. This configuration
implies that the multiplexer applies a total of three inputs to the ADC. For this configuration, the
multiplexer sequence is as shown in Figure 6. In this configuration IAP-IAN, IBP-IBN and VA are
sampled, the extra conversion time slot (i.e., slot 2) is the optional Neutral current, and the physical
current sensor for the Neutral current measurement may be omitted if not required.
For a standard single-phase application with tamper sensor in the neutral path, two current inputs can be
configured for differential mode, using the pin pairs IAP-IAN and IBP-IBN. This means that the multiplexer
applies a total of three inputs to the ADC. In this application, the system design may use two locally
connected current sensors via IAP-IAN and IBP-IBN, as shown in Figure 2, and configured as differential
inputs. Alternately, the IAP-IAN pin pair is configured as a differential input and connected to a local current
shunt, and IBP-IBN is configured to connect to an isolated 71M6x01 isolated sensor (i.e., RMT_E = 1), as
shown in Figure 3. The VA pin is typically connected to the phase voltage via resistor dividers. For this
configuration, the multiplexer frame is also as shown in Figure 6 and time slot 2 is unused and ignored by
the CE, as the samples corresponding to the remote sensor (IBP-IBN) do not pass through the
multiplexer and are stored directly in CE RAM. The remote current sensor channel is sampled during the
second half of the multiplexer frame and its timing relationship to the VA voltage is precisely known so
that delay compensation can be properly applied.
The 71M6542F adds the ability to sample a second phase voltage (applied at the VB pin), which makes it
suitable for meters with two voltage and two current sensors, such as meters implementing Equation 2 for
dual-phase operation (P = VA*IA+VB*IB). Figure 7 shows the multiplexer sequence when four inputs are
16
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
processed with locally connected sensors, as shown in Figure 3. When using one local and one remote
sensor (Figure 5), the multiplexer sequence is also as shown in Figure 7.
For both multiplexer sequences shown in Figure 6 and Figure 7, the frame duration is 13 CK32 cycles
(where CK32 = 32768 Hz), therefore, the resulting sample rate is 32768 Hz / 13 = 2520.6 Hz.
Table 3 summarizes the various AFE input configurations.
Multiplexer Frame
Settle
MUX_DIV[3:0] = 3 Conversions
CK32
MUX STATE S
Fig. 2:
Fig. 3:
Fig. 5:
0
IA
IA
IA
1
VA
VA
VA
2
IB
Not Used
VB
S
0
CROSS
MUX_SYNC
11/5/2010
Figure 6: States in a Multiplexer Frame (MUX_DIV[3:0] = 3)
Multiplexer Frame
Settle
MUX_DIV = 4 Conversions
CK32
MUX STATE S
Fig. 4:
0
1
2
3
IA
VA
IB
VB
S
0
CROSS
MUX_SYNC
11/5/2010
Figure 7: States in a Multiplexer Frame (MUX_DIV[3:0] = 4)
Table 3: ADC Input Configuration
Rev 2
Pin
ADC
Channel
IAP
ADC0
IAN
ADC1
IBP
ADC2
IBN
ADC3
VA
ADC10
VB
ADC9
Required
Setting
Comment
Differential mode must be selected with DIFFA_E = 1 (I/O
RAM 0x210C[4]). The ADC results are stored in CE RAM
DIFFA_E = 1
location ADC0 (CE RAM 0x0), and ADC1 (CE RAM 0x1) is not
disturbed.
For locally connected sensors (Figure 2 and Figure 4), the
differential input must be enabled by setting DIFFB_E (I/O
RAM 0x210C[5].
DIFFB_E = 1 For the remote connected sensor (Figure 3 and Figure 5)
with a remote shunt sensor, RMT_E (I/O RAM 0x2709[3])
or
RMT_E = 1 must be set.
In both cases, the ADC results are stored in RAM location
ADC2 (CE RAM 0x2), and ADC3 (CE RAM 0x3) is not
disturbed.
Single-ended mode only. The ADC result is stored in RAM
-location ADC10 (CE RAM 0xA).
Single-ended mode only (71M6542F only). The ADC result
-is stored in RAM location ADC9 (CE RAM 0x9).
17
71M6541D/F/G and 71M6542F/G Data Sheet
Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS
signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally,
MUX_CTRL launches each pass of the CE through its code. Conceptually, MUX_CTRL is clocked by
CK32, the 32768 Hz clock from the PLL block. The behavior of the MUX_CTRL circuit is governed by:
•
•
•
•
CHOP_E[1:0] (I/O RAM 0x2106[3:2])
MUX_DIV[3:0] (I/O RAM 0x2100[7:4])
FIR_LEN[1:0] (I/O RAM 0x210C[2:1])
ADC_DIV (I/O RAM 0x2200[5])
The duration of each multiplexer state depends on the number of ADC samples processed by the FIR as
determined by the FIR_LEN[1:0] (I/O RAM 0x210C[2:1] control field. Each multiplexer state starts on the
rising edge of CK32, the 32-kHz clock.
It is recommended that MUX_DIV[3:0] (I/O RAM 0x2200[2:0]) be set to zero while changing the ADC
configuration. Although not required, it minimizes system transients that might be caused by momentary
shorts between the ADC inputs, especially when changing the DIFFn_E control bits (I/O RAM 0x210C[5:4]).
After the configuration bits are set, MUX_DIV[3:0] should be set to the required value.
Additionally, the ADC can be configured to operate at ½ rate (32768*75=2.46MHz). In this mode, the
bias current to the ADC amplifiers is reduced and overall system power is reduced. The ADC_DIV (I/O
RAM 0x2200[5]) bit selects full speed or half speed. At half speed, if FIR_LEN[1:0] is set to 01 (288),
each conversion requires 4 XTAL cycles, resulting in a 2520Hz sample rate when MUX_DIV[3:0] = 3.
Note that in order to work with these power-reducing settings, a corresponding CE code is required.
The duration of each time slot in CK32 cycles depends on FIR_LEN[1:0], ADC_DIV and PLL_FAST:
Time_Slot_Duration (PLL_FAST = 1) = (FIR_LEN[1:0]+1) * (ADC_DIV+1)
Time_Slot_Duration (PLL_FAST = 0) = 3*(FIR_LEN[1:0]+1) * (ADC_DIV+1)
The duration of a multiplexer frame in CK32 cycles is:
MUX_Frame_Duration = 3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV[3:0]
The duration of a multiplexer frame in CK_FIR cycles is:
MUX frame duration (CK_FIR cycles) =
[3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV] * (48+PLL_FAST*102)
The ADC conversion sequence is programmable through the MUXx_SEL control fields (I/O RAM 0x2100
to 0x2105). As stated above, there are three ADC time slots in the 71M6541D/F/G and four ADC time
slots in the 71M6542F/G, as set by MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). In the expression
MUXx_SEL[3:0] = n, ‘x’ refers to the multiplexer frame time slot number and n refers to the desired ADC input
number or ADC handle (i.e., ADC0 to ADC10, or simply 0 to 10 decimal). Thus, there are a total of 11 valid
ADC handles in the 71M654x devices. For example, if MUX0_SEL[3:0] = 0, then ADC0, corresponding to the
sample from the IAP-IAN input (configured as a differential input), is positioned in the multiplexer frame during
time slot 0. See Table 1 and Table 2 for the appropriate MUXx_SEL[3:0] settings and other settings
applicable to a particular CE code.
Note that when the remote sensor interface is enabled, and even though the samples corresponding to
the remote sensor current (IBP-IBN) do not pass through the multiplexer, the MUX2_SEL[3:0] and
MUX3_SEL[3:0] control fields must be written with a valid ADC handle that is not being used. Typically,
ADC1 is used for this purpose (see Table 2). In this manner, the ADC1 handle, which is not used in the
71M6541D/F/G or 71M6542F/G, is used as a place holder in the multiplexer frame, in order to generate
the correct multiplexer frame sequence and the correct sample rate. The resulting sample data stored
in CE RAM 0x1 is undefined and is ignored by the CE code. Meanwhile, the digital isolation interface
takes care of automatically storing the samples for the remote interface current (IBP-IBN) in CE RAM
0x2.
18
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0],
MUXx_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code.
Refer to Table 1 and Table 2 for the settings that are applicable to the 71M6541D/F/G and
71M6542F/G.
Table 4 summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC.
All listed registers are 0 after reset and wake from battery modes, and are readable and writable.
Table 4: Multiplexer and ADC Configuration Bits
Name
MUX0_SEL[3:0]
MUX1_SEL[3:0]
MUX2_SEL[3:0]
MUX3_SEL[3:0]
MUX4_SEL[3:0]
MUX5_SEL[3:0]
MUX6_SEL[3:0]
MUX7_SEL[3:0]
MUX8_SEL[3:0]
MUX9_SEL[3:0]
MUX10_SEL[3:0]
ADC_DIV
MUX_DIV[3:0]
PLL_FAST
FIR_LEN[1:0]
DIFFA_E
DIFFB_E
Location
Description
Selects the ADC input converted during time slot 0.
Selects the ADC input converted during time slot 1.
Selects the ADC input converted during time slot 2.
Selects the ADC input converted during time slot 3.
Selects the ADC input converted during time slot 4.
Selects the ADC input converted during time slot 5.
Selects the ADC input converted during time slot 6.
Selects the ADC input converted during time slot 7.
Selects the ADC input converted during time slot 8.
Selects the ADC input converted during time slot 9.
Selects the ADC input converted during time slot 10.
Controls the rate of the ADC and FIR clocks.
The number of ADC time slots in each multiplexer frame (maximum = 11).
Controls the speed of the PLL and MCK.
Determines the number of ADC cycles in the ADC decimation FIR filter.
Enables the differential configuration for analog input pins IAP-IAN.
Enables the differential configuration for analog input pins IBP-IBN.
Enables the remote sensor interface transforming pins IBP-IBN into a
RMT_E
digital balanced differential pair for communications with the 71M6x01
2709[3]
sensor.
PRE_E
2704[5]
Enables the 8x pre-amplifier.
Refer to Table 76 starting on page 111 for more complete details about these I/O RAM locations.
2.2.3
2105[3:0]
2105[7:4]
2104[3:0]
2104[7:4]
2103[3:0]
2103[7:4]
2102[3:0]
2102[7:0]
2101[3:0]
2101[7:0]
2100[3:0]
2200[5]
2100[7:4]
2200[4]
210C[1]
210C[4]
210C[5]
Delay Compensation
When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that
phase must be sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.
φ=
t delay
T
⋅ 360 o = t delay ⋅ f ⋅ 360 o
Where f is the frequency of the input signal, T = 1/f and tdelay is the sampling delay between current and
voltage.
Traditionally, sampling is accomplished by using two A/D converters per phase (one for voltage and the
other one for current) controlled to sample simultaneously. Maxim’s Teridian Single-Converter
Technology, however, exploits the 32-bit signal processing capability of its CE to implement “constant
delay” all-pass filters. The all-pass filter corrects for the conversion time difference between the voltage
and the corresponding current samples that are obtained with a single multiplexed A/D converter.
o
The “constant delay” all-pass filter provides a broad-band delay 360 – θ, which is precisely matched to
the difference in sample time between the voltage and the current of a given phase. This digital filter
does not affect the amplitude of the signal, but provides a precisely controlled phase response.
The recommended ADC multiplexer sequence samples the current first, immediately followed by
sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle Ф relative to
Rev 2
19
71M6541D/F/G and 71M6542F/G Data Sheet
the current. The delay compensation implemented in the CE aligns the voltage samples with their
corresponding current samples by first delaying the current samples by one full sample interval (i.e.,
o
360 ), then routing the voltage samples through the all-pass filter, thus delaying the voltage samples by
360o - θ, resulting in the residual phase error between the current and its corresponding voltage of θ – Ф.
The residual phase error is negligible, and is typically less than ±1.5 milli-degrees at 100Hz, thus it does
not contribute to errors in the energy measurements.
When using remote sensors, the CE performs the same delay compensation described above to align
each voltage sample with its corresponding current sample. Even though the remote current samples do
not pass through the 71M654x multiplexer, their timing relationship to their corresponding voltages is
fixed and precisely known, provided that the MUXn_SEL[3:0] slot assignment fields are programmed as
shown in Table 1 and Table 2.
2.2.4
ADC Pre-Amplifier
The ADC pre-amplifier is a low-noise differential amplifier with a fixed gain of 8 available only on the IAPIAN sensor input pins. A gain of 8 is enabled by setting PRE_E = 1 (I/O RAM 0x2704[5]). When disabled,
the supply current of the pre-amplifier is <10 nA and the gain is unity. With proper settings of the PRE_E
and DIFFA_E (I/O RAM 0x210C[4]) bits, the pre-amplifier can be used whether differential mode is
selected or not. For best performance, the differential mode is recommended. In order to save power, the
bias current of the pre-amplifier and ADC is adjusted according to the ADC_DIV control bit (I/O RAM
0x2200[5]).
2.2.5
A/D Converter (ADC)
A single 2nd order delta-sigma A/D converter digitizes the voltage and current inputs to the device. The
resolution of the ADC, including the sign bit, is 21 bits (FIR_LEN[1:0] = 1, I/O RAM 0x210C[2:1]), or 22 bits
(FIR_LEN[1:0] = 2). The ADC is clocked by CKADC.
Initiation of each ADC conversion is controlled by MUX_CTRL internal circuit as described above. At the
end of each ADC conversion, the FIR filter output data is stored into the CE RAM location determined by
the multiplexer selection. FIR data is stored LSB justified, but shifted left 9 bits.
2.2.6
FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer.
The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each
ADC conversion, the output data is stored into the fixed CE RAM location determined by the multiplexer
selection as shown in Table 1 and Table 2.
2.2.7
Voltage References
A bandgap circuit provides the reference voltage to the ADC. The amplifier within the reference is chopper
stabilized, i.e., the chopper circuit can be enabled or disabled by the MPU using the I/O RAM control field
CHOP_E[1:0] (I/O RAM 0x2106[3:2]). The two bits in the CHOP_E[1:0] field enable the MPU to operate the
chopper circuit in regular or inverted operation, or in toggling modes (recommended). When the
chopper circuit is toggled in between multiplexer cycles, dc offsets on VREF are automatically be
averaged out, therefore the chopper circuit should always be configured for one of the toggling modes.
Since the VREF band-gap amplifier is chopper-stabilized, the dc offset voltage, which is the most
significant long-term drift mechanism in the voltage references (VREF), is automatically removed by the
chopper circuit. Both the 71M654x and the 71M6x01 feature chopper circuits for their respective VREF
voltage reference.
The general topology of a chopped amplifier is shown in Figure 8. The CROSS signal is an internal onchip signal and is not accessible on any pin or register.
20
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
A
Vinp
B
A
Vinn
B
A
+
G
-
Voutp
B
A
Voutn
B
CROSS
Figure 8: General Topology of a Chopped Amplifier
It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as
controlled by CROSS (an internal signal), in the A position, the output voltage is:
Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff
With all switches set to the B position by applying the inverted CROSS signal, the output voltage is:
Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff, or
Voutp – Voutn = G (Vinp – Vinn) - G Voff
Thus, when CROSS is toggled, e.g., after each multiplexer cycle, the offset alternately appears on the
output as positive and negative, which results in the offset effectively being eliminated, regardless of its
polarity or magnitude.
When CROSS is high, the connection of the amplifier input devices is reversed. This preserves the overall
polarity of that amplifier gain; it inverts its input offset. By alternately reversing the connection, the amplifier’s
offset is averaged to zero. This removes the most significant long-term drift mechanism in the voltage
reference. The CHOP_E[1:0] (I/O RAM 0x2106[3:2]) control field controls the behavior of CROSS. The
CROSS signal reverses the amplifier connection in the voltage reference in order to negate the effects of its
offset. On the first CK32 rising edge after the last multiplexer state of its sequence, the multiplexer waits
one additional CK32 cycle before beginning a new frame. At the beginning of this cycle, the value of
CROSS is updated according to the CHOP_E[1:0] field. The extra CK32 cycle allows time for the
chopped VREF to settle. During this cycle, MUXSYNC is held high. The leading edge of MUXSYNC initiates
a pass through the CE program sequence. The beginning of the sequence is the serial readout of the four
RTM words.
CHOP_E[1:0] has four states: positive, reverse, and two toggle states. In the positive state, CHOP_E[1:0]
= 01, CROSS is held low. In the reverse state, CHOP_E[1:0] = 10, CROSS is held high.
Figure 9: CROSS Signal with CHOP_E = 00
Figure 9 shows CROSS over two accumulation intervals when CHOP_E[1:0] = 00: At the end of the
first interval, CROSS is high, at the end of the second interval, CROSS is low. Operation with
CHOP_E[1:0] = 00 does not require control of the chopping mechanism by the MPU.
In the second toggle state, CHOP_E[1:0] = 11, CROSS does not toggle at the end of the last multiplexer
cycle in an accumulation interval.
A second, low-power voltage reference is used in the LCD system and for the comparators that support
transitions to and from the battery modes.
Rev 2
21
71M6541D/F/G and 71M6542F/G Data Sheet
2.2.8
71M6x01 Isolated Sensor Interface (Remote Sensor Interface)
2.2.8.1 General Description
Non-isolating sensors, such as shunt resistors, can be connected to the inputs of the 71M654x via a
combination of a pulse transformer and a 71M6x01 IC (a top-level block diagram of this sensor interface
is shown in Figure 36). The 71M6x01 receives power directly from the 71M654x via a pulse transformer
and does not require a dedicated power supply circuit. The 71M6x01 establishes 2-way communication
with the 71M654x, supplying current samples and auxiliary information such as sensor temperature via a
serial data stream.
One 71M6x01 Isolated Sensor can be supported by the 71M6541D/F/G and 71M6542F/G. When
remote interface IBP-IBN is enabled, the two analog current inputs pins IBP and IBN become a digital
balanced differential interface to the remote sensor. See Table 3 for details.
Each 71M6x01 Isolated Sensor consists of the following building blocks:
•
•
•
•
•
•
Power supply for power pulses received from the 71M654x
Digital communications interface
Shunt signal pre-amplifier
Delta-Sigma ADC Converter with precision bandgap reference (chopping amplifier)
Temperature sensor
Fuse system containing part-specific information
During an ordinary multiplexer cycle, the 71M654x internally determines which other channels are
enabled with MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). At the same time, it decimates the modulator output
from the 71M6x01 Isolated Sensors. Each result is written to CE RAM during one of its CE access time
slots. See Table 3 for the CE RAM locations of the sampled signals.
2.2.8.2 Communication between 71M654x and 71M6x01 Isolated Sensor
The ADC of the 71M6x01 derives its timing from the power pulses generated by the 71M654x and as a
result, operates its ADC slaved to the frequency of the power pulses. The generation of power pulses, as
well as the communication protocol between the 71M654x and 71M6x01 Isolated Sensor is automatic and
transparent to the user. Details are not covered in this data sheet.
2.2.8.3 Control of the 71M6x01 Isolated Sensor
The 71M654x can read or write certain types of information from each 71M6x01 isolated sensor.
The data to be read is selected by a combination of the RCMD[4:0] and TMUXRn[2:0]. To perform a read
transaction from one of the 71M6x01 devices, the MPU first writes the TMUXRn[2:0] field (where n = 2, 4, 6,
located at I/O RAM 0x270A[2:0], 0x270A[6:4] and 0x2709[2:0], respectively). Next, the MPU writes
RCMD[4:0] (SFR 0xFC[4:0]) with the desired command and phase selection. When the RCMD[4:2] bits
have cleared to zero, the transaction has been completed and the requested data is available in
RMT_RD[15:0] (I/O RAM 0x2602[7:0] is the MSB and 0x2603[7:0] is the LSB). The read parity error bit,
PERR_RD (SFR 0xFC[6]) is also updated during the transaction. If the MPU writes to RCMD[4:0] before a
previously initiated read transaction is completed, the command is ignored. Therefore, the MPU must wait
for RCMD[4:2]=0 before proceeding to issue the next remote sensor read command.
The RCMD[4:0] field is divided into two sub-fields, COMMAND=RCMD[4:2] and PHASE=RCMD[1:0], as
shown in Table 5.
Command
RCMD[4:2]
000
Invalid
001
Command 1
100
Reserved
101
Invalid
110
Reserved
22
Table 5. RCMD[4:0] Bits
Phase Selector
RCMD[1:0]
00
Invalid
IBP-IBN
01
Associated TMUXRn
Control Field
--TMUXRB [2:0]
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
111
Reserved
Notes:
1. Only two codes of RCMD[4:2] (SFR 0xFC[4:2]) are relevant for normal
operation. These are RCMD[4:2] = 001 and 010. Codes 000 and 101
are invalid and will be ignored if used. The remaining codes are
reserved and must not be used.
2. For the RCMD[1:0] control field, codes 01, 10 and 11 are valid and 00
is invalid and must not be used.
Table 6 shows the allowable combinations of values in RCMD[4:2] and TMUXRn[2:0], and the
corresponding data type and format sent back by the 71M6x01 isolated sensor and how the data is stored
in RMT_RD[15:8] and RMT_RD[7:0]. The MPU selects which of the three phases is read by asserting the
proper code in the RCMD[1:0] field, as shown in Table 5.
Table 6: Remote Interface Read Commands
RCMD[4:2]
TMUXRn[2:0]
001
00X
Read Operation
TRIMT[7:0]
010
00X
STEMP[10:0]
010
01X
VSENSE[7:0]
010
10X
VERSION[7:0]
(trim fuse for all 71M6x01)
(sensed 71M6x01 temperature)
(sensed 71M6x01 supply voltage)
(chip version)
RMT_RD [15:8]
RMT_RD [7:0]
TRIMT[7]=RMT_RD[8]
TRIMT[6:0]=RMT_RD[7:1]
STEMP[10:8]=RMT_RD[10:8]
STEMP[7:0]
(RMT_RD[15:11] are sign extended)
All zeros
VSENSE[7:0]
VERSION[7:0]
All zeros
Notes:
1. TRIMT[7:0] is the VREF trim value for all 71M6x01 devices. Note that the TRIMT[7:0] 8-bit value is formed
by RMT_RD[8] and RMT_RD[7:1]. See the 71M6xxx Data sheet for more information on TRIMT[7:0]
2. See the 71M6xxx Data Sheet for the equation to calculate temperature from the STEMP[7:0] value read from
the 71M6x01.
3. See the 71M6xxx Data Sheet for the equation to calculate temperature from the VSENSE[7:0] value read from
the 71M6x01.
With hardware and trim-related information on each connected 71M6x01 Isolated Sensor available to the
71M6541D/F/G, the MPU can implement temperature compensation of the energy measurement based on
the individual temperature characteristics of the 71M6x01 Isolated Sensor. See 4.7 Metrology
Temperature Compensation on page 97 for details.
Table 7 shows all I/O RAM registers used for control of the external 71M6x01 Isolated Sensors. See the
71M6xxx Data Sheet for additional details.
Table 7: I/O RAM Control Bits for Isolated Sensor
Name
Address
RST
WAKE
Default Default
RCMD[4:0]
SFR
FC[4:0]
0
0
PERR_RD
PERR_WR
SFR FC[6]
SFR FC[5]
0
0
CHOPR[1:0]
2709[7:6]
00
00
Rev 2
R/W Description
When the MPU writes a non-zero value to RCMD,
the 71M654x issues a command to the corresponding isolated sensor selected with
R/W
RCMD[1:0]. When the command is complete, the
71M654x clears RCMD[4:2]. The command code
itself is in RCMD[4:2].
The 71M654x sets these bits to indicate that a
parity error on the isolated sensor has been deR/W
tected. Once set, the bits are remembered until
they are cleared by the MPU.
The CHOP settings for the isolated sensors.
00 – Auto chop. Change every multiplexer frame.
R/W 01 – Positive
10 – Negative
11 – Same as 00
23
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Address
TMUXRB[2:0] 270A[2:0]
RMT_RD[15:8] 2602[7:0]
RMT_RD[7:0] 2603[7:0]
RST
WAKE
Default Default
000
000
0
R/W Description
R/W The TMUX bits for control of the isolated sensor.
0
R
The read buffer for 71M6x01 read operations.
Controls how the 71M654x drives the 71M6x01
power pulse. When set, the power pulse is driven
210C[3]
RFLY_DIS
0
0
R/W
high and low. When cleared, it is driven high
followed by an open circuit flyback interval.
Enables the isolated remote sensor interface and
RMTB_E
2709[3]
0
0
R/W re-configures pins IBP-IBN as a balanced pair
digital remote interface.
Refer to Table 76 starting on page 111 for more complete details about these I/O RAM locations.
2.3
Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately
measure energy. The CE calculations and processes include:
•
•
•
•
•
•
•
•
Multiplication of each current sample with its associated voltage sample to obtain the energy per
sample (when multiplied with the constant sample time).
Frequency-insensitive delay cancellation on all four channels (to compensate for the delay between
samples caused by the multiplexing scheme).
90° phase shifter (for VAR calculations).
Pulse generation.
Monitoring of the input signal frequency (for frequency and phase information).
Monitoring of the input signal amplitude (for sag detection).
Scaling of the processed samples based on calibration coefficients.
Scaling of samples based on temperature compensation information.
2.3.1
CE Program Memory
The CE program resides in flash memory. Common access to flash memory by the CE and MPU is controlled
by a memory share circuit. Each CE instruction word is two bytes long. Allocated flash space for the CE
program cannot exceed 4096 16-bit words (8 KB). The CE program counter begins a pass through the
CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is executed.
For proper operation, the code pass must be completed before the multiplexer cycle ends.
The CE program must begin on a 1 KB boundary of the flash address. The I/O RAM control field
CE_LCTN[5:0] (I/O RAM 0x2109[5:0]) defines which 1 KB boundary contains the CE code. Thus, the first
CE instruction is located at 1024*CE_LCTN[5:0].
2.3.2
CE Data Memory
The CE and MPU share data memory (RAM). Common access to XRAM by the CE and MPU is controlled
by a memory share circuit. The CE can access up to 3 KB of the 3 KB data RAM (XRAM), i.e., from RAM
address 0x0000 to 0x0C00.
The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access by the CE.
The MPU reads and writes the XRAM shared between the CE and MPU as the primary means of data
communication between the two processors.
Table 3 shows the CE addresses in XRAM allocated to analog inputs from the AFE.
The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and
accumulators. This hardware is controlled through the I/O RAM control field EQU[2:0], equation assist
(I/O RAM 0x2106[7:5]), bit DIO_PV (I/O RAM 0x2457[6]), bit DIO_PW, pulse count assist (I/O RAM
0x2457[7]), and SUM_SAMPS[12:0], accumulation assist (I/O RAM 0x2107[4:0] and 0x2108[7:0]).
24
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
SUM_SAMPS[12:0] supports an accumulation scheme where the incremental energy values from up to
SUM_SAMPS[12:0] multiplexer frames are added up over one accumulation interval. The integration time
for each energy output is, for example, SUM_SAMPS[12:0]/2520.6 (with MUX_DIV[3:0] = 011, I/O RAM
0x2100[7:4] and FIR_LEN[1:0] = 10, I/O RAM 0x210C[2:1]). CE hardware issues the XFER_BUSY interrupt
when the accumulation is complete.
2.3.3
CE Communication with the MPU
The CE outputs six signals to the MPU: CE_BUSY, XFER_BUSY, XPULSE, YPULSE, WPULSE and
VPULSE. These are connected to the MPU interrupt service. CE_BUSY indicates that the CE is actively
processing data. This signal occurs once every multiplexer frame. XFER_BUSY indicates that the CE is
updating to the output region of the CE RAM, which occurs whenever an accumulation cycle has been
completed. Both, CE_BUSY and XFER_BUSY are cleared when the CE executes a HALT instruction.
XPULSE, YPULSE, VPULSE and WPULSE can be configured to interrupt the MPU and indicate sag
failures, zero crossings of the mains voltage, or other significant events. Additionally, these signals can
be connected directly to DIO pins to provide direct outputs for the CE. Interrupts associated with these
signals always occur on the leading edge (see “External” interrupt source No. 2 in Figure 16).
2.3.4
Meter Equations
The 71M6541D/F/G and 71M6542F/G provide hardware assistance to the CE in order to support various
meter equations. This assistance is controlled through I/O RAM register EQU[2:0] (equation assist). The
Compute Engine (CE) firmware for industrial configurations can implement the equations listed in Table 8.
EQU[2:0] specifies the equation to be used based on the meter configuration and on the number of
phases used for metering.
Table 8: Inputs Selected in Multiplexer Cycles
Wh and VARh formula
EQU
Description
0
1-element, 2-W, 1φ with
neutral current sense
1
1-element, 3-W, 1φ
2†
2-element, 3-W, 3φ Delta
Element 0
Element 1
Element 2
Recommended
Multiplexer
Sequence
VA ∙ IA
VA ∙ IB1
N/A
IA VA IB1
VA(IA-IB)/2
N/A
N/A
IA VA IB
VA ∙ IA
VB ∙ IB
N/A
IA VA IB VB
Note:
1. Optionally, IB may be used to measure neutral current
† 71M6542F/G only
2.3.5
Real-Time Monitor (RTM)
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable
XRAM locations at full sample rate. The four monitored locations, as selected by the I/O RAM registers
RTM0[9:8], RTM0[7:0], RTM1[9:8], RTM1[7:0], RTM2[9:8], RTM2[7:0], RTM3[9:8], and RTM3[7:0], are
serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code
pass. The RTM can be enabled and disabled with control bit RTM_E (I/O RAM 0x2106[1]). The RTM
output is clocked by CKTEST. Each RTM word is clocked out in 35 CKCE cycles (1 CKCE cycle is
equivalent to 203 ns) and contains a leading flag bit. See Figure 10 for the RTM output format. RTM is
low when not in use.
Figure 11 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and
the RTM serial output stream. In this example, MUX_DIV[3:0] = 4 (I/O RAM 0x2100[7:4]) and
FIR_LEN[1:0] = 10 (I/O RAM 0x210C[1]), (384), resulting in 4 ADC conversions. An ADC conversion
always consumes an integer number of CK32 clocks. Followed by the conversions is a single CK32
cycle.
Figure 11 also shows that the RTM serial data stream begins transmitting at the beginning of state S.
RTM, consisting of 140 CK cycles, always finishes before the next CE code pass starts.
Rev 2
25
71M6541D/F/G and 71M6542F/G Data Sheet
CK32
MUX_SYNC
MUX_STATE
S
CKTEST
0
31
FLAG
1
30
31
0
FLAG
1
30
31
SIG
N
30
L SB
1
SIG
N
0
FLAG
L SB
RTM DATA0 (32 bits)
RTM DATA1 (32 bits)
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
31
SIG
N
30
L SB
1
L SB
0
FLAG
SIG
N
RTM
Figure 10: RTM Timing
ADC MUX Frame
ADC TIMING
MUX_DIV Conversions, MUX_DIV=4 is shown
Settle
CK32
150
MUX_SYNC
MUX STATE
0
S
1
2
S
3
ADC EXECUTION
ADC0
CE TIMING
0
ADC1
450
900
ADC2
ADC3
1350
1800
CE_EXECUTION
CK COUNT = CE_CYCLES + 1CK for each ADC transfer
MAX CK COUNT
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
RTM TIMING
140
RTM
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY SUM_SAMPS CODE PASSES.
Figure 11: Timing relationship between ADC MUX, CE, and RTM Serial Transfer
26
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2.3.6
Pulse Generators
The 71M6541D/F/G and 71M6542F/G provide four pulse generators, VPULSE, WPULSE, XPULSE and
YPULSE, as well as hardware support for the VPULSE and WPULSE pulse generators. The pulse
generators can be used to output CE status indicators, SAG for example, to DIO pins. All pulses can be
configured to generate interrupts to the MPU.
The polarity of the pulses may be inverted with control bit PLS_INV (I/O RAM 0x210C[0]). When this bit is
set, the pulses are active high, rather than the more usual active low. PLS_INV inverts all four pulse
outputs.
The function of each pulse generator is determined by the CE code and the MPU code must configure the
corresponding pulse outputs in agreement with the CE code. For example, standard CE code produces a
mains zero-crossing pulse on XPULSE and a SAG pulse on YPULSE.
A common use of the zero-crossing pulses is to generate interrupt in order to drive real-time clock software
in places where the mains frequency is sufficiently accurate to do so and also to adjust for crystal aging.
A common use for the SAG pulse is to generate an interrupt that alerts the MPU when mains power is about
to fail, so that the MPU code can store accumulated energy and other data to EEPROM before the
V3P3SYS supply voltage actually drops.
2.3.6.1 XPULSE and YPULSE
Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse output pins. Pins
SEGDIO6 and SEGDIO7 are used for these pulses, respectively. Generally, the XPULSE and YPULSE
outputs can be updated once on each pass of the CE code.
See 5.3 CE Interface Description on page 125 for details.
2.3.6.2 VPULSE and WPULSE
Referring to Figure 12, during each CE code pass the hardware stores exported WPULSE and VPULSE sign
bits in an 8-bit FIFO and outputs them at a specified interval. This permits the CE code to calculate the
VPULSE and WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them
over the multiplexer frame. As seen in Figure 12, the FIFO is reset at the beginning of each multiplexer
frame. As also seen in Figure 12, the I/O RAM register PLS_INTERVAL[7:0] (I/O RAM 0x210B[7:0])
controls the delay to the first pulse update and the interval between subsequent updates. The LSB of
the PLS_INTERVAL[7:0] register is equivalent to 4 CK_FIR cycles (CK_FIR is typically 4.9152MHz if
PLL_FAST=1 and ADC_DIV=0, but other CK_FIR frequencies are possible; see the ADC_DIV definition in
Table 76.) If PLS_INTERVAL[7:0]=0, the FIFO is deactivated and the pulse outputs are updated immediately.
The MUX frame duration in units of CK_FIR clock cycles is given by:
If PLL_FAST=1:
MUX frame duration in CK_FIR cycles = [1 + (FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [150 / (ADC_DIV+1)]
If PLL_FAST=0:
MUX frame duration in CK_FIR cycles = [3 + 3*(FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [48 / (ADC_DIV+1)]
PLS_INTERVAL[7:0] in units of CK_FIR clock cycles is calculated by:
PLS_INTERVAL[7:0] = floor (Mux frame duration in CK_FIR cycles / CE pulse updates per Mux frame / 4 )
Since the FIFO resets at the beginning of each multiplexer frame, the user must specify
PLS_INTERVAL[7:0] so that all of the possible pulse updates occurring in one CE execution are output
before the multiplexer frame completes. For instance, the 71M654x CE code outputs six updates per
multiplexer interval, and if the multiplexer interval is 1950 CK_FIR clock cycles long, the ideal value for
the interval is 1950/6/4 = 81.25. However, if PLS_INTERVAL[7:0] = 82, the sixth output occurs too late and
would be lost. In this case, the proper value for PLS_INTERVAL[7:0] is 81 (i.e., round down the result).
Since one LSB of PLS_INTERVAL[7:0] is equal to 4 CK_FIR clock cycles, the pulse time interval TI in units of
CK_FIR clock cycles is:
TI = 4*PLS_INTERVAL[7:0]
Rev 2
27
71M6541D/F/G and 71M6542F/G Data Sheet
If the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0), hardware also provides a maximum pulse width feature
in control register PLS_MAXWIDTH[7:0] (I/O RAM 0x210A) . By default, WPULSE and VPULSE are negative
pulses (i.e., low level pulses, designed to sink current through an LED). PLS_MAXWIDTH[7:0] determines the
maximum negative pulse width TMAX in units of CK_FIR clock cycles based on the pulse interval TI
according to the formula:
TMAX = (2 * PLS_MAXWIDTH[7:0] + 1) * TI
If PLS_MAXWIDTH = 255 or PLS_INTERVAL=0, no pulse width checking is performed, and the pulses
default to 50% duty cycle. TMAX is typically programmed to 10 ms., which works well with most calibration
systems.
The polarity of the pulses may be inverted with the control bit PLS_INV (I/O RAM 0x210C[0]). When
PLS_INV is set, the pulses are active high. The default value for PLS_INV is zero, which selects active low
pulses.
The WPULSE and VPULSE pulse generator outputs are available on pins SEGDIO0/WPULSE and
SEGDIO1/VPULSE, respectively (pins 45 and 44). The pulses can also be output on OPT_TX pin 53
(see OPT_TXE[1:0], I/O RAM 0x2456[3:2] for details).
ADC MUX Frame
Settle
MUX_DIV Conversions (MUX_DIV=4 is shown)
CK32
150
MUX_SYNC
CE CODE
S0
S1
S2
S3
S4
S5
W_FIFO
RST
WPULSE
S0
S1
S0
4*PLS_INTERVAL
4*PLS_INTERVAL
S2
S1
4*PLS_INTERVAL
S3
S2
4*PLS_INTERVAL
S4
S3
4*PLS_INTERVAL
S5
S4
S5
4*PLS_INTERVAL
1. This example shows how the FIFO distributes 6 pulse generator updates over one MUX frame.
2. If WPULSE is low longer than (2*PLS_MAXWIDTH+1) updates, WPULSE will be raised until the next
low-going pulse begins.
3. Only the WPULSE circuit is shown. The VARPULSE circuit behaves identically.
4. All dimensions are in CK_FIR cycles (4.92MHz).
5. If PLS_INTERVAL=0, FIFO does not perform delay.
Figure 12. Pulse Generator FIFO Timing
2.3.7
CE Functional Overview
The 71M654x provides an ADC and multiplexer to sample the analog currents and voltages as seen in
Figure 2 and Figure 3. The VA and VB voltage sensors are formed by resistive voltage dividers directly
connected to the 71M654x device, and therefore always use the ADC and multiplexer facilities in the
71M654x device. Current sensors, however, may be connected directly to the 71M654x or remotely
connected through an isolated 71M6x01 device. The remote 71M6x01 sensor has its own separate ADC
and voltage reference. When a current sensor is connected via a 71M6x01 isolated sensor, the 71M654x
places the sample data received digitally over the isolation interface (via the pulse transformer) in the
appropriate CE RAM location, as shown in Figure 3. The ADCs (i.e., ADC in the 71M654x and the ADC in
the 71M6x01) process their corresponding sensor channels providing one sample per channel per
multiplexer cycle.
Figure 14 (71M6541D/F/G) and Figure 15 (71M6542F/G) show the sampling sequence when both current
sensors (IA and IB) are connected directly to the 71M6541D/F/G as seen in Figure 2. However, when the
28
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
IB channel is a 71M6x01 isolated sensor, the sample data does not pass through the 71M6541D/F/G
multiplexer, as seen in Figure 3. In this case, the sample is taken during the second half of the multiplexer
cycle and the data is directly stored in the corresponding CE RAM location as indicated in Figure 3. The
timing relationship between the remote current sensor channel and its corresponding voltage is precisely
defined so that delay compensation can be properly applied by the CE.
Referring to Figure 15, the 71M6542F/G features an additional voltage input (VB) permitting the
implementation of a two-phase meter. As with VA, the VB voltage divider is directly connected to the
71M6542F/G and uses the ADC and multiplexer facilities in the 71M6542F/G. MUX_DIV[3:0] = 4
configures the multiplexer to provide an additional time slot to accommodate the additional VB voltage
sample. As with the 71M6541D/F/G, IA samples are obtained from a current sensor that is directly
connected to the 71M6542F/G, while IB samples may be obtained from a directly connected CT or a
remotely connected shunt using a 71M6x01 isolated device as seen in Figure 2 and Figure 3.
The number of samples processed during one accumulation cycle is controlled by the I/O RAM register
SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0], 0x2108[7:0]). The integration time for each energy output is:
SUM_SAMPS / 2520.6, where 2520.6 is the sample rate in Hz
For example, SUM_SAMPS = 2100 establishes 2100 samples per accumulation cycle, which has a
duration of 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the
MPU that accumulated data are available.
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
Figure 13 shows the accumulation interval resulting from SUM_SAMPS = 2100, consisting of 2100
samples of 397 µs each, followed by the XFER_BUSY interrupt. The sampling in this example is applied
to a 50 Hz signal. There is no correlation between the line signal frequency and the choice of
SUM_SAMPS. Furthermore, sampling does not have to start when the line voltage crosses the zero line,
and the length of the accumulation interval need not be an integer multiple of the signal cycles.
833ms
20ms
XFER_BUSY
Interrupt to MPU
Figure 13: Accumulation Interval
Rev 2
29
71M6541D/F/G and 71M6542F/G Data Sheet
IB
VA
IA
122.07 µs
30.5
µs
122.07 µs
122.07 µs
Multiplexer Frame (13 x 30.518 µs = 396.7 µs -> 2520.6 Hz)
MUX_DIV[3:0] = 3 Conversions
Settle
CK32
(32768 Hz)
MUX STATE
S
0
1
S
2
Figure 14: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 3)
VB
IB
VA
IA
91.5 µs
91.5 µs
91.5 µs
30.5 µs
91.5 µs
Multiplexer Frame (13 x 30.518 µs = 396 µs à2520Hz)
MUX_DIV[3:0] = 4 Conversions
Settle
CK32
(32768 Hz)
MUX STATE S
0
1
2
3
S
Figure 15: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 4)
30
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2.4
80515 MPU Core
The 71M6541D/F/G and 71M6542F/G include an 80515 MPU (8-bit, 8051-compatible) that processes
most instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS.
The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and
execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte
instructions are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average
performance improvement (in terms of MIPS) over the Intel 8051 device running at the same clock
frequency.
Table 9 shows the CKMPU frequency as a function of the MCK clock (19.6608 MHz) divided by the MPU
clock divider which is set in the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]). Actual processor
clocking speed can be adjusted to the total processing demand of the application (metering calculations,
AMR management, memory management, LCD driver management and I/O management) using
MPU_DIV[2:0], as shown in Table 9.
Table 9: CKMPU Clock Frequencies
MPU_DIV [2:0]
000
001
010
011
100
101
110
111
CKMPU Frequency
4.9152 MHz
2.4576 MHz
1.2288 MHz
614.4 kHz
307.2 kHz
Typical measurement and metering functions based on the results provided by the internal 32-bit compute
engine (CE) are available for the MPU as part of the Teridian standard library. Teridian provides
demonstration source code to help reduce the design cycle.
2.4.1
Memory Organization and Addressing
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory
organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas:
Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE and MPU,
Configuration or I/O RAM), and internal data memory (Internal RAM). Table 10 shows the memory map.
Program Memory
The 80515 can address up to 64 KB of program memory space (0x0000 to 0xFFFF). Program memory is
read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from program memory location 0x0000. The lower part of
the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte
intervals, starting from 0x0003.
MPU External Data Memory (XRAM)
Both internal and external memory is physically located on the 71M654x device. The external memory
referred in this documentation is only external to the 80515 MPU core.
3 KB of RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first
1 KB, leaving 2 KB for the MPU. Different versions of the CE code use varying amounts. Consult the
documentation for the specific code version being used for the exact limit.
If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is
disabled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] ≠ 0 because the
71M654x ADC writes to these locations. Setting MUX_DIV[3:0] = 0 disables the ADC output
preventing the CE from writing the first 0x40 bytes of RAM.
In addition, MUXn_SEL[3:0] values must be written only after writing MUX_DIV[3:0].
Rev 2
31
71M6541D/F/G and 71M6542F/G Data Sheet
The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX
@DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX
A,@DPTR instruction (PDATA, SFR 0xBF, provides the upper 8 bytes for the MOVX A,@Ri instruction).
Internal and External Memory Map
Table 10 shows the address, type, use and size of the various memory components.
Table 10: Memory Map
Address
(hex)
0000-7FFF
Memory
Technology
Flash Memory
Memory
Type
Name
Program memory
Non-volatile
for MPU and CE
Typical Usage
Memory Size
(bytes)
MPU Program and
non-volatile data
64/32 KB †
CE program (on 1
KB boundary)
3 KB max.
0000-0BFF
Static RAM
Volatile
External RAM
(XRAM)
Shared by CE and
MPU
5/3 KB †
2000-27FF
Static RAM
Volatile
Configuration
RAM (I/O RAM)
Hardware control
2 KB
2800-287F
Static RAM
Non-volatile
(battery)
Configuration
RAM (I/O RAM)
Battery-buffered
memory
128
0000-00FF
Static RAM
Volatile
Internal RAM
Part of 80515 Core
256
† Memory size depends on IC. See 2.5.1 Physical Memory for details.
MOVX Addressing
There are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to
the external data RAM.
In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank provide the eight
lower-ordered bits of address. The eight high-ordered bits of the address are specified with the PDATA
SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the
external data RAM.
In the second type of MOVX instruction, MOVX A,@DPTR, the data pointer generates a 16-bit address.
This form is faster and more efficient when accessing very large data arrays (up to 64 KB), since no
additional instructions are needed to set up the eight high ordered bits of the address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two
with direct access and two with paged access, to the entire external memory range.
Dual Data Pointer
The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that
is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called
DPTR, the second data pointer is called DPTR1. The data pointer select bit, located in the LSB of the DPS
register (DPS[0], SFR 0x92), chooses the active pointer. DPTR is selected when DPS[0] = 0 and DPTR1 is
selected when DPS[0] = 1.
The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers
are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected
DPTR for any activity.
The second data pointer may not be supported by certain compilers.
DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions faster
compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save and
restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency.
By selecting the R80515 core in the Keil compiler project settings and by using the compiler directive
“MODC2”, dual data pointers are enabled in certain library routines.
32
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred
to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction
MOVX A,@Ri or MOVX @Ri,A.
Internal Data Memory Map and Access
The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory
address is always 1 byte wide. Table 11 shows the internal data memory map.
The Special Function Registers (SFR) occupy the upper 128 bytes. The SFR area of internal data memory
is available only by direct addressing. Indirect addressing of this area accesses the upper 128 bytes of
Internal RAM. The lower 128 bytes contain working registers and bit addressable memory. The lower 32
bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW, SFR
0xD0 ) select which bank is in use. The next 16 bytes form a block of bit addressable memory space at
addresses 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect
addressing.
Table 11: Internal Data Memory Map
Address Range
2.4.2
Direct Addressing
Indirect Addressing
Special Function Registers (SFRs)
RAM
0x80
0xFF
0x30
0x7F
Byte addressable area
0x20
0x00
0x2F
0x1F
Bit addressable area
Register banks R0…R7
Special Function Registers (SFRs)
A map of the Special Function Registers is shown in Table 12.
Only a few addresses in the SFR memory space are occupied, the others are not implemented. A read
access to unimplemented addresses returns undefined data, while a write access has no effect. SFRs
specific to the 71M654x are shown in bold print on a shaded field. The registers at 0x80, 0x88, 0x90,
etc., are bit addressable, all others are byte addressable.
Table 12: Special Function Register Map
Hex/
Bin
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
Rev 2
Bit
Addressable
X000
Byte Addressable
X001
X010
INTBITS
VSTAT
B
IFLAGS
A
WDCON
PSW
T2CON
IRCON
IEN1
IP1
S0RELH
P3 (DIO12:15)
FLSHCTL
IEN0
IP0
S0RELL
P2 (DIO8:11)
S0CON
S0BUF
IEN2
DPS
P1(DIO4:7)
TCON
TMOD
TL0
P0 (DIO0:3)
SP
DPL
X011
X100
X101
RCMD
SPI_CMD
X110
S1RELH
S1CON
TL1
DPH
X111
PDATA
FLSHPG
S1BUF
ERASE
TH0
DPL1
S1RELL
TH1
DPH1
EEDATA EECTRL
CKCON
PCON
Bin/
Hex
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
87
33
71M6541D/F/G and 71M6542F/G Data Sheet
2.4.3
Generic 80515 Special Function Registers
Table 13 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional
descriptions of the registers can be found at the page numbers listed in the table.
Table 13: Generic 80515 SFRs - Location and Reset Values
Name
P0
SP
DPL
DPH
DPL1
DPH1
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
P1
DPS
S0CON
S0BUF
IEN2
S1CON
S1BUF
S1RELL
P2
IEN0
IP0
S0RELL
P3
IEN1
IP1
S0RELH
S1RELH
PDATA
IRCON
T2CON
PSW
WDCON
A
B
34
Address
(Hex)
0x80
0x81
0x82
0x83
0x84
0x85
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x90
0x92
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0xA0
0xA8
0xA9
0xAA
0xB0
0xB8
0xB9
0xBA
0xBB
0xBF
0xC0
0xC8
0xD0
0xD8
0xE0
0xF0
Reset value
Description
(Hex)
0xFF
Port 0
0x07
Stack Pointer
0x00
Data Pointer Low 0
0x00
Data Pointer High 0
0x00
Data Pointer Low 1
0x00
Data Pointer High 1
0x00
UART Speed Control
0x00
Timer/Counter Control
0x00
Timer Mode Control
0x00
Timer 0, low byte
0x00
Timer 1, high byte
0x00
Timer 0, low byte
0x00
Timer 1, high byte
0x01
Clock Control (Stretch=1)
0xFF
Port 1
0x00
Data Pointer select Register
0x00
Serial Port 0, Control Register
0x00
Serial Port 0, Data Buffer
0x00
Interrupt Enable Register 2
0x00
Serial Port 1, Control Register
0x00
Serial Port 1, Data Buffer
0x00
Serial Port 1, Reload Register, low byte
0xFF
Port 2
0x00
Interrupt Enable Register 0
0x00
Interrupt Priority Register 0
0xD9
Serial Port 0, Reload Register, low byte
0xFF
Port 3
0x00
Interrupt Enable Register 1
0x00
Interrupt Priority Register 1
0x03
Serial Port 0, Reload Register, high byte
0x03
Serial Port 1, Reload Register, high byte
High address byte for [email protected] - also called USR2
0x00
0x00
Interrupt Request Control Register
0x00
Polarity for INT2 and INT3
0x00
Program Status Word
0x00
Baud Rate Control Register (only WDCON[7] bit used)
0x00
Accumulator
0x00
B Register
Page
36
35
35
35
35
35
39
42
40
39
39
39
39
36
36
32
38
36
42
38
36
36
36
41
45
36
36
41
45
36
36
32
42
42
35
36
35
35
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Accumulator (ACC, A, SFR 0x E0):
ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The
mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC.
B Register (SFR 0xF0):
The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register
to hold temporary data.
Program Status Word (PSW, SFR 0xD0 ):
This register contains various flags and control bits for the selection of the register banks (see Table 14).
Table 14: PSW Bit Functions (SFR 0xD0)
PSW Bit
Symbol
7
6
5
CV
AC
F0
Function
Carry flag.
Auxiliary Carry flag for BCD operations.
General purpose Flag 0 available for user.
F0 is not to be confused with the F0 flag in the CESTATUS register.
4
RS1
3
RS0
2
1
0
OV
–
P
Register bank select control bits. The contents of RS1 and RS0 select the
working register bank:
Bank selected
Location
RS1/RS0
00
Bank 0
0x00 – 0x07
01
Bank 1
0x08 – 0x0F
10
Bank 2
0x10 – 0x17
11
Bank 3
0x18 – 0x1F
Overflow flag.
User defined flag.
Parity flag, affected by hardware to indicate odd or even number of one bits in
the Accumulator, i.e., even parity.
Stack Pointer (SP, SFR 0x81):
The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before
PUSH and CALL instructions, causing the stack to begin at location 0x08.
Data Pointer:
The data pointers (DPTR and DPRT1) are 2 bytes wide. The lower part is DPL (SFR 0x82) and DPL1 (SFR
0x84), respectively. The highest is DPH (SFR 0x83) and DPH1 (SFR 0x85), respectively. The data pointers
can be loaded as two registers (e.g., MOV DPL,#data8). They are generally used to access external
code or data space (e.g., MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
Program Counter:
The program counter (PC) is 2 bytes wide and initialized to 0x0000 after reset. This register is incremented
when fetching operation code or when operating on data from program memory.
Port Registers:
SEGDIO0 through SEGDIO15 are controlled by Special Function Registers P0, P1, P2 and P3 as shown in
Table 15. Above SEGDIO15, the LCD_SEGDIOn[ ] registers in I/O RAM are used. Since the direction bits
are contained in the upper nibble of each SFR Pn register and the DIO bits are contained in the lower nibble,
it is possible to configure the direction of a given DIO pin and set its output value with a single write operation,
thus facilitating the implementation of bit-banged interfaces. Writing a 1 to a DIO_DIR bit configures the
corresponding DIO as an output, while writing a 0 configures it as an input. Writing a 1 to a DIO bit causes
the corresponding pin to be at high level (V3P3), while writing a 0 causes the corresponding pin to be held
at a low level (GND). See 2.5.8 Digital I/O for additional details.
Rev 2
35
71M6541D/F/G and 71M6542F/G Data Sheet
Table 15: Port Registers (SEGDIO0-15)
SFR
Name
P0
P1
P2
P3
SFR
Address
D7
0x80
0x90
0xA0
0xB0
D6
D5
D4
D3
DIO_DIR[3:0]
DIO_DIR[7:4]
DIO_DIR[11:8]
DIO_DIR[15:12]
D2
D1
D0
DIO[3:0]
DIO[7:4]
DIO[11:8]
DIO[15:11]
Ports P0-P3 on the chip are bi-directional and control SEGDIO0-15. Each port consists of a Latch (SFR
P0 to P3), an output driver and an input buffer, therefore the MPU can output or read data through any of
these ports. Even if a DIO pin is configured as an output, the state of the pin can still be read by the
MPU, for example when counting pulses issued via DIO pins that are under CE control.
At power-up SEGDIO0-15 are configured as inputs. It is necessary to write PORT_E = 1 (I/O RAM
0x270C[5]) to enable SEGDIO0-15. The default PORT_E = 0 blocks any momentary output
transient pulses that would otherwise occur when SEGDIO0-15 are reset on power-up.
Clock Stretching (CKCON)
The three low order bits of the CKCON[2:0] (SFR 0x8E) register define the stretch memory cycles that
are used for MOVX instructions when accessing external peripherals. The practical value of this register
for the 71M6541D/F/G and 71M6542F/G is to guarantee access to XRAM between CE, MPU, and SPI.
The default setting of CKCON[2:0] (001) should not be changed.
Table 16 shows how the signals of the External Memory Interface change when stretch values are set
from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the
CKCON[2:0] (001), which is shown in bold in the table, performs the MOVX instructions with a stretch
value equal to 1.
Table 16: Stretch Memory Cycle Width
2.4.4
Read Signal Width
Write Signal Width
CKCON[2:0]
Stretch
Value
memaddr
memrd
memaddr
memwr
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set
and of the associated op-codes is contained in the 71M654X Software User’s Guide (SUG).
2.4.5
UARTs
The 71M6541D/F/G and 71M6542F/G include a UART (UART0) that can be programmed to
communicate with a variety of AMR modules and other external devices. A second UART (UART1) is
connected to the optical port, as described in 2.5.7 UART and Optical Interface.
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor
at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as
follows:
36
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
•
•
UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are
input LSB first.
UART0 TX: This pin is used to output the serial data. The bytes are output LSB first.
Several UART-related registers are available for the control and buffering of serial data.
A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0
and S1BUF, SFR 0x9C for UART1). When written by the MPU, SxBUF acts as the transmit buffer, and
when read by the MPU, it acts as the receive buffer. Writing data to the transmit buffer starts the
transmission by the associated UART. Received data are available by reading from the receive buffer.
Both UARTs can simultaneously transmit and receive data.
WDCON[7] (SFR 0xD8) selects whether timer 1 or the internal baud rate generator is used. All UART
transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for
variable communication baud rates from 300 to 38400 bps. Table 17 shows how the baud rates are
calculated. Table 18 shows the selectable UART operation modes.
Table 17: Baud Rate Generation
Using Timer 1
(WDCON[7] = 0)
smod
UART0
2
UART1
N/A
* f CKMPU/ (384 * (256-TH1))
Using Internal Baud Rate Generator
(WDCON[7] = 1)
smod
2
10
* f CKMPU/(64 * (2 -S0REL))
fCKMPU/(32 * (210-S1REL))
S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers.
(S0RELL, S0RELH, S1RELL, S1RELH are SFR 0xAA, SFR 0xBA, SFR 0x9D and SFR 0xBB, respectively) SMOD
is the SMOD bit in the SFR PCON register (SFR 0x87). TH1(SFR 0x8D) is the high byte of timer 1.
Table 18: UART Modes
UART 0
Mode 0
Mode 1
Mode 2
Mode 3
N/A
Start bit, 8 data bits, stop bit, variable
baud rate (internal baud rate generator
or timer 1)
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of fCKMPU
Start bit, 8 data bits, parity, stop bit,
variable baud rate (internal baud rate
generator or timer 1)
UART 1
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Start bit, 8 data bits, stop bit, variable baud
rate (internal baud rate generator)
N/A
N/A
Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of
8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant
th
1. 8-bit serial modes with parity can be simulated by setting and reading the 9 bit, using the
control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B)
registers for transmit and RB81 bit in S1CON[2] for receive operations.
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals
for inter-processor communication in multi-processor systems. In this case, the slave processors have bit
SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs
th
the slave’s address, it sets the 9 bit to 1, causing a serial port receive interrupt in all the slaves. The
slave processors compare the received byte with their address. If there is a match, the addressed slave
clears SM20 or SM21 and receive the rest of the message. The rest of the slave’s ignores the
th
message. After addressing the slave, the host outputs the rest of the message with the 9 bit set to 0, so
no additional serial port receive interrupts are generated.
Rev 2
37
71M6541D/F/G and 71M6542F/G Data Sheet
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
and S1CON shown in Table 19 and Table 20, respectively, and the PCON register shown in Table 21.
Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice
would be to clear them with a bit operation, but this must be avoided. The hardware implements
bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after
the read, but before the write, its flag is cleared unintentionally.
The proper way to clear these flag bits is to write a byte mask consisting of all ones except for
a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 19: The S0CON (UART0) Register (SFR 0x98)
Bit
S0CON[7]
Symbol
SM0
S0CON[6]
SM1
S0CON[5]
S0CON[4]
S0CON[3]
SM20
REN0
TB80
S0CON[2]
RB80
S0CON[1]
TI0
S0CON[0]
RI0
Function
The SM0 and SM1 bits set the UART0 mode:
Mode
Description
SM0
SM1
0
N/A
0
0
1
8-bit UART
0
1
2
9-bit UART
1
0
3
9-bit UART
1
1
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it performs (parity check, multiprocessor
communication etc.)
th
In Modes 2 and 3 it is the 9 data bit received. In Mode 1, SM20 is 0,
RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by
software.
Transmit interrupt flag; set by hardware after completion of a serial transfer.
Must be cleared by software (see Caution above).
Receive interrupt flag; set by hardware after completion of a serial reception.
Must be cleared by software (see Caution above).
Table 20: The S1CON (UART1) Register (SFR 0x9B)
Bit
S1CON[7]
Symbol
SM
Function
Sets the baud rate and mode for UART1.
SM
0
1
S1CON[5]
S1CON[4]
S1CON[3]
SM21
REN1
TB81
S1CON[2]
RB81
S1CON[1]
TI1
S1CON[0]
RI1
38
Mode
A
B
Description
9-bit UART
8-bit UART
Baud Rate
variable
variable
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Mode A. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.)
th
In Modes A and B, it is the 9 data bit received. In Mode B, if SM21 is 0,
RB81 is the stop bit. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software (see Caution above).
Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software (see Caution above).
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 21: PCON Register Bit Description (SFR 0x87)
Bit
PCON[7]
2.4.6
Symbol
SMOD
Function
The SMOD bit doubles the baud rate when set
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured
for counter or timer operations.
In timer mode, the register is incremented every machine cycle, i.e., it counts up once for every 12 periods
of the MPU clock. In counter mode, the register is incremented when the falling edge is observed at the
corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins,
see 2.5.8 Digital I/O). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input
count rate is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, however
to ensure proper recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 22 and Table 23. The
TMOD (SFR 0x89) Register, shown in Table 24, is used to select the appropriate mode. The timer/counter
operation is controlled by the TCON (SFR 0x88) Register, which is shown in Table 25. Bits TR1 (TCON[6])
and TR0 (TCON[4]) in the TCON register start their associated timers when set.
Table 22: Timers/Counters Mode Description
M1
M0
Mode
0
0
Mode 0
0
1
1
0
Mode 1
Mode 2
1
1
Mode 3
Function
13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 (SFR
0x8A or SFR 0x8B) register and the remaining 8 bits in the TH0 or TH1
(SFR 0x8C or SFR 0x8D) register (for Timer 0 and Timer 1, respectively).
The 3 high order bits of TL0 and TL1 are held at zero.
16-bit Counter/Timer mode.
8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or
TH1, while TL0 or TL1 is incremented every machine cycle. When
TL(x) overflows, a value from TH(x) is copied to TL(x) (where x is 0
for counter/timer 0 or 1 for counter/timer 1.
If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent
8-bit Timer/Counters.
In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while TH0
is affected by the TR1 bit, and the TF1 flag is set on overflow.
Table 23 specifies the combinations of operation modes allowed for Timer 0 and Timer 1.
Table 23: Allowed Timer/Counter Mode Combinations
Timer 1
Timer 0 - mode 0
Timer 0 - mode 1
Timer 0 - mode 2
Rev 2
Mode 0
Yes
Yes
Not allowed
Mode 1
Yes
Yes
Not allowed
Mode 2
Yes
Yes
Yes
39
71M6541D/F/G and 71M6542F/G Data Sheet
Table 24: TMOD Register Bit Description (SFR 0x89)
Bit
Symbol Function
Timer/Counter 1
TMOD[7]
Gate
If TMOD[7] is set, external input signal control is enabled for Counter 1. The
TR1 bit in the TCON register (SFR 0x88) must also be set in order for Counter 1 to
increment. With these settings, Counter 1 increments on every falling edge of the
logic signal applied to one or more of the SEGDIO2-11 pins, as specified by the
contents of the DIO_R2 through DIO_R11 registers. See 2.5.8 Digital I/O and
LCD Segment Drivers and Table 47.
TMOD[6]
C/T
Selects timer or counter operation. When set to 1, a counter operation is performed.
When cleared to 0, the corresponding register functions as a timer.
TMOD[5:4] M1:M0
Selects the mode for Timer/Counter 1, as shown in Table 22.
Timer/Counter 0:
TMOD[3]
Gate
If TMOD[3] is set, external input signal control is enabled for Counter 0. The
TR0 bit in the TCON register (SFR 0x88) must also be set in order for Counter 0 to
increment. With these settings, Counter 0 is incremented on every falling edge of
the logic signal applied to one or more of the SEGDIO2-11 pins, as specified by
the contents of the DIO_R2 through DIO_R11 registers. See 2.5.8 Digital I/O and
LCD Segment Drivers and Table 47.
TMOD[2]
C/T
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register functions as a timer.
TMOD[1:0] M1:M0
Selects the mode for Timer/Counter 0 as shown in Table 22.
Table 25: The TCON Register Bit Functions (SFR 0x88)
Bit
TCON[7]
TCON[6]
TCON[5]
TCON[4]
TCON[3]
TCON[2]
TCON[1]
TCON[0]
2.4.7
Symbol Function
TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt is
processed.
TR1
Timer 1 run control bit. If cleared, Timer 1 stops.
TF0
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be
cleared by software and is automatically cleared when an interrupt is processed.
TR0
Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1
Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is
observed. Cleared when an interrupt is processed.
IT1
Interrupt 1 type control bit. Selects either the falling edge or low level on input pin
to cause an interrupt.
IE0
Interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is
observed. Cleared when an interrupt is processed.
IT0
Interrupt 0 type control bit. Selects either the falling edge or low level on input pin
to cause interrupt.
WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard hardware watchdog timer instead (see
2.5.11 Hardware Watchdog Timer).
2.4.8
Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own interrupt request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by
40
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
the corresponding interrupt flag can be individually enabled or disabled by the interrupt enable bits in the
IEN0 (SFR 0xA8), IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A).
Figure 16 shows the device interrupt structure.
Referring to Figure 16, interrupt sources can originate from within the 80515 MPU core (referred to as
Internal Sources) or can originate from other parts of the 71M654x SoC (referred to as External Sources).
There are seven external interrupt sources, as seen in the leftmost part of Figure 16, and in Table 26 and
Table 27 (i.e., EX0-EX6).
Interrupt Overview
When an interrupt occurs, the MPU vectors to the predetermined address as shown in Table 38. Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a return from interrupt instruction, RETI. When a RETI instruction is performed, the
processor returns to the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor also indicates this by setting a flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, and then samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the
interrupt is acknowledged by hardware forcing an LCALL to the appropriate vector address, if the
following conditions are met:
•
•
•
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
•
•
•
•
•
The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 26, Table 27 and Table 28).
The Timer/Counter control registers, TCON and T2CON (see
Table 29 and Table 30).
The interrupt request register, IRCON (see Table 31).
The interrupt priority registers: IP0 and IP1 (see Table 36).
Table 26: The IEN0 Bit Functions (SFR 0xA8)
Bit
IEN0[7]
IEN0[6]
IEN0[5]
IEN0[4]
IEN0[3]
IEN0[2]
IEN0[1]
IEN0[0]
Symbol
EAL
WDT
–
ES0
ET1
EX1
ET0
EX0
Function
EAL = 0 disables all interrupts.
Not used for interrupt control.
Not Used.
ES0 = 0 disables serial channel 0 interrupt.
ET1 = 0 disables timer 1 overflow interrupt.
EX1 = 0 disables external interrupt 1: DIO status change
ET0 = 0 disables timer 0 overflow interrupt.
EX0 = 0 disables external interrupt 0: DIO status change
Table 27: The IEN1 Bit Functions (SFR 0xB8)
Rev 2
Bit
IEN1[7]
IEN1[6]
IEN1[5]
Symbol
–
–
EX6
IEN1[4]
IEN1[3]
EX5
EX4
Function
Not used.
Not used.
EX6 = 0 disables external interrupt 6:
XFER_BUSY, RTC_1S, RTC_1M or RTC_T
EX5 = 0 disables external interrupt 5: EEPROM or SPI
EX4 = 0 disables external interrupt 4: VSTAT
41
71M6541D/F/G and 71M6542F/G Data Sheet
IEN1[2]
IEN1[1]
IEN1[0]
Bit
IEN2[0]
EX3 = 0 disables external interrupt 3: CE_BUSY
EX2 = 0 disables external interrupt 2:
XPULSE, YPULSE, WPULSE or VPULSE
–
Not Used.
Table 28: The IEN2 Bit Functions (SFR 0x9A)
EX3
EX2
Symbol
ES1
Function
ES1 = 0 disables the serial channel 1 interrupt.
Table 29: TCON Bit Functions (SFR 0x88)
Bit
TCON[7]
TCON[6]
TCON[5]
TCON[4]
TCON[3]
TCON[2]
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
TCON[1]
TCON[0]
IE0
IT0
Function
Timer 1 overflow flag.
Not used for interrupt control.
Timer 0 overflow flag.
Not used for interrupt control.
External interrupt 1 flag: DIO status changed
External interrupt 1 type control bit:
0 = interrupt on low level.
1 = interrupt on falling edge.
External interrupt 0 flag: DIO status changed
External interrupt 0 type control bit:
0 = interrupt on low level.
1 = interrupt on falling edge.
Table 30: The T2CON Bit Functions (SFR 0xC8)
Bit
T2CON[7]
T2CON[6]
Symbol
–
I3FR
T2CON[5]
I2FR
T2CON[4:0]
–
Function
Not used.
Polarity control for external interrupt 3: CE_BUSY
0 = falling edge.
1 = rising edge.
Polarity control for external interrupt 2:
XPULSE, YPULSE, WPULSE and VPULSE
0 = falling edge.
1 = rising edge.
Not used.
Table 31: The IRCON Bit Functions (SFR 0xC0)
42
Bit
IRCON[7]
Symbol
–
Function
Not used
IRCON[6]
–
Not used
IRCON[5]
IEX6
IRCON[4]
IEX5
IRCON[3]
IEX4
IRCON[2]
IEX3
1 = External interrupt 6 occurred and has not been cleared:
XFER_BUSY, RTC_1S, RTC_1M or RTC_T
1 = External interrupt 5 occurred and has not been cleared:
EEPROM or SPI
1 = External interrupt 4 occurred and has not been cleared:
VSTAT
1 = External interrupt 3 occurred and has not been cleared:
CE_BUSY
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
IRCON[1]
IEX2
IRCON[0]
–
1 = External interrupt 2 occurred and has not been cleared:
XPULSE, YPULSE, WPULSE or VPULSE
Not used.
TF0 and TF1 (Timer 0 and Timer 1 overflow flags) are automatically cleared by hardware when the
service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service
routine is called).
Rev 2
43
71M6541D/F/G and 71M6542F/G Data Sheet
External MPU Interrupts
The seven external interrupts are the interrupts external to the 80515 core, i.e., signals that originate in
other parts of the 71M654x, for example the CE, DIO, RTC, or EEPROM interface.
The external interrupts are connected as shown in Table 32. The polarity of interrupts 2 and 3 is
programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be
programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts 4
through 6 are defined as rising-edge sensitive. Thus, the hardware signals attached to interrupts 5
and 6 are inverted to achieve the edge polarity shown in Table 32.
Table 32: External MPU Interrupts
External
Interrupt
0
1
2
3
4
5
6
Connection
Polarity
Digital I/O
Digital I/O
CE_PULSE
CE_BUSY
VSTAT (VSTAT[2:0] changed)
EEPROM busy (falling), SPI (rising)
XFER_BUSY (falling), RTC_1SEC, RTC_1MIN, RTC_T
see 2.5.8
see 2.5.8
rising
falling
rising
falling
Flag Reset
automatic
automatic
automatic
automatic
automatic
automatic
manual
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See 2.5.8
Digital I/O for more information.
SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own
flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY,
RTC_1SEC, RTC_1MIN, RTC_T, SPI, PLLRISE and PLLFALL have their own enable and flag bits in
addition to the interrupt 6, 4 and enable and flag bits (see Table 33: Interrupt Enable and Flag Bits).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler.
The other flags, IE_XFER through IE_VPULSE, are cleared by writing a zero to them.
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided. The hardware implements bit operations as a
byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
the write, its flag cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a
zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 33: Interrupt Enable and Flag Bits
Interrupt Enable
Name
EX0
EX1
EX2
EX3
EX4
EX5
EX6
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
44
Location
SFR 0xA8[[0]
SFR 0xA8[2]
SFR 0xB8[1]
SFR 0xB8[2]
SFR 0xB8[3]
SFR 0xB8[4]
SFR 0xB8[5]
0x2700[0]
0x2700[1]
0x2700[2]
0x2700[4]
Interrupt Flag
Name
IE0
IE1
IEX2
IEX3
IEX4
IEX5
IEX6
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
Location
SFR 0x88[1]
SFR 0x88[3]
SFR 0xC0[1]
SFR 0xC0[2]
SFR 0xC0[3]
SFR 0xC0[4]
SFR 0xC0[5]
SFR 0xE8[0]
SFR 0xE8[1]
SFR E0x8[2]
SFR 0xE8[4]
Interrupt Description
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (int 6)
RTC_1SEC interrupt (int 6)
RTC_1MIN interrupt (int 6)
RTC_T alarm clock interrupt (int 6)
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Interrupt Enable
Name
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
Interrupt Flag
Location
0x2701[7]
0x2700[7]
0x2700[6]
0x2700[5]
0x2701[6]
0x2701[5]
Name
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
Location
SFR 0xF8[7]
SFR 0xE8[7]
SFR 0xE8[6]
SFR 0xE8[5]
SFR 0xF8[4]
SFR 0xF8[3]
Interrupt Description
SPI interrupt
EEPROM interrupt
CE_XPULSE interrupt (int 2)
CE_YPULSE interrupt (int 2)
CE_WPULSE interrupt (int 2)
CE_VPULSE interrupt (int 2)
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 34.
Table 34: Interrupt Priority Level Groups
Group
0
1
2
3
4
5
Group Members
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
–
Serial channel 1 interrupt
–
–
–
–
–
–
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 35) by setting or clearing one bit in the SFR interrupt priority register IP0 (SFR 0xA9) and one in IP1
(SFR 0xB9) (Table 36). If requests of the same priority level are received simultaneously, an internal polling
sequence as shown in Table 37 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 35: Interrupt Priority Levels
IP1[x]
0
0
1
1
IP0[x]
0
1
0
1
Priority Level
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
Table 36: Interrupt Priority Registers (IP0 and IP1)
Register
Address
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IP0
IP1
SFR 0xA9
SFR 0xB9
–
–
–
–
IP0[5]
IP1[5]
IP0[4]
IP1[4]
IP0[3]
IP1[3]
IP0[2]
IP1[2]
IP0[1]
IP1[1]
Rev 2
Bit 0
(LSB)
IP0[0]
IP1[0]
45
71M6541D/F/G and 71M6542F/G Data Sheet
External interrupt 0
Serial channel 1 interrupt
Timer 0 interrupt
External interrupt 2
External interrupt 1
External interrupt 3
Timer 1 interrupt
External interrupt 4
Serial channel 0 interrupt
External interrupt 5
External interrupt 6
Polling sequence
Table 37: Interrupt Polling Sequence
Interrupt Sources and Vectors
Table 38 shows the interrupts with their associated flags and vector addresses.
Table 38: Interrupt Vectors
Interrupt
Request Flag
IE0
TF0
IE1
TF1
RI0/TI0
RI1/TI1
IEX2
IEX3
IEX4
IEX5
IEX6
46
Description
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
Serial channel 1 interrupt
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Interrupt Vector
Address
0x0003
0x000B
0x0013
0x001B
0x0023
0x0083
0x004B
0x0053
0x005B
0x0063
0x006B
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
0
External
Source
Internal
Source
Individual
Enable Bits
Individual Flags
DIO
DIO status
changed
DIO_Rn
TCON.1 (IE0)
byte received
UART1
(optical)
Logic and Polarity
Selection
Interrupt
Flags
Interrupt Enable
IEN0.7
(EAL)
IEN0.0
(EX0)
Priority
Assignment
IT0
IEN2.0
(ES1)
S1CON.0 (RI1)
IP1.0/
IP0.0
>=1
byte transmitted
S1CON.1 (TI1)
IEN0.1
(ET0)
Timer 0
XPULSE
YPULSE
2
1
3
overflow occurred
CE detected zero
crossing
CE detected sag
EX_XPULSE
TCON.5 (TF0)
EX_YPULSE
IE_YPULSE
WPULSE
Wh pulse
EX_WPULSE
IE_WPULSE
VPULSE
VARh pulse
EX_VPULSE
IE_VPULSE
DIO_Rn
TCON.3 (IE1)
DIO
CE_BUSY
DIO status
changed
IEN1.1
(EX2)
IE_XPULSE
>=1
I3FR
overflow occurred
VSTAT
IEN0.3
(ET1)
TCON.7 (TF1)
>=1
byte transmitted
5
command
received
XFER_BUSY
accumulation
cycle completed
RTC_1M
RTC_T
EX_EEX
S0CON.0 (TI0)
IEN1.4
(EX5)
IE_EEX
>=1
SPI
RTC_1S
6
BUSY fell
IEN0.4
(ES0)
S0CON.0 (RI0)
UART0
EEPROM
every second
every minute
alarm clock
EX_SPI
IP1.4/
IP0.4
IRCON.4
(IEX5)
IE_SPI
EX_XFER
IE_XFER
EX_RTC1S
IE_RTC1S
EX_RTC1M
IE_RTC1M
IEN1.5
(EX6)
IP1.5/
IP0.5
IRCON.5
(IEX6)
>=1
EX_RTCT
IE_RTCT
Flag=1
means that
an interrupt
has occurred
and has not
been cleared
EX0 – EX6 are cleared
automaticallywhen the
hardware vectors to the
interrupt handler
Interrupt
Vector
3/19/2010
“Internal Source” refers to interrupt sources originating within the 80515 MPU core.
“External Source” refers to interrupt sources outside the 80515 MPU core originating from other parts of the 71M654x SoC.
Figure 16: Interrupt Structure
Rev 2
IP1.3/
IP0.3
IRCON.3
(IEX4)
Supply status changed
byte received
IP1.2/
IP0.2
IRCON.2
(IEX3)
IEN1.3
(EX4)
4
IP1.1/
IP0.1
IEN0.2
(EX1)
IEN1.2
(EX3)
CE completed code run and
has new status information
Timer 1
I2FR
IRCON.1
(IEX2)
Polling Sequence
No.
47
71M6541D/F/G and 71M6542F/G Data Sheet
2.5
On-Chip Resources
2.5.1
Physical Memory
2.5.1.1 Flash Memory
The device includes 128KB (71M6541G, 71M6542G), 64KB (71M6542F, 71M6541F) or 32KB
(71M6541D) of on-chip flash memory. The flash memory primarily contains MPU and CE program code.
It also contains images of the CE RAM and I/O RAM. On power-up, before enabling the CE, the MPU
copies these images to their respective locations.
Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must
begin on a 1-KB boundary of the flash address space. The CE_LCTN[5:0] field (I/O RAM 0x2109[5:0])
defines which 1 KB boundary contains the CE code. Thus, the first CE instruction is located at
1024*CE_LCTN[5:0].
Flash memory can be accessed by the MPU, the CE, and by the SPI interface (R/W).
Table 39: Flash Memory Access
Access by
MPU
CE
SPI
Access
Type
R/W/E
R
R/W/E
Condition
W/E only if CE is disabled.
Access only when SFM is invoked (MPU halted).
Flash Write Procedures
If the FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4] key is correctly programmed, the MPU may write to the
flash memory. This is one of the non-volatile storage options available to the user in addition to external
EEPROM.
The flash program write enable bit, FLSH_PWE (SFR 0xB2[0]), differentiates 80515 data store instructions
([email protected],A) between Flash and XRAM writes. This bit is automatically cleared by hardware
after each byte write operation. Write operations to this bit are inhibited when interrupts are enabled.
If the CE bit is enabled (CE_E = 1, I/O RAM 0x2106[0]), flash write operations must not be attempted unless
FLSH_PSTWR (SFR 0xB2[2]) is set. This bit enables the “posted flash write” capability. FLSH_PSTWR has
no effect when CE_E = 0). When CE_E = 1, however, FLSH_PSTWR delays a flash write until the time
interval between the CE code passes. During this delay time, the FLSH_PEND bit (SFR 0xB2[3]) is high, and
the MPU continues to execute commands. When the CE code pass ends (CE_BUSY falls), the FLSH_PEND
bit falls and the write operation occurs. The MPU can query the FLSH_PEND bit to determine when the
write operation has been completed. While FLSH_PEND = 1, further flash write requests are ignored.
Updating Individual Bytes in Flash Memory
The original state of a flash byte is 0xFF (all bits are 1). Once a value other than 0xFF is written to a flash
memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells
cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this,
the page can be updated in RAM and then written back to the flash memory.
Flash Erase Procedures
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.
These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
•
•
Write 1 to the FLSH_MEEN bit (SFR 0xB2[1]).
Write the pattern 0xAA to the FLSH_ERASE register (SFR 0x94).
The mass erase cycle can only be initiated when the ICE port is enabled.
48
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
The page erase sequence is:
•
•
Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:2]).
Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94).
Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE
operations are blocked. This guarantees the security of the user’s MPU and CE program code. Security
is enabled by MPU code that is executed in a 64 CKMPU cycle pre-boot interval before the primary boot
sequence begins. Once security is enabled, the only way to disable it is to perform a global erase of the
flash, followed by a chip reset.
The first 64 cycles of the MPU boot code are called the pre-boot phase because during this phase the
ICE is inhibited. A read-only status bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU.
Upon completion of pre-boot, the ICE can be enabled and is permitted to take control of the MPU.
The security enable bit, SECURE (SFR 0xB2[6]), is reset whenever the chip is reset. Hardware associated
with the bit permits only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security
feature but may not reset it. Once SECURE is set, the pre-boot code is protected and no external read of
program code is possible.
Specifically, when the SECURE bit is set, the following applies:
•
•
•
The ICE is limited to bulk flash erase only.
Page zero of flash memory, the preferred location for the user’s pre-boot code, may not be
page-erased by either MPU or ICE. Page zero may only be erased with global flash erase.
Write operations to page zero, whether by MPU or ICE are inhibited.
The 71M6541D/F/G and 71M6542F/G also include hardware to protect against unintentional Flash write
and erase. To enable flash write and erase operations, a 4-bit hardware key that must be written to the
FLSH_UNLOCK[3:0] field. The key is the binary number ‘0010’. If FLSH_UNLOCK[3:0] is not ‘0010’, the
Flash erase and write operation is inhibited by hardware. Proper operation of this security key requires
that there be no firmware function that writes ‘0010’ to FLSH_UNLOCK[3:0]. The key should be written by
the external SPI master, in the case of SPI flash programming (SFM mode), or through the ICE interface
in the case of ICE flash programming. When a boot loader is used, the key should be sent to the boot
load code which then writes it to FLSH_UNLOCK[3:0]. FLSH_UNLOCK[3:0] is not automatically reset. It
should be cleared when the SPI or ICE has finished changing the Flash. Table 40 summarizes the I/O
RAM registers used for flash security.
Table 40: Flash Security
Name
FLSH_UNLOCK[3:0]
Location
2702[7:4]
Rst
0
Wk
0
SECURE
SFR B2[6]
0
0
Dir Description
R/W Must be a 2 to enable any flash modification.
See the description of Flash security for
more details.
R/W Inhibits erasure of page 0 and flash addresses
above the beginning of CE code as defined by
CE_LCTN[5:0] (I/O RAM 0x2109[5:0]). Also
inhibits the read of flash via the ICE and SPI
ports.
SPI Flash Mode
In normal operation, the SPI slave interface cannot read or write the flash memory. However, the
71M6541D/F/G and 71M6542F/G contain a Special Flash Mode (SFM) that facilitates initial
(production) programming of the flash memory. When the 71M654x is in SFM mode, the SPI interface can
erase, read, and write the flash. Other memory elements such as XRAM and I/O RAM are not
accessible to the SPI in this mode. In order to protect the flash contents, several operations are required
before the SFM mode is successfully invoked.
Details on the SFM are in 2.5.10 (SPI Slave Port).
Rev 2
49
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.1.2 MPU/CE RAM
The 71M6541D includes 3 KB of static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in
the MPU core. The 71M6541D/F/G and the 71M6542F/G include 5 KB of static RAM memory on-chip
(XRAM) plus 256 bytes of internal RAM in the MPU core. The static RAM is used for data storage for
both MPU and CE operations.
2.5.1.3 I/O RAM (Configuration RAM)
The I/O RAM can be seen as a series of hardware registers that control basic hardware functions. I/O
RAM address space starts at 0x2000. The registers of the I/O RAM are listed in Table 74.
The 71M6541D/F/G and 71M6542F/G include 128 bytes non-volatile RAM memory on-chip in the I/O
RAM address space (addresses 0x2800 to 0x287F). This memory section is supported by the voltage
applied at VBAT_RTC and the data in it are preserved in BRN, LCD, and SLP modes as long as the
voltage at VBAT_RTC is within specification.
2.5.2
Oscillator
The oscillator drives a standard 32.768 kHz watch crystal. This type of crystal is accurate and does not
require a high-current oscillator circuit. The oscillator has been designed specifically to handle watch
crystals and is compatible with their high impedance and limited power handling capability. The oscillator
power dissipation is very low to maximize the lifetime of any battery attached to VBAT_RTC.
Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to 2.5.4, Real-Time
Clock (RTC) for more information.
The oscillator is powered from the V3P3SYS pin or from the VBAT_RTC pin, depending on the V3OK
internal bit (i.e., V3OK = 1 if V3P3SYS ≥ 2.8 VDC and V3OK = 0 if V3P3SYS < 2.8 VDC). The oscillator
requires approximately 100 nA, which is negligible compared to the internal leakage of a battery.
2.5.3
PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz crystal oscillator output that is multiplied by a PLL by
600 to produce 19.660800 MHz, the master clock (MCK). All on-chip timing, except for the RTC clock, is
derived from MCK. Table 41 provides a summary of the clock functions and their controls.
The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see 2.4.6
Timers and Counters).
The master clock can be boosted to 19.66 MHz by setting the PLL_FAST bit = 1 (I/O RAM 0x2200[4]) and
can be reduced to 6.29 MHz by PLL_FAST = 0. The MPU clock frequency CKMPU is determined by
another divider controlled by the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) and can be
-(MPU_DIV+2)
, where MPU_DIV[2:0] may vary from 0 to 4. The 71M654x V3P3SYS supply
set to MCK*2
current is reduced by reducing the MPU clock frequency. When the ICE_E pin is high, the circuit also
generates the 9.83 MHz clock for use by the emulator.
The PLL is only turned off in SLP mode or in LCD mode when LCD_BSTE is disabled. The LCD_BSTE
value depends on the setting of the LCD_VMODE [1:0] field (see Table 56).
When the part is waking up from SLP or LCD modes, the PLL is turned on in 6.29 MHz mode, and the PLL
frequency is not be accurate until the PLL_OK flag (SFR 0xF9[4]) rises. Due to potential overshoot, the MPU
should not change the value of PLL_FAST until PLL_OK is true.
50
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 41: Clock System Summary
Clock
OSC
Crystal
MCK
Crystal/PLL
CKCE
MCK
CKADC
MCK
CKMPU
MCK
CKICE
MCK
CKOPTMOD
MCK
CK32
MCK
2.5.4
Fixed Frequency or Range
Derived
From
PLL_FAST=1
PLL_FAST=0
Controlled by
Function
32.768 kHz
–
Crystal clock
19.660800 MHz
6.291456 MHz
PLL_FAST
Master clock
(600*CK32)
(192*CK32)
4.9152 MHz
1.5728 MHz
–
CE clock
1.572864 MHz,
4.9152 MHz,
ADC_DIV
ADC clock
2.4576 MHz
0.786432 MHz
4.9152 MHz … 1.572864 MHz…
MPU_DIV[2:0] MPU clock
307.2 kHz
98.304 kHz
9.8304 MHz… 3.145728 MHz …
MPU_DIV[2:0]
ICE clock
196.608 kHz
614.4 kHz
Optical
UART
38.40 kHz
38.6 kHz
–
Modulation
32.768 kHz
–
32 kHz clock
Real-Time Clock (RTC)
2.5.4.1 RTC General Description
The RTC is driven directly by the crystal oscillator and is powered by either the V3P3SYS pin or the
VBAT_RTC pin, depending on the V3OK internal bit. The RTC consists of a counter chain and output
registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of
month, month, and year. The chain registers are supported by a shadow register that facilitates read
and write operations.
Table 42 shows the I/O RAM registers for accessing the RTC.
2.5.4.2 Accessing the RTC
Two bits, RTC_RD (I/O RAM 0x2890[6]) and RTC_WR (I/O RAM 0x2890[7]), control the behavior of the
shadow register.
When RTC_RD is low, the shadow register is updated by the RTC after each two milliseconds. When
RTC_RD is high, this update is halted and the shadow register contents become stationary and are suitable
to be read by the MPU. Thus, when the MPU wishes to read the RTC, it freezes the shadow register by
setting the RTC_RD bit, reads the shadow register, and then lowers the RTC_RD bit to let updates to the
shadow register resume. Since the RTC clock is only 500Hz, there may be a delay of approximately 2 ms
from when the RTC_RD bit is lowered until the shadow register receives its first update. Reads to RTC_RD
continue to return a one until the first shadow update occurs.
When RTC_WR is high, the update of the shadow register is also inhibited. During this time, the MPU may
overwrite the contents of the shadow register. When RTC_WR is lowered, the shadow register is written into
the RTC counter on the next 500Hz RTC clock. A change bit is included for each word in the shadow
register to ensure that only programmed words are updated when the MPU writes a zero to RTC_WR.
Reads of RTC_WR returns one until the counter has actually been updated by the register.
The sub-second register of the RTC, RTC_SBSC (I/O RAM 0x2892), can be read by the MPU after the one
second interrupt and before reaching the next one second boundary. The RTC_SBSC register is expressed
as a count of 1/128 second periods remaining until the next one second boundary. Writing 0x00 to
RTC_SBSC resets the counter re-starting the count from 0 to 127. Reading and resetting the sub-second
counter can be used as part of an algorithm to accurately set the RTC.
The RTC is capable of processing leap years. Each counter has its own output register. The RTC chain
registers are not affected by the reset pin, watchdog timer resets, or by transitions between the battery
modes and mission mode.
Rev 2
51
71M6541D/F/G and 71M6542F/G Data Sheet
Table 42: RTC Control Registers
Name
RTC_ADJ[6:0]
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
RTC_Q[1:0]
Location
Rst
Wk
Dir
Description
2504[6:0]
289B[2:0]
289C[7:0]
289D[7:2]
289D[1:0]
00
4
0
0
0
–
4
0
0
0
R/W Register for analog RTC frequency adjustment.
R/W
Registers for digital RTC adjustment.
0x0FFBF ≤ RTC_P ≤ 0x10040
RTC_RD
2890[6]
0
0
RTC_WR
2890[7]
0
0
RTC_FAIL
2890[4]
0
0
RTC_SBSC[7:0]
2892[7:0]
R/W Register for digital RTC adjustment.
Freezes the RTC shadow register so it is suitable for
R/W MPU reads. When RTC_RD is read, it returns the
status of the shadow register: 0 = up to date, 1 = frozen.
Freezes the RTC shadow register so it is suitable for
MPU write operations. When RTC_WR is cleared,
the contents of the shadow register written to the RTC
R/W counter on the next RTC clock (~500 Hz). When
RTC_WR is read, it returns 1 as long as RTC_WR is
set. It continues to return one until the RTC counter is
updated.
Indicates that a count error has occurred in the RTC
R/W and that the time is not trustworthy. This bit can be
cleared by writing a 0.
Time remaining since the last 1 second boundary.
R
LSB = 1/128 second.
2.5.4.3 RTC Rate Control
Two rate adjustment mechanisms are available:
•
•
The first rate adjustment mechanism is an analog rate adjustment, using the I/O RAM register
RTCA_ADJ[6:0] (I/O RAM 0x2504[6:0]), that trims the crystal load capacitance.
The second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency
is processed in the RTC.
Setting RTCA_ADJ[6:0] to 00 minimizes the load capacitance, maximizing the oscillator frequency. Setting
RTCA_ADJ[6:0] to 7F maximizes the load capacitance, minimizing the oscillator frequency. The adjustable
capacitance is approximately:
C ADJ =
RTCA _ ADJ
⋅ 16.5 pF
128
The precise amount of adjustment depends on the crystal properties, the PCB layout and the value of the
external crystal capacitors. The adjustment may occur at any time, and the resulting clock frequency should
be measured over a one-second interval.
The second rate adjustment is digital, and can be used to adjust the clock rate up to ±988ppm, with a
resolution of 3.8 ppm (±1.9 ppm). Note that 3.8 ppm corresponds to 1-LSB of the 19-bit quantity formed
by 4*RTCP+RTCQ and 1.9 ppm corresponds to ½-LSB. The rate adjustment is implemented starting at
the next second-boundary following the adjustment. Since the LSB results in an adjustment every four
seconds, the frequency should be measured over an interval that is a multiple of four seconds.
The clock rate is adjusted by writing the appropriate values to RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C,
0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x289D[1:0]). Updates to RTC rate adjust registers, RTC_P and
RTC_Q, are done through the shadow register described above. The new values are loaded into the
counters when RTC_WR (I/O RAM 0x2890[7]) is lowered.
The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency by ∆ ppm,
RTC_P and RTC_Q are calculated using the following equation:
52
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
 32768 ⋅ 8

+ 0.5 
4 ⋅ RTC_P + RTC_Q = floor 
−6
 1 + ∆ ⋅10

Conversely, the amount of ppm shift for a given value of 4RTC_P+RTC_Q is:
32768 ∙ 8
− 1� 106
∆ () = �
4 ∗  + 
For example, for a shift of -988 ppm, 4⋅RTC_P + RTC_Q = 262403 = 0x40103. RTC_P = 0x10040, and
RTC_Q = 0x03. The default values of RTC_P and RTC_Q, corresponding to zero adjustment, are 0x10000
and 0x0, respectively.
Two settings for the TMUX2OUT test pin, PULSE_1S and PULSE_4S, are available for measuring and
calibrating the RTC clock frequency. These are waveforms of approximately 25% duty cycle with 1s or 4s
period.
Default values for RTCA_ADJ, RTC_P and RTC_Q should be nominal values, at the center of
the adjustment range. Un-calibrated extreme values (zero, for example) can cause incorrect
operation.
If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC
time as necessary. Alternatively, the characteristics can be loaded into an NV RAM and the OSC_COMP
bit (I/O RAM 0x28A0[5]) may be set. In this case, the oscillator is adjusted automatically, even in SLP
mode. See the Real Time RTC Temperature Compensation section for details.
2.5.4.4 RTC Temperature Compensation
The 71M6541D/F/G and 71M6542F/G can be configured to regularly measure die temperature, including
in SLP and LCD modes and while the MPU is halted. If enabled by the OSC_COMP bit, the temperature
information is automatically used to correct for the temperature variation of the crystal. A table look-up
method is used which generates the required digital compensation without involvement from the MPU.
Storage for the look-up table is in a dedicated 128 byte NV RAM.
Table 43 shows the I/O RAM registers involved in automatic RTC temperature compensation.
Table 43: I/O RAM Registers for RTC Temperature Compensation
Name
OSC_COMP
Location
28A0[5]
Rst
Wk
Dir
0
0
R/W
STEMP[10:3]
STEMP[2:0]
2881[7:0]
2882[7:5]
–
–
R
LKPADDR[6:0]
2887[6:0]
0
0
R/W
LKPAUTOI
2887[7]
0
0
R/W
LKPDAT[7:0]
2888[7:0]
0
0
R/W
LKP_RD
LKP_WR
2889[1]
2889[0]
0
0
0
0
R/W
R/W
Rev 2
Description
Enables the automatic update of RTC_P and RTC_Q
every time the temperature is measured.
The result of the temperature measurement (10-bits of
magnitude data plus a sign bit).
The complete STEMP[10:0] value can be read and
shifted right in a single 16-bit read operation as shown
in the following code fragment.
volatile int16_t xdata STEMP _at_0x2881;
fa = (float)(STEMP/32);
The address for reading and writing the RTC lookup RAM.
Auto-increment flag. When set, LKPADDR[6:0] auto
increments every time LKP_RD or LKP_WR is pulsed.
The incremented address can be read at
LKPADDR[6:0].
The data for reading and writing the RTC lookup RAM.
Strobe bits for the RTC lookup RAM read and write.
When set, the LKPADDR and LKPDAT registers are
used in a read or write operation. When a strobe is
set, it stays set until the operation completes, at which
time the strobe is cleared and LKPADDR is
incremented if LKPAUTOI is set.
53
71M6541D/F/G and 71M6542F/G Data Sheet
Referring to Figure 17, the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0] rightshifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP/4). A limiter ensures
that the resulting look-up address is in the 6-bit plus sign range of -64 to +63 (decimal). The 8-bit NV RAM
content pointed to by the address is added as a 2’s complement value to 0x40000, the nominal value of
4*RTC_P + RTC_Q.
Refer to 2.5.4.3 RTC Rate Control for information on the rate adjustments performed by registers
RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C, 0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x2891[1:0]. The 8-bit
values loaded in to NV RAM must be scaled correctly to produce rate adjustments that are consistent
with the equations given in 2.5.4.3 RTC Rate Control for RTC_P and RTC_Q. Note that the sum of the
8-bit 2’s complement value looked-up and 0x40000 form a 19-bit value, which is equal to
4*RTC_P+RTC_Q, as shown in Figure 17. The output of the Temperature Compensation is automatically
loaded into the RTC_P[16:0] and RTC_Q[1:0] locations after each look-up and summation operation.
LIMIT
STEMP
10+S
>>2
8+S
Look Up
RAM
63
ADDR
-256
-64
63
255
6+S
Q
-64
Σ
7+S
19
4*RTC_P+RTC_Q
19
0x40000
Figure 17: Automatic Temperature Compensation
The 128 NV RAM locations are organized in 2’s complement format as shown in Table 44. As mentioned
above, the STEMP[10:0] digital temperature values are scaled such that the corresponding NV RAM
addresses are equal to STEMP[10:0]/4 (limited in the range of -64 to +63). See 2.5.5 71M654x Temperature
Sensor on page 56 for the equations to calculate temperature in degrees °C from the STEMP[10:0] reading.
The temperature equation is used to calculate the two temperature columns in Table 44 (the second
column and the rightmost column). The second column uses the full 11-bit values of STEMP[10:0], while
the values in the rightmost column are calculated using the post-limiter (6+S) values multiplied by 4.
Since each look-up table address step corresponds to a 4 x 0.325 °C temperature step, two is added to
the post-limiter 6+S value after multiplying by 4 to calculate the temperature values in the rightmost
column. This method ensures that the compensation data is loaded into the look-up table in a manner
that minimizes quantization error. Table 44 shows the numerical values corresponding to each node in
Figure 17. The values of STEMP[10:0] outside the -256 to +255 range are not shown in this table. The
limiter output is confined to the range of -64 to +63, which is directly the desired address of the 128-byte
look-up table. The rightmost column gives the nominal temperature corresponding to each address cell in
the 128-byte compensation table
Table 44: NV RAM Temperature Table Structure
STEMP[10:0]
(10+S)
(decimal)
54
o
Temp ( C)
(Equation)
-256
-61.71
-255
-61.39
-254
-61.06
-253
…
-4
-60.73
…
20.69
-3
21.02
-2
21.35
-1
21.67
STEMP[10:0]>>2
(8+S)
(decimal)
Limiter Output
(6+S)
(decimal)
Temp ( C)
(LU Table)
-64
-64
-61.06
…
…
…
-1
-1
21.35
o
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
0
22.00
1
22.33
2
22.65
3
22.98
4
23.31
5
23.64
6
23.96
7
…
252
24.29
…
104.40
253
104.73
254
105.06
255
105.39
0
0
22.65
1
1
23.96
…
…
…
63
63
105.06
For proper operation, the MPU must load the lookup table with values that reflect the crystal properties
with respect to temperature, which is typically done once during initialization. Since the lookup table is
not directly addressable, the MPU uses the following procedure to load the entire NV RAM table:
1.
2.
3.
4.
5.
6.
Set the LKPAUTOI bit (I/O RAM 0x2887[7]) to enable address auto-increment.
Write zero into the I/O RAM register LKPADDR[6:0] (I/O RAM 0x2887[6:0]).
Write the 8-bit datum into I/O RAM register LKPDAT (I/O RAM 0x2888).
Set the LKP_WR bit (I/O RAM 0x2889[0]) to write the 8-bit datum into NV_RAM
Wait for LKP_WR to clear (LKP_WR auto-clears when the data has been copied to NV RAM).
Repeat steps 3 through 5 until all data has been written to NV RAM.
The NV RAM table can also be read by writing a 1 into the LKP_RD bit (I/O RAM 0x2889[1]). The process of
reading from and writing to the NV RAM is accelerated by setting the LKPAUTOI bit (I/O RAM 0x2887[7]).
When LKPAUTOI is set, LKPADDR[6:0] auto-incremented every time LKP_RD or LKP_WR is pulsed. It is
also possible to perform random access of the NV RAM by writing a 0 to the LKPAUTOI bit and loading the
desired address into LKPADDR[6:0].
If the oscillator temperature compensation feature is not being used, it is possible to use the NV
RAM storage area as ordinary NV storage space using the procedure described above to read and
write NV RAM data. In this case, keep the OSC_COMP bit (I/O RAM 0x28A0[5]) reset to disable the
automatic oscillator temperature compensation feature.
2.5.4.5 RTC Interrupts
The RTC generates interrupts each second and each minute. These interrupts are called RTC_1SEC and
RTC_1MIN. In addition, the RTC functions as an alarm clock by generating an interrupt when the minutes
and hours registers both equal their respective target counts as defined in Table 45. The alarm clock
interrupt is called RTC_T. All three interrupts appear in the MPU’s external interrupt 6. See Table 33
in the interrupt section for the enable bits and flags for these interrupts.
The target registers for minutes and hours are listed in Table 45.
Table 45: I/O RAM Registers for RTC Interrupts
Name
RTC_TMIN[5:0]
RTC_THR[4:0]
Rev 2
Location Rst
289E[5:0] 0
289F[4:0] 0
Wk
0
0
Dir Description
R/W The target minutes register. See RTC_THR[4:0] below.
R/W The target hours register. The RTC_T interrupt occurs
when RTC_MIN becomes equal to RTC_TMIN and
RTC_HR becomes equal to RTC_THR.
55
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.5
71M654x Temperature Sensor
The 71M654x includes an on-chip temperature sensor for determining the temperature of its bandgap
reference. The primary use of the temperature data is to determine the magnitude of compensation
required to offset the thermal drift in the system for the compensation of current, voltage and energy
measurement and the RTC. See 4.7 Metrology Temperature Compensation on page 97. Also see 2.5.4.4
RTC Temperature Compensation on page 53.
Unlike earlier generation Teridian SoCs, the 71M654x does not use the ADC to read the temperature
sensor. Instead, it uses a technique that is operational in SLP and LCD mode, as well as BRN and MSN
modes. This means that the temperature sensor can be used to compensate for the frequency variation
of the crystal, even in SLP mode while the MPU is halted. See 2.5.4.4 RTC Temperature Compensation
on page 53.
In MSN and BRN modes, the temperature sensor is awakened on command from the MPU by setting the
TEMP_START (I/O RAM 0x28B4[6]) control bit. The MPU must wait for the TEMP_START bit to clear before
reading STEMP[10:0] and before setting the TEMP_START bit once again. In SLP and LCD modes, it is
awakened at a regular rate set by TEMP_PER[2:0] (I/O RAM 0x28A0[2:0]).
The result of the temperature measurement can be read from the two I/O RAM locations STEMP[10:3]
(I/O RAM 0x2881) and STEMP[2:0] (I/O RAM 0x2882[7:5]). Note that both of these I/O RAM locations must
be read and properly combined to form the STEMP[10:0] 11-bit value (see STEMP in Table 46). The
resulting 11-bit value is in 2’s complement form and ranges from -1024 to +1023 (decimal). The equations
below are used to calculate the sensed temperature from the 11-bit STEMP[10:0] reading.
The equations below are used to calculate the sensed temperature. The first equation applies when the
71M654x is in MSN mode and TEMP_PWR = 1. The second equation applies when the 71M654x is in
BRN mode, and in this case, the TEMP_PWR and TEMP_BSEL bits must both be set to the same value, so
that the battery that supplies the temperature sensor is also the battery that is measured and reported in
BSENSE. Thus, the second equation requires reading STEMP and BSENSE. In the second equation,
BSENSE (the sensed battery voltage) is used to obtain a more accurate temperature reading when the IC
is in BRN mode.
For the 71M654x in MSN Mode (with TEMP_PWR = 1):
Temp(°C ) = 0.325 ⋅ STEMP + 22
For the 71M654x in BRN Mode, (with TEMP_PWR=TEMP_BSEL):
Temp(oC ) = 0.325 ⋅ STEMP + 0.00218 ⋅ BSENSE 2 − 0.609 ⋅ BSENSE + 64.4
Table 46 shows the I/O RAM registers used for temperature and battery measurement.
If TEMP_PWR selects VBAT_RTC when the battery is nearly discharged, the temperature
measurement may not finish. In this case, firmware may complete the measurement by selecting
V3P3D (TEMP_PWR = 1).
Table 46: I/O RAM Registers for Temperature and Battery Measurement
Name
TBYTE_BUSY
TEMP_PER[2:0]
56
Location
Rst
Wk
Dir
28A0[3]
0
0
R
28A0[2:0]
0
–
R/W
Description
Indicates that hardware is still writing the 0x28A0
byte. Additional writes to this byte are locked out
while it is one. Write duration could be as long as 6 ms.
Sets the period between temperature measurements.
Automatic measurements can be enabled in any
mode (MSN, BRN, LCD, or SLP).
TEMP_PER
0
1-6
7
Time
Manual updates (see TEMP_START)
2 ^ (3+TEMP_PER) (seconds)
Continuous
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
Rst
Wk
Dir
TEMP_BAT
28A0[4]
0
–
R/W
TEMP_START
28B4[6]
0
–
R/W
TEMP_PWR
28A0[6]
0
–
R/W
TEMP_BSEL
28A0[7]
0
–
R/W
0
–
R/W
TEMP_TEST[1:0] 2500[1:0]
STEMP[10:3]
STEMP[2:0]
2881[7:0]
2882[7:5]
BSENSE[7:0]
2885[7:0]
–
–
2704[3]
0
0
BCURR
Description
Causes VBAT to be measured whenever a
temperature measurement is performed.
TEMP_PER[2:0] must be zero in order for TEMP_START
to function. If TEMP_PER[2:0] = 0, then setting
TEMP_START starts a temperature measurement.
Ignored in SLP and LCD modes. Hardware clears
TEMP_START when the temperature measurement is
complete. The MPU must wait for TEMP_START to
clear before reading STEMP[10:0] and before setting
TEMP_START again.
Selects the power source for the temperature sensor:
1 = V3P3D, 0 = VBAT_RTC. This bit is ignored in
SLP and LCD modes, where the temperature sensor is
always powered by VBAT_RTC.
Selects which battery is monitored by the
temperature sensor: 1 = VBAT, 0 = VBAT_RTC
Test bits for the temperature monitor VCO.
TEMP_TEST must be 00 in regular operation. Any
other value causes the VCO to run continuously with
the control voltage described below.
TEMP_TEST
00
01
1X
Function
Normal operation
Reserved for factory test
Reserved for factory test
R
R
The result of the temperature measurement.
To correctly form STEMP[10:0], the MPU must read
0x2881[7:0], shift it left by three bit positions (padding
LSBs with zeros), then read 0x2882[7:5], shift it right
by 5-bits (padding the 5 MSBs with zeros), and then
logically OR the two quantities together.
R The result of the battery measurement.
Connects a 100 µA load to the battery selected by
R/W
TEMP_BSEL.
Refer to the 71M6xxx Data Sheet for information on reading the temperature sensor in the 71M6x01
devices.
2.5.6
71M654x Battery Monitor
The 71M654x temperature measurement circuit can also monitor the batteries at the VBAT and
VBAT_RTC pins. The battery to be tested (i.e., VBAT or VBAT_RTC pin) is selected by TEMP_BSEL (I/O
RAM 0x28A0[7]).
When TEMP_BAT (I/O RAM 0x28A0[4]) is set, a battery measurement is performed as part of each
temperature measurement. The value of the battery reading is stored in register BSENSE[7:0] (I/O RAM
0x2885). The following equation is used to calculate the voltage measured on the VBAT pin (or VBAT_RTC
pin) from the BSENSE[7:0] and STEMP[10:0] values. The result of the equation below is in volts.
VBAT (orVBAT _ RTC ) = 3.293V + ( BSENSE[7 : 0] − 142) ⋅ 0.0246V + STEMP[10 : 0] ⋅ 0.000276V
In MSN mode, a 100 µA de-passivation load can be applied to the selected battery (i.e., selected by the
TEMP_BSEL bit) by setting the BCURR (I/O RAM 0x2704[3]) bit. Battery impedance can be measured by
taking a battery measurement with and without BCURR. Regardless of the BCURR bit setting, the battery
load is never applied in BRN, LCD, and SLP modes.
Rev 2
57
71M6541D/F/G and 71M6542F/G Data Sheet
Refer to the 71M6xxx Data Sheet for information on reading the VCC sensor in the 71M6x01 devices.
2.5.7
UART and Optical Interface
The 71M6541D/F/G and 71M6542F/G provide two asynchronous interfaces, UART0 and UART1. Both
can be used to connect to AMR modules, user interfaces, etc., and also support a mechanism for
programming the on-chip flash memory.
Referring to Figure 19, UART1 includes an interface to implement an IR/optical port. The pin OPT_TX is
designed to directly drive an external LED for transmitting data on an optical link. The pin OPT_RX has
the same threshold as the RX pin, but can also be used to sense the input from an external photo detector
used as the receiver for the optical link. OPT_TX and OPT_RX are connected to a dedicated UART port
(UART1).
The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV (I/O RAM 0x2456[0])
and OPT_RXINV (I/O RAM 0x2457[1]), respectively. Additionally, the OPT_TX output may be modulated at
38 kHz. Modulation is available in MSN and BRN modes (see Table 67). The OPT_TXMOD bit (I/O RAM
0x2456[1]) enables modulation. The duty cycle is controlled by OPT_FDC[1:0] (I/O RAM 0x2457[5:4]) ,
which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A 6.25% duty cycle means that OPT_TX is
low for 6.25% of the period.
When not needed for UART1, OPT_TX can alternatively be configured as SEGDIO51. Configuration is
via the OPT_TXE[1:0] (I/O RAM 0x2456[3:2]) field and LCD_MAP[51] (I/O RAM 0x2405[0]). The
OPT_TXE[1:0] field allows the MPU to select VPULSE, WPULSE, SEGDIO51 or the output of the pulse
modulator to be sourced onto the OPT_TX pin. Likewise, the OPT_RX pin can alternately be configured
as SEGDIO55, and its control is OPT_RXDIS (I/O RAM 0x2457[2]) and LCD_MAP[55] (I/O RAM 0x2405[4]).
VARPULSE
from
OPT_TX UART
OPT_TXINV
3
2
V3P3
Internal
WPULSE
1
DIO2
A
MOD
B
0
EN DUTY
OPT_TXE[1:0]
OPT_TXMOD
OPT_FDC
2
OPT_TX
OPT_TXMOD = 1,
OPT_FDC = 2 (25%)
OPT_TXMOD = 0
A
A
B
B
1/38kHz
Figure 18: Optical Interface
Bit Banged Optical UART (Third UART)
As shown in Figure 19, the 71M654x can also be configured to drive the optical UART with a DIO signal
in a bit banged configuration. When control bit OPT_BB (I/O RAM 0x2022[0]) is set, the optical port is
driven by DIO5 and the SEGDIO5 pin is driven by UART1_TX. This configuration is typically used when
the two dedicated UARTs must be connected to high speed clients and a slower optical UART is
permissible.
58
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Internal
SEG55
DIO55
1
1
OPT_RXDIS
UART1_TX
0
DIO5
1
EN
0
SEG51
VARPULSE
DIO51
B
0
V3P3
SEGDIO51/
OPT_TX
1
2
DUTY
LCD_MAP[55]
3
WPULSE
MOD
A
OPT_TXMOD
OPT_FDC
OPT_TXINV
SEGDIO55/
OPT_RX
0
0
UART1_RX
0
LCD_MAP[51]
1
OPT_TXE[1:0]
SEG5
2
1
0
SEGDIO5/TX2
1
LCD_MAP[5]
OPT_BB
OPT_TXMOD=1,
OPT_FDC=2 (25%)
OPT_TXMOD=0
A
B
1/38kHz
Figure 19: Optical Interface (UART1)
2.5.8
Digital I/O and LCD Segment Drivers
2.5.8.1 General Information
The 71M6541D/F/G and 71M6542F/G combine most DIO pins with LCD segment drivers. Each
SEG/DIO pin can be configured as a DIO pin or as a segment (SEG) driver pin.
On reset or power-up, all DIO pins are DIO inputs (except for SEGDIO0-15, see caution note below) until
they are configured as desired under MPU control. The pin function can be configured by the I/O RAM
registers LCD_MAPn (0x2405 – 0x240B). Setting the bit corresponding to the pin in LCD_MAPn to 1
configures the pin for LCD, setting LCD_MAPn to 0 configures it for DIO.
After reset or power up, pins SEGDIO0 through SEGDIO15 are initially DIO outputs, but are
disabled by PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses during reset. After
configuring pins SEGDIO0 through SEGDIO15 the MPU must enable these pins by setting
PORT_E.
Once a pin is configured as DIO, it can be configured independently as an input or output. For SEGDIO0
to SEGDIO15, this is done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3
(SFR 0xB0), as shown in Table 48 (71M6541D/F/G) and Table 52 (71M6542F/G).
The PB pin is a dedicated digital input and is not part of the SEGDIO system.
The CE features pulse counting registers and each pulse counter interrupt output is internally
routed to the pulse interrupt logic. Thus, no routing of pulse signals to external pins is required in
order to generate pulse interrupts. See interrupt source No. 2 in Figure 16.
A 3-bit configuration word, I/O RAM register DIO_Rn (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can be
used for pins SEGDIO2 through SEGDIO11 (when configured as DIO) and PB to individually assign an
internal resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures
the PB pin). This way, DIO pins can be tracked even if they are configured as outputs. Table 47 lists
the internal resources which can be assigned using DIO_R2[2:0] through DIO_R11[2:0] and DIO_RPB[2:0].
If more than one input is connected to the same resource, the resources are combined using a logical OR.
Table 47: Selectable Resources using the DIO_Rn[2:0] Bits
Value in DIO_Rn[2:0]
Rev 2
Resource Selected for SEGDIOn or PB Pin
0
None
1
Reserved
2
T0 (counter0 clock)
3
T1 (counter1 clock)
4
High priority I/O interrupt (INT0)
59
71M6541D/F/G and 71M6542F/G Data Sheet
Value in DIO_Rn[2:0]
5
Resource Selected for SEGDIOn or PB Pin
Low priority I/O interrupt (INT1)
Note:
Resources are selectable only on SEGDIO2 through SEGDIO11 and the
PB pin. See Table 48 (71M6541D/F/G) and Table 52 (71M6542F/G).
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as
shown in Figure 20, right), not source it from V3P3D (as shown in Figure 20, left). This is due
to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT. See
6.4.6 V3P3D Switch on page 143.
Sourcing current in or out of DIO pins other than those dedicated for wake functions, for
example with pull-up or pull-down resistors, must be avoided. Violating this rule leads to
increased quiescent current in sleep and LCD modes.
MISSION
LCD/SLEEP
BROWNOUT
V3P3SYS
MISSION
LCD/SLEEP
BROWNOUT
VBAT
DIO
HIGH
HIGH-Z
LOW
GNDD
Not recommended
VBAT
V3P3D
V3P3D
HIGH
HIGH-Z
LOW
V3P3SYS
DIO
GNDD
Recommended
Figure 20: Connecting an External Load to DIO Pins
60
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.8.2 Digital I/O for the 71M6541D/F/G
A total of 32 combined SEG/DIO pins plus 5 SEG outputs are available for the 71M6541D/F/G. These
pins can be categorized as follows:
17 combined SEG/DIO segment pins:
o
o
o
o
SEGDIO4…SEGDIO5 (2 pins)
SEGDIO9…SEGDIO14 (6 pins)
SEGDIO19…SEGDIO25 (7 pins)
SEGDIO44…SEGDIO45 (2 pins)
15 combined SEG/DIO segment pins shared with other functions:
o
o
o
o
o
o
o
SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins)
SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
SEGDIO6/XPULSE, SEGDIO7/YPULSE (2 pins)
SEGDIO8/DI (1 pin)
SEGDIO26/COM5, SEGDIO27/COM4 (2 pins)
SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
5 dedicated SEG segment pins are available:
o
o
ICE Inteface pins: SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E_RST (3 pins)
Test Port pins: SEG46/TMUX2OUT, SEG47/TMUXOUT (2 pins)
There are four dedicated common segment outputs (COM0…COM3) plus the two additional shared common
segment outputs that are listed under combined SEG/DIO shared pins (SEGDIO26/COM5,
SEGDIO27/COM4).
Thus, in a configuration where none of these pins are used as DIOs, there can be up to 37 LCD segment
pins with 4 commons, or 35 LCD segment pins with 6 commons. And in a configuration where LCD
segment pins are not used, there can be up to 32 DIO pins.
The configuration for pins SEGDIO19 to SEGDIO27 is shown in Table 49, and the configuration for pins
SEGDIO36-39 and SEGDIO44-45 is shown in Table 50. SEG46 to SEG50 cannot be configured for DIO.
The configuration for pins SEGDIO51 and SEGDIO55 is shown in Table 51.
Table 48: Data/Direction Registers for SEGDIO0 to SEGDIO14 (71M6541D/F/G)
SEGDIO
Pin #
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
Internal Resources
Configurable
(see Table 47)
Rev 2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
–
–
1
2
3
4
5
6
LCD_MAP[14:8] (I/O RAM 0x240A)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 –
LCD_SEG0[5:0] to LCD_SEG14[5:0] (I/O RAM 0x2410[5:0] to 0x241E[5:0]
–
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
P0 (SFR 0x80)
P1 (SFR 0x90)
P2 (SFR 0xA0)
P3 (SFR 0xB0)
–
4
5
6
7
4
5
6
7
4
5
6
7
4
5
6
P0 (SFR 0x80)
P1 (SFR 0x90)
P2 (SFR 0xA0)
P3 (SFR 0xB0)
0
–
1
2
3
4
5
6
7
LCD_MAP[7:0] (I/O RAM 0x240B)
–
Y
Y
Y
Y
Y
Y
0
Y
Y
Y
Y
–
–
–
–
61
71M6541D/F/G and 71M6542F/G Data Sheet
Table 49: Data/Direction Registers for SEGDIO19 to SEGDIO27 (71M6541D/F/G)
SEGDIO
–
–
–
19
20
21
22
23
24
25
26
27
–
–
–
–
Pin #
–
–
–
16
15
14
13
12
11
10
9
8
–
–
–
–
–
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
–
–
–
–
–
–
3
4
5
6
7
0
1
2
3
LCD_MAP[23:19] (I/O RAM 0x2409)
LCD_MAP[27:24] (I/O RAM 0x2408)
–
–
– 19 20 21 22 23 24 25 26 27 –
–
–
–
LCD_SEGDIO19[5:0] to LCD_SEGDIO27[5:0]
(I/O RAM 0x2423[5:0] to 0x242C[5:0])
–
–
– 19 20 21 22 23 24 25 26 27 –
–
–
–
LCD_SEGDIO19[0] to LCD_SEGDIO27[0]
(I/O RAM 0x2423[0] to 0x242C[0])
–
–
– 19 20 21 22 23 24 25 26 27 –
–
–
–
LCD_SEGDIO19[1] to LCD_SEGDIO27[1]
(I/O RAM 0x2423[1] to 0x242C[1])
Table 50: Data/Direction Registers for SEGDIO36-39 to SEGDIO44-45 (71M6541D/F/G)
SEGDIO
Pin #
Configuration:
0 = DIO, 1 = LCD
–
–
–
–
–
–
44
63
45
62
–
–
5
–
–
–
–
–
–
–
–
4
5
6
7
–
–
–
–
4
LCD_MAP[39:36]
LCD_MAP[45:44]
(I/O RAM 0x2407)
(I/O RAM 0x2406)
–
–
36 37 38 39
–
–
–
–
44
LCD_SEGDIO36[5:0] to LCD_SEGDIO45[5:0]
(I/O RAM 0x2434-2437[5:0] to 0x243C-243D[5:0])
–
–
36 37 38 39
–
–
–
–
44
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
(I/O RAM 0x2434-2437[0] to 0x243C-243D[0])
–
–
36 37 38 39
–
–
–
–
44
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
(I/O RAM 0x2434-2437[1] to 0x243C-243D[1])
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
36
3
–
–
37
2
38
1
39
64
–
–
–
–
–
–
–
–
45
45
45
Table 51: Data/Direction Registers for SEGDIO51 and SEGDIO55 (71M6541D/F/G)
SEGDIO
51
–
–
–
55
–
–
–
Pin #
33
–
–
–
32
–
–
–
3
–
–
–
7
–
–
–
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
62
LCD_MAP[55], LDC_MAP[51]
(I/O RAM 0x2405)
–
–
–
–
–
55
–
51
LCD_SEGDIO51[5:0], LCD_SEGDIO55[5:0]
(I/O RAM 0x2443[5:0] and 0x2447[5:0])
–
–
–
–
–
–
51
55
LCD_SEGDIO51[0] to LCD_SEGDIO55[0]
(I/O RAM 0x2443[0] and 0x2447[0])
–
–
–
–
–
–
51
55
LCD_SEGDIO51[1] to LCD_SEGDIO55[1]
(I/O RAM 0x2443[1] and 0x2447[1])
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.8.3 Digital I/O for the 71M6542F/G
A total of 55 combined SEG/DIO pins are available for the 71M6542D/F. These pins can be categorized
as follows:
35 combined DIO/LCD segment pins:
o SEGDIO4…SEGDIO5 (2 pins)
o SEGDIO9…SEGDIO25 (17 pins)
o SEGDIO28…SEGDIO35 (8 pins)
o SEGDIO40…SEGDIO45 (6 pins)
o SEGDIO52…SEGDIO53 (2 pins)
15 combined DIO/LCD segment pins shared with other functions:
o
o
o
o
o
o
o
SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins)
SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
SEGDIO6/XPULSE, SEGDIO7/YPULSE (2 pins)
SEGDIO8/DI (1 pin)
SEGDIO26/COM5, SEGDIO27/COM4 (2 pins)
SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
5 dedicated SEG segment pins are available:
o
o
ICE Inteface pins: SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E_RST (3 pins)
Test Port pins: SEG46/TMUX2OUT, SEG47/TMUXOUT (2 pins)
There are four dedicated common segment outputs (COM0…COM3) plus the two additional shared common
segment outputs that are listed under combined SEG/DIO shared pins (SEGDIO26/COM5,
SEGDIO27/COM4).
Thus, in a configuration where none of these pins are used as DIOs, there can be up to 55 LCD segment
pins with 4 commons, or 53 LCD segment pins with 6 commons. And in a configuration where LCD
segment pins are not used, there can be up to 50 DIO pins.
Example: SEGDIO12 (see pin 32 in Table 52) is configured as a DIO output pin with a value of 1 (high) by
writing 0 to bit 4 of LCD_MAP[15:8], and writing 1 to both P3[4]and P3[0]. The same pin is configured as
an LCD driver by writing 1 to bit 4 of LCD_MAP[15:8]. The display information is written to bits 0 to 5 of
LCD_SEG12.
The configuration for pins SEGDIO16 to SEGDIO31 is shown in Table 53, the configuration for pins
SEGDIO32 to SEGDIO45 is shown in Table 54. SEG46 through SEG50 cannot be configured as DIO
pins. The configuration for pins SEGDIO51 to SEGDIO55 is shown in Table 55.
Table 52: Data/Direction Registers for SEGDIO0 to SEGDIO15 (71M6542F/G)
SEGDIO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin #
45
44
43
42
41
39
38
37
36
35
34
33
32
31
30
29
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
Internal Resources
Configurable
(see Table 47)
Rev 2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LCD_MAP[7:0] (I/O RAM 0x240B)
LCD_MAP[15:8] (I/O RAM 0x240A)
10
11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RAM 0x2410[5:0] to 0x241F[5:0]
0
1
2
3
P0 (SFR 0x80)
0
1
2
3
P1 (SFR 0x90)
0
1
2
3
P2 (SFR 0xA0)
0
1
2
3
P3 (SFR 0xB0)
4
5
6
7
P0 (SFR 0x80)
4
5
6
7
P1 (SFR 0x0)
4
5
6
7
P2 (SFR 0xA0)
4
5
6
7
P3 (SFR 0xB0)
–
–
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
–
–
–
–
63
71M6541D/F/G and 71M6542F/G Data Sheet
Table 53: Data/Direction Registers for SEGDIO16 to SEGDIO31 (71M6542F/G)
SEGDIO
Pin #
16
28
Configuration:
0 = DIO, 1 = LCD
0
SEG Data Register
17
27
18
25
20
23
21
22
22
21
23
20
24
19
25
18
26
17
27
16
28
11
29
10
30
9
31
8
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LCD_MAP[23:16] (I/O RAM 0x2409)
LCD_MAP[31:24] (I/O RAM 0x2408)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0]
(I/O RAM 0x2420[5:0] to 0x242F[5:0])
16
17
18
19
27
28
29
30
31
18
LCD_SEGDIO16[0] to LCD_SEGDIO31[0]
(I/O RAM 0x2420[0] to 0x242F[0])
19 20 21 22 23 24 25 26 27
LCD_SEGDIO16[1] to LCD_SEGDIO31[1]
(I/O RAM 0x2420[1] to 0x242F[1])
28
29
30
31
DIO Data Register
Direction Register:
0 = input, 1 = output
19
24
16
17
20
21
22
23
24
25
26
Table 54: Data/Direction Registers for SEGDIO32 to SEGDIO45 (71M6542F/G)
SEGDIO
Pin #
Configuration:
0 = DIO, 1 = LCD
32
7
33
6
34
5
44
95
45
94
0
1
5
32
33
32
33
32
33
2
3
4
5
6
7
0
1
2
3
4
LCD_MAP[39:32]
LCD_MAP[45:40]
(I/O RAM 0x2407)
(I/O RAM 0x2406[5:0])
34 35 36 37 38 39 40 41 42 43 44
LCD_SEGDIO32[5:0] to LCD_SEGDIO45[5:0]
(I/O RAM 0x2430[5:0] to 0x243D[5:0])
34 35 36 37 38 39 40 41 42 43 44
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
(I/O RAM 0x2430[0] to 0x243D[0])
34 35 36 37 38 39 40 41 42 43 44
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
(I/O RAM 0x2430[1] to 0x243D[1])
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
35
4
36
3
37
2
38
1
39
100
40
99
41
98
42
97
43
96
45
45
45
Table 55: Data/Direction Registers for SEGDIO51 to SEGDIO55 (71M6542F/G)
SEGDIO
51
52
53
54
55
–
–
–
Pin #
53
52
51
47
46
–
–
–
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
64
–
–
–
2
3
4
LCD_MAP[55:51]
(I/O RAM 0x2405[7:3])
–
–
–
51 52 53 54 55
LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0]
(I/O RAM 0x2443[5:0] to 0x2447[5:0])
–
–
–
51 52 53 54 55
LCD_SEGDIO51[0] to LCD_SEGDIO55[0]
(I/O RAM 0x2443[0] to 0x2447[0])
–
–
–
51 52 53 54 55
LCD_SEGDIO51[1] to LCD_SEGDIO55[1]
(I/O RAM 0x2443[1] to 0x2447[1])
0
1
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.8.4 LCD Drivers
The LCD drivers are grouped into up to six commons (COM0 – COM5) and up to 56 segment drivers.
The LCD interface is flexible and can drive 7-segment digits, 14-segments digits or enunciator symbols.
A voltage doubler and a contrast DAC generate VLCD from either VBAT or V3P3SYS, depending on the
V3P3SYS voltage. The voltage doubler, while capable of driving into a 500 kΩ load, is able to generate a
maximum LCD voltage that is within 1 V of twice the supply voltage. The doubler and DAC operate from
a trimmed low-power reference.
The configuration of the VLCD generation is controlled by the I/O RAM field LCD_VMODE[1:0] (I/O RAM
0x2401[7:6]). It is decoded into the LCD_EXT, LDAC_E, and LCD_BSTE internal signals. Table 56
details the LCD_VMODE[1:0] configurations.
Table 56: LCD_VMODE[1:0] Configurations
LCD_VMODE [1:0] LCD_EXT LDAC_E LCD_BSTE
11
1
0
0
10
0
1
1
01
0
1
0
00
0
0
0
Description
External VLCD connected to the VLCD pin.
See note 2 below for the definition of V3P3L.
LCD boost is enabled. The maximum VLCD pin
voltage is 2*V3P3L-1.
In general, the VLCD pin voltage is as follows:
VLCD = max(2*V3P3L-1, 2.5(1+LCD_DAC[4:0]/31)
LCD boost is disabled. The maximum VLCD
voltage is V3P3L.
VLCD = max(V3P3L, 2.5V+2.5*LCD_DAC[4:0]/31)
VLCD=V3P3L, LCD DAC and LCD boost are
disabled. In LCD mode, this setting causes the
lowest battery current.
Notes:
1. LCD_EXT, LDAC_E and LCD_BSTE are 71M654x internal signals which are decoded from
the LCD_VMODE[1:0] control field setting (I/O RAM 0x2401[7:6]). Each of these decoded
signals, when asserted, has the effect indicated in the description column above, and as
summarized below.
LCD_EXT : When set, the VLCD pin expects an external supply voltage
LDAC_E : When set, LCD DAC is enabled
LCD_BSTE : When set, the LCD boost circuit is enabled
2. V3P3L is an internal supply rail that is supplied from either the VBAT pin or the V3P3SYS
pin, depending on the V3P3SYS pin voltage. When the V3P3SYS pin drops below 3.0 VDC,
the 71M654x switches to BRN mode and V3P3L is sourced from the VBAT pin, otherwise
V3P3L is sourced from the V3P3SYS pin while in MSN mode.
When using the VLCD boost circuit, use care when setting the LCD_DAC[4:0] (I/O RAM 0x240D[4:0])
value to ensure that the LCD manufacturer’s recommended operating voltage specification is not
exceeded.
The voltage doubler is active in all LCD modes including the LCD mode when LCD_BSTE = 1. Current
dissipation in LCD mode can be reduced if the boost circuit is disabled and the LCD system is operated
directly from VBAT.
The LCD DAC uses a low-power reference and, within the constraints of VBAT and the voltage doubler,
generates a VLCD voltage of 2.5 VDC + 2.5 * LCD_DAC[4:0]/31.
The LCD_BAT bit (I/O RAM 0x2402[7]) causes the LCD system to use the battery voltage in all power
modes. This may be useful when an external supply is available for the LCD system. The advantage of
connecting the external supply to VBAT, rather than VLCD is that the LCD DAC is still active.
If LCD_EXT = 1, the VLCD pin must be driven from an external source. In this case, the LCD DAC has
no effect.
Rev 2
65
71M6541D/F/G and 71M6542F/G Data Sheet
The LCD system has the ability to drive up to six segments per SEG driver. If the display is configured with
six back planes, the 6-way multiplexing compresses the number of SEG pins required to drive a display and
therefore enhance the number of DIO pins available to the application. Refer to the LCD_MODE[2:0] field
(I/O RAM 0x2400[6:4]) settings (Table 57) for the different LCD multiplexing choices. If 5-state
multiplexing is selected, SEGDIO27 is converted to COM4. If 6-state multiplexing is selected, SEGDIO26
is converted to COM5. These conversions override the SEG/DIO mapping of SEGDIO26 and SEGDIO27.
Additionally, independent of LCD_MODE[2:0], if LCD_ALLCOM = 1, then SEGDIO26 and SEGDIO27
become COM4 and COM5 if their LCD_MAP[ ] bits are set.
The LCD_ON (I/O RAM 0x240C[0]) and LCD_BLANK (I/O RAM 0x240C[1]) bits are an easy way to either
blank the LCD display or turn it fully on. Neither bit affects the contents of the LCD data stored in the
LCDSEG_DIO[ ] registers. In comparison, LCD_RST (I/O RAM 0x240C[2]) clears all LCD data to zero.
LCD_RST affects only pins that are configured as LCD.
A small amount of power can be saved by programming the LCD frequency to the lowest value
that provides satisfactory LCD visibility over the required temperature range.
66
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 57 shows all I/O RAM registers that control the operation of the LCD interface.
Table 57: LCD Configurations
Name
Location Rst
Wk Dir
LCD_ALLCOM
2400[3]
0
–
R/W
LCD_BAT
2402[7]
0
–
R/W
LCD_E
2400[7]
0
–
R/W
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
R/W
R/W
LCD_RST
240C[2]
0
–
R/W
LCD_DAC[4:0]
240D[4:0]
0
–
R/W
LCD_CLK[1:0]
2400[1:0]
0
–
R/W
LCD_MODE[2:0] 2400[6:4]
0
–
R/W
LCD_VMODE[1:0] 2401[7:6]
00
00
R/W
Description
Configures all 6 SEG/COM pins as COM. Has no effect
on pins whose LCD_MAP bit is zero.
Connects the LCD power supply to VBAT in all modes.
Enables the LCD display. When disabled, VLC2,
VLC1, and VLC0 are ground as are the COM and SEG
outputs if their LCD_MAP bit is 1.
LCD_ON = 1 turns on all LCD segments without
affecting the LCD data. Similarly, LCD_BLANK = 1
turns off all LCD segments without affecting the LCD
data. If both bits are set, all LCD segments are turned
on.
Clear all bits of LCD data. These bits affect SEGDIO
pins that are configured as LCD drivers.
This register controls the LCD contrast DAC, which
adjusts the VLCD voltage and has an output range of
2.5 VDC to 5 VDC. The VLCD voltage is
VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31
Thus, the LSB of the DAC is 80.6 mV. The maximum
DAC output voltage is limited by V3P3SYS, VBAT, and
whether LCD_BSTE is set.
Sets the LCD clock frequency (1/T). See definition of T
in Figure 21.
Note: fw = 32768 Hz
00-fw/2^9, 01-fw/2^8, 10-fw/2^7, 11-fw/2^6
The LCD bias and multiplex mode.
Output
LCD_MODE
000
4 states, 1/3 bias
001
3 states, 1/3 bias
010
2 states, ½ bias
011
3 states, ½ bias
100
Static display
101
5 states, 1/3 bias
110
6 states, 1/3 bias
This register specifies how VLCD is generated.
LCD_VMODE Description
11
External VLCD
LCD boost and LCD DAC
10
enabled
01
LCD DAC enabled
No boost and no DAC. VLCD
00
= VBAT or V3P3SYS
The LCD can be driven in static, ½ bias, and 1/3 bias modes. Figure 21 defines the COM waveforms.
Note that COM pins that are not required in a specific mode maintain a ‘segment off’ state rather than
GND, VCC, or high impedance.
The segment drivers SEGDIO22 and SEGDIO23 can be configured to blink at either 0.5 Hz or 1 Hz.
The blink rate is controlled by LCD_Y (I/O RAM 0x2400[2]). There can be up to six pixels/segments
connected to each of these driver pins. The I/O RAM fields LCD_BLKMAP22[5:0] (I/O RAM 0x2402[5:0])
and LCD_BLKMAP23[5:0] (I/O RAM 0x2401[5:0]) identify which pixels, if any, are to blink.
LCD_BLKMAP22[5:0] and LCD_BLKMAP23[5:0] are non-volatile.
Rev 2
67
71M6541D/F/G and 71M6542F/G Data Sheet
The LCD bias may be compensated for temperature using the LCD_DAC[4:0] field (I/O RAM 0x240D[4:0]).
The bias may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in MSN mode and VBAT in BRN
and LCD modes). When the LCD_DAC[4:0] field is set to 000, the DAC is bypassed and powered
down. This can be used to reduce current in LCD mode.
STATIC (LCD_MODE=100)
1/2 BIAS, 2 STATES (LCD_MODE = 010 )
0
1
COM0
COM0
1/2 BIAS, 3 STATES (LCD_MODE = 011 )
0
1
2
COM0
COM1
(1/2)
COM1
COM2
(1/2)
COM2
(1/2)
COM2
COM3
(1/2)
COM3
(1/2)
COM3
(1/2)
COM4
(1/2)
COM4
(1/2)
COM4
(1/2)
COM5
(1/2)
COM5
(1/2)
COM5
(1/2)
COM1
SEG_ON
SEG_ON
SEG_ON
SEG_OFF
SEG_OFF
SEG_OFF
T
1/3 BIAS, 3 STATES (LCD_MODE = 011 )
0
1
2
COM0
1/3 BIAS, 4 STATES (LCD_MODE = 000 )
3
0
1
2
COM0
1/3 BIAS, 6 STATES (LCD_MODE = 110 )
3
4
5
0
1
2
COM0
COM1
COM1
COM1
COM2
COM2
COM2
COM3
COM3
COM4
COM4
COM4
COM5
COM5
COM5
SEG_ON
SEG_ON
SEG_ON
SEG_OFF
SEG_OFF
SEG_OFF
COM3
(2/3)
(1/3)
Figure 21: LCD Waveforms
68
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
LCD Drivers (71M6541D/F/G)
With a maximum of 35 LCD driver pins available, the 71M6541D/F/G is capable of driving up to 6 x 35 =
210 pixels of an LCD display when using the 6 x multiplex mode. At eight pixels per digit, this
corresponds to 26 digits.
LCD segment data is written to the LCD_SEGn[5:0] I/O RAM registers as described in 2.5.8.2 and 2.5.8.3.
SEG46 through SEG50 cannot be configured as DIO pins. Display data for these pins are written to I/O
RAM registers LCD_SEG46[5:0] through LCD_SEG50[5:0] (see Table 58). When the ICE_E pin is pulled
high, it overrides the SEG functionality, and pins E_RXTX/SEG48, E_TCLK/SEG49 and E_RST/SEG50
function as ICE interface pins.
LCD_MAP[46] and LCD_MAP[47] (I/O RAM 0x2406[6] and 0x2407[7]) must be set to 1 in order to permit
TMUX2OUT/SEG46 and TMUXOUT/SEG47 to operate as SEG drivers, otherwise. If LCD_MAP[46] and
LCD_MAP[47] are 0, these pins operate as TMU2XOUT and TMUXOUT (see 2.5.12 Test Ports
(TMUXOUT and TMUX2OUT Pins) on page 78).
Rev 2
49
50
Pin #
61
60
38
37
36
Configuration
Always LCD pins, except
when used for ICE interface
or TMUXOUT/TMUX2OUT.
SEG Data Register
LCD_SEG50[5:0]
48
LCD_SEG49[5:0]
47
LCD_SEG48[5:0]
46
LCD_SEG47[5:0]
SEG
LCD_SEG46[5:0]
Table 58: 71M6541D/F/G LCD Data Registers for SEG46 to SEG50
69
71M6541D/F/G and 71M6542F/G Data Sheet
LCD Drivers (71M6542F/G)
With a maximum of 56 LCD driver pins available, the 71M6542D/F is capable of driving up to 6 x 56 = 336
pixels of an LCD display when using the 6 x multiplex mode. At eight pixels per digit, this corresponds to
42 digits.
LCD segment data is written to the LCD_SEGn[5:0] I/O RAM registers as described in 2.5.8.3 Digital I/O
for the .
SEG46 through SEG50 cannot be configured as DIO pins. Display data for these pins are written to I/O
RAM fields LCD_SEG46[5:0] (I/O RAM 0x243E[5:0]) through LCD_SEG50[5:0] (I/O RAM 0x2442[5:0]); see
Table 59. The associated pins function as ICE interface pins, and the ICE functionality overrides the LCD
function whenever ICE_E is pulled high.
Table 59: 71M6542F/G LCD Data Registers for SEG46 to SEG50
SEG
46
47
48
49
50
Pin #
93
92
58
57
56
2.5.9
LCD_SEGDIO50[5:0]
LCD_SEGDIO49[5:0]
LCD_SEGDIO48[5:0]
LCD_SEGDIO47[5:0]
SEG Data Register
Always LCD pins, except
when used for ICE interface
or TMUXOUT/TMUX2OUT.
LCD_SEGDIO46[5:0]
Configuration:
EEPROM Interface
The 71M6541D/F/G provides hardware support for either a two-pin or a three-wire (µ-wire) type of
EEPROM interface. The interfaces use the SFR EECTRL (SFR 0x9F) and EEDATA (SFR 0x9E)
registers for communication.
2.5.9.1 Two-pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices and is intended for
2
use with I C devices. The interface is multiplexed onto the SEGDIO2 (SDCK) and SEGDIO3 (SDATA)
pins and is selected by setting DIO_EEX[1:0] = 01 (I/O RAM 0x2456[7:6]). The MPU communicates with
the interface through the SFR registers EEDATA and EECTRL. If the MPU wishes to write a byte of data
to the EEPROM, it places the data in EEDATA and then writes the Transmit code to EECTRL. This
initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also asserted when
BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission.
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each
transmission, and then holds in a high state until the next transmission. The EECTRL bits when the
two-pin interface is selected are shown in Table 60.
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Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 60: EECTRL Bits for 2-pin Interface
Status
Bit
Name
Read/
Write
Reset
State
Polarity
Description
7
6
5
ERROR
BUSY
RX_ACK
R
R
R
0
0
1
Positive
Positive
Positive
4
TX_ACK
R
1
Positive
1 when an illegal command is received.
1 when serial data bus is busy.
1 indicates that the EEPROM sent an ACK bit.
1 indicates that an ACK bit has been sent to the
EEPROM.
CMD[3:0]
0000
0010
3:0
CMD[3:0]
W
0000
Positive
0011
0101
0110
1001
Others
Operation
No-op command.
Receive a byte from the EEPROM
and send ACK.
Transmit a byte to the EEPROM.
Issue a STOP sequence.
Receive the last byte from the
EEPROM and do not send ACK.
Issue a START sequence.
No operation, set the ERROR bit.
The EEPROM interface can also be operated by controlling the DIO2 and DIO3 pins directly. The
direction of the DIO line can be changed from input to output and an output value can be written
with a single write operation, thus avoiding collisions (see Table 15 Port Registers (SEGDIO0-15)).
Therefore, no resistor is required in series SDATA to protect against collisions.
2.5.9.2 Three-wire (µ-Wire) EEPROM Interface with Single Data Pin
A 500 kHz three-wire interface, using SDATA, SDCK, and a DIO pin for CS is available. The interface is
selected by setting DIO_EEX[1:0] = 10. The EECTRL bits when the three-wire interface is selected are
shown in Table 61. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM
or read from the EEPROM, depending on the values of the EECTRL bits.
2.5.9.3 Three-wire (µ-Wire/SPI) EEPROM Interface with Separate Di/DO Pins
If DIO_EEX[1:0]=11, the three-wire interface is the same as above, except DI and DO are separate pins.
In this case, SEGDIO3 becomes DO and SEGDIO8 becomes DI. The timing diagrams are the same as
for DIO_EEX[1:0]=10 except that all output data appears on DO and all input data is expected on DI. In
this mode, DI is ignored while data is being received on DO. This mode is compatible with SPI modes 0,0
and 1,1 where data is shifted out on the falling edge of the clock and is strobed in on the rising edge of
the clock.
Table 61: EECTRL Bits for the 3-wire Interface
Control
Bit
Name
Read/
Write
7
WFR
W
6
BUSY
R
5
HiZ
W
Rev 2
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY is delayed until
a rising edge is seen on the data line. This bit can be used during the
last byte of a Write command to cause the INT5 interrupt to occur when
the EEPROM has finished its internal write sequence. This bit is ignored
if Hi-Z=0.
Asserted while the serial data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
Indicates that the SD signal is to be floated to high impedance immediately
after the last SDCK rising edge.
71
71M6541D/F/G and 71M6542F/G Data Sheet
4
RD
W
3:0
CNT[3:0]
W
Indicates that EEDATA (SFR 0x9E) is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data are read MSB first, and right
justified into the low order bits of EEDATA. If RD=0, CNT bits are sent
MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA simply obeys the HiZ bit.
The timing diagrams in Figure 22 through Figure 26 describe the 3-wire EEPROM interface behavior. All
commands begin when the EECTRL (SFR 0x9F) register is written. Transactions start by first raising the
DIO pin that is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 22
through Figure 26 are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM is
driving SDATA, but transitions to Hi-Z (high impedance) when CS falls. The firmware should then
immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a
low-Z state.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- No HiZ
SCLK (output)
SDATA (output)
D7
D6
D5
SDATA output Z
D4
D3
D2
(LoZ)
BUSY (bit)
Figure 22: 3-wire Interface. Write Command, HiZ=0.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ
SCLK (output)
SDATA (output)
D7
D6
D5
SDATA output Z
D4
D3
D2
(LoZ)
(HiZ)
BUSY (bit)
Figure 23: 3-wire Interface. Write Command, HiZ=1
EECTRL Byte Written
INT5
CNT Cycles (8 shown)
READ
SCLK (output)
SDATA (input)
SDATA output Z
D7
D6
D5
D4
D3
D2
D1
D0
(HiZ)
BUSY (bit)
Figure 24: 3-wire Interface. Read Command.
72
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
EECTRL Byte Written
INT5 not issued
CNT Cycles (0 shown)
Write -- No HiZ
EECTRL Byte Written
Write -- HiZ
INT5 not issued
CNT Cycles (0 shown)
SCLK (output)
SCLK (output)
SDATA (output)
SDATA (output)
D7
SDATA output Z
SDATA output Z
(LoZ)
(HiZ)
BUSY (bit)
BUSY (bit)
Figure 25: 3-Wire Interface. Write Command when CNT=0
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ and WFR
SCLK (output)
SDATA (out/in)
D7
D6
D5
(From 654x)
SDATA output Z
(LoZ)
D4
D3
D2
BUSY
READY
(From EEPROM)
(HiZ)
BUSY (bit)
Figure 26: 3-wire Interface. Write Command when HiZ=1 and WFR=1.
2.5.10 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
and I/O RAM locations. It is also able to send commands to the MPU. The interface to the slave port
consists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. These pins are multiplexed with the
combined DIO/LCD segment driver pins SEGDIO36 to SEGDIO39.
Additionally, the SPI interface allows flash memory to be read and to be programmed. To facilitate flash
programming, cycling power or asserting RESET causes the SPI port pins to default to SPI mode. The
SPI port is disabled by clearing the SPI_E bit (I/O RAM 0x270C[4]).
Possible applications for the SPI interface are:
1) An external host reads data from CE locations to obtain metering information. This can be used in
applications where the 71M654x function as a smart front-end with preprocessing capability. Since
the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, I/O RAM, but
not SFRs or the 80515-internal register bank.
2) A communication link can be established via the SPI interface: By writing into MPU memory locations,
the external host can initiate and control processes in the 71M654x MPU. Writing to a CE or MPU
location normally generates an interrupt, a function that can be used to signal to the MPU that the
byte that had just been written by the external host must be read and processed. Data can also be
inserted by the external host without generating an interrupt.
3) An external DSP can access front-end data generated by the ADC. This mode of operation uses the
71M654x as an analog front-end (AFE).
4) Flash programming by the external host (SPI Flash Mode).
SPI Transactions
A typical SPI transaction is as follows. While SPI_CSZ is high, the port is held in an initialized/reset state.
During this state, SPI_DO is held in Hi-Z state and all transitions on SPI_CLK and SPI_DI are ignored.
When SPI_CSZ falls, the port begins the transaction on the first rising edge of SPI_CLK. As shown in
Table 62, a transaction consists of an optional 16 bit address, an 8 bit command, an 8 bit status byte,
followed by one or more bytes of data. The transaction ends when SPI_CSZ is raised. Some transactions
may consist of a command only.
Rev 2
73
71M6541D/F/G and 71M6542F/G Data Sheet
When SPI_CSZ rises, SPI command bytes that are not of the form x000 0000 update the SPI_CMD (SFR
0xFD) register and then cause an interrupt to be issued to the MPU. The exception is if the transaction was
a single byte. In this case, the SPI_CMD byte is always updated and the interrupt issued. SPI_CMD is not
cleared when SPI_CSZ is high.
The SPI port supports data transfers up to 10 Mb/s. A serial read or write operation requires at least 8
clocks per byte, guaranteeing SPI access to the RAM is no faster than 1.25 MHz, thus ensuring that SPI
access to DRAM is always possible.
Table 62: SPI Transaction Fields
Field
Name
Address
Command
Required
Yes, except for
single-byte
transaction
Yes
Size
(bytes)
2
1
Status
Yes, if transaction
includes DATA
1
Data
Yes, if transaction
includes DATA
1 or
more
Description
16-bit address. The address field is not required if the
transaction is a simple SPI command.
8-bit command. This byte can be used as a command to the
MPU. In multi-byte transactions, the MSB is the R/W bit.
Unless the transaction is multi-byte and SPI_CMD is exactly
0x80 or 0x00, the SPI_CMD register is updated and an SPI
interrupt is issued. Otherwise, the SPI_CMD register is
unchanged and the interrupt is not issued.
8-bit status field, indicating the status of the previous
transaction. This byte is also available in the MPU memory
map as SPI_STAT (I/O RAM 0x2708) register. See Table 64
for the contents.
The read or write data. Address is auto incremented for
each new byte.
The SPI_STAT byte is output on every SPI transaction and indicates the parity of the previous transaction
and the error status of the previous transaction. Potential error sources are:
•
•
71M654x not ready.
Transaction not ending on a byte boundary.
SPI Safe Mode
Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus
disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI
SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte transfer
region at address 0x400 to 0x40F. If the SPI host needs to write to other addresses, it must use the
SPI_CMD register to request the write operation from the MPU. SPI SAFE mode is enabled by the
SPI_SAFE bit (I/O RAM 0x270C[3]).
Single-Byte Transaction
If a transaction is a single byte, the byte is interpreted as SPI_CMD. Regardless of the byte value, singlebyte transactions always update the SPI_CMD register and cause an SPI interrupt to be generated.
Multi-Byte Transaction
As shown in Figure 27, multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a status byte,
and a sequence of data bytes. A multi byte transaction is three or more bytes.
74
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
SERIAL READ
16 bit Address
Status Byte
8 bit CMD
DATA[ADDR]
DATA[ADDR+1]
(From Host) SPI_CSZ
Extended Read . . .
0
15
16
A0
C7
23
31
24
32
39
40
D0
D7
47
(From Host) SPI_CK
(From Host) SPI_DI
A15
A14
A1
C6
C5
C0
HI Z
(From 654x) SPI_DO
SERIAL WRITE
x
ST7
16 bit Address
ST6
ST5
ST0
D7
D6
Status Byte
8 bit CMD
D1
DATA[ADDR]
D6
D1
D0
DATA[ADDR+1]
(From Host) SPI_CSZ
Extended Write . . .
0
15
16
A0
C7
23
31
24
32
39
40
D0
D7
47
(From Host) SPI_CK
(From Host) SPI_DI
x
A15
A14
A1
HI Z
(From 654x) SPI_DO
C6
C5
D7
C0
ST7
ST6
ST5
D6
D1
D6
D1
D0
x
ST0
Figure 27: SPI Slave Port - Typical Multi-Byte Read and Write operations
Table 63: SPI Command Sequences
Command Sequence
ADDR 1xxx xxxx STATUS
Byte0 ... ByteN
0xxx xxxx ADDR Byte0 ...
ByteN
Rev 2
Description
Read data starting at ADDR. ADDR auto-increments until SPI_CSZ is
raised. Upon completion, SPI_CMD (SFR 0xFD) is updated to 1xxx xxxx
and an SPI interrupt is generated. The exception is if the command byte
is 1000 0000. In this case, no MPU interrupt is generated and SPI_CMD
is not updated.
Write data starting at ADDR. ADDR auto-increments until SPI_CSZ is
raised. Upon completion, SPI_CMD is updated to 0xxx xxxx and an SPI
interrupt is generated. The exception is if the command byte is 0000
0000. In this case, no MPU interrupt is generated and SPI_CMD is not
updated.
75
71M6541D/F/G and 71M6542F/G Data Sheet
Table 64: SPI Registers
Name
EX_SPI
SPI_CMD
Location
Rst
Wk
Dir
Description
2701[7]
SFR FD[7:0]
0
–
0
–
R/W
R
SPI_E
270C[4]
1
1
R/W
IE_SPI
SFR F8[7]
0
0
R/W
SPI_SAFE
270C[3]
0
0
R/W
SPI_STAT
2708[7:0]
0
0
R
SPI interrupt enable bit.
SPI command. The 8-bit command from the bus master.
SPI port enable bit. It enables the SPI interface on pins
SEGDIO36 – SEGDIO39.
SPI interrupt flag. Set by hardware, cleared by writing a 0.
Limits SPI writes to SPI_CMD and a 16 byte region in
DRAM when set. No other write operations are permitted.
SPI_STAT contains the status results from the previous
SPI transaction.
Bit 7: Ready error: The 71M654x was not ready to read
or write as directed by the previous command.
Bit 6: Read data parity: This bit is the parity of all bytes
read from the 71M654x in the previous command. Does
not include the SPI_STAT byte.
Bit 5: Write data parity: This bit is the overall parity of the
bytes written to the 71M654x in the previous command.
It includes CMD and ADDR bytes.
Bit 4-2: Bottom 3 bits of the byte count. Does not include
ADDR and CMD bytes. One, two, and three byte
instructions return 111.
Bit 1: SPI FLASH mode: This bit is zero when the TEST
pin is zero.
Bit 0: SPI FLASH mode ready: Used in SPI FLASH
mode. Indicates that the flash is ready to receive
another write instruction.
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71M6541D/F/G and 71M6542F/G Data Sheet
SPI Flash Mode (SFM)
In normal operation, the SPI slave interface cannot read or write the flash memory. However, the
71M6541D/F/G and 71M6542F/G support an SPI Flash Mode (SFM) which facilitates initial programming
of the flash memory. When in SFM mode, the SPI can erase, read, and write the flash memory. Other
memory elements such as XRAM and I/O RAM are not accessible in this mode. In order to protect the
flash contents, several operations are required before the SFM mode is successfully invoked.
In SFM mode, n byte reads and dual-byte writes to flash memory are supported. See the SPI Transactions
description on Page 73 for the format of read and write commands. Since the flash write operation is always
based on a two-byte word, the initial address must always be even. Data is written to the 16-bit flash
memory bus after the odd word is written.
In SFM mode, the MPU is completely halted. For this reason, the interrupt feature described in the SPI
Transaction section above is not available in SFM mode. The 71M6541D/F/G and 71M6542F/G must be
reset by the WD timer or by the RESET pin in order to exit SFM mode.
Invoking SFM
The following conditions must be met prior to invoking SFM:
•
•
•
•
•
Pin ICE_E = 1. This disables the watchdog and adds another layer of protection against inadvertent
Flash corruption.
The external power source (V3P3SYS, V3P3A) is at the proper level (> 3.0 VDC).
PREBOOT = 0 (SFR 0xB2[7]). This validates the state of the SECURE bit (SFR 0xB2[6]).
SECURE = 0. This I/O RAM register indicates that SPI secure mode is not enabled. Operations are
limited to SFM Mass Erase mode if the SECURE bit = 1 (Flash read back is not allowed in Secure mode).
FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4]) = 0010.
The I/O RAM registers SFMM (I/O RAM 0x2080) and SFMS (I/O RAM 0x2081) are used to invoke SFM. Only
the SPI interface has access to these two registers. This eliminates an indirect path from the MPU for
disabling the watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This
sequential write process prevents inadvertent entering of SFM.
The sequence for invoking SFM is:
•
First, write to the SFMM (I/O RAM 0x2080) register. The value written to this register defines the SFM
mode.
o 0xD1: Mass Erase mode. A Flash Mass erase cycle is invoked upon entering SFM.
o 0x2E: Flash Read back mode. SFM is entered for Flash read back purposes. Flash writes
are not be blocked and it is up to the user to guarantee that only previously unwritten
locations are written. This mode is not accessible when SPI secure mode is set.
o SFM is not invoked if any other pattern is written to the SFMM register.
•
Next, write 0x96 to the SFMS (I/O RAM 0x2081) register. This action invokes SFM provided that the
previous write operation to SFMM met the requirements. Writing any other pattern to this register does
not invoke SFM. Additionally, any write operations to this register automatically reset the previously
written SFMM register values to zero.
Rev 2
77
71M6541D/F/G and 71M6542F/G Data Sheet
SFM details
The following occurs upon entering SFM.
•
•
•
•
•
The CE is disabled.
The MPU is halted. Once the MPU is halted it can only be restarted with a reset. This reset can be
accomplished with the RESET pin, a watchdog reset, or by cycling power (without battery at the
VBAT pin).
The Flash control logic is reset in case the MPU was in the middle of a Flash write operation or Erase
cycle.
Mass erase is invoked if specified in the SFMM register, I/O RAM 0x2080 (see Invoking SFM, above).
The SECURE bit (SFR 0xB2[6]) is cleared at the end of this and all Mass Erase cycles.
All SPI read and write operations now refer to Flash instead of XRAM space.
The SPI host can access the current state of the pending multi-cycle Flash access by performing a 4-byte
SPI write of any address and checking the status field.
All SPI write operations in SFM mode must be 6-byte write transaction that writes two bytes to an even
address. The write transactions must contain a command byte of the form 0xxx xxxx. Auto incrementing
is disabled for write operations.
SPI read transactions can make use of auto increment and may access single bytes. The command byte
must always be of the form 1xxx xxxx in SFM read transactions.
SPI commands in SFM
Interrupts are not generated in SFM since the MPU is halted. The format of the commands is described in
the SPI Transactions description on Page 73.
2.5.11 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6541D/F/G and
71M6542F/G. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU
firmware at least every 1.5 seconds. When not refreshed on time, the WDT overflows and the part is
reset as if the RESET pin were pulled high, except that the I/O RAM bits are in the same state as after a
wake-up from SLP or LCD modes (see the I/O RAM description in 5.2 I/O RAM Map – Alphabetical Order
for a list of I/O RAM bit states after RESET and wake-up). After 4100 CK32 cycles (or 125 ms) following
the WDT overflow, the MPU is launched from program address 0x0000.
The watchdog timer is also reset when the internal signal WAKE=0 (see 3.4 Wake Up Behavior).
For details, see 3.3.4 Watchdog Timer Reset.
2.5.12 Test Ports (TMUXOUT and TMUX2OUT Pins)
Two independent multiplexers allow the selection of internal analog and digital signals for the TMUXOUT
and TMUX2OUT pins. These pins are multiplexed with the SEG47 and SEG46 function. In order to function
as test pins, LCD_MAP[46] (I/O RAM 0x2406[6]) and LCD_MAP[47] (I/O RAM 0x2406[7]) must be 0.
One of the digital or analog signals listed in
Table 65 can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled
with the I/O RAM register TMUX[5:0] (I/O RAM 0x2502[5:0], as shown in
Table 65.
One of the digital or analog signals listed in Table 66 can be selected to be output on the TMUX2OUT pin.
The function of the multiplexer is controlled with the I/O RAM register TMUX2[4:0] (I/O RAM 0x2503[4:0]), as
shown in Table 66.
The TMUX[5:0] and TMUX2[4:0] I/O RAM locations are non-volatile and their contents are preserved
by battery power and across resets.
78
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
The TMUXOUT and TMUX2OUT pins may be used for diagnostics purposes during the product
development cycle or in the production test. The RTC 1-second output may be used to calibrate the
crystal oscillator. The RTC 4-second output provides higher precision for RTC calibration. RTCLK may
also be used to calibrate the RTC.
Table 65: TMUX[5:0] Selections
Signal Name
Description
1
RTCLK
9
WD_RST
A
CKMPU
D
V3AOK bit
E
V3OK bit
1B
MUX_SYNC
32.768 kHz clock waveform
Indicates when the MPU has reset the watchdog timer. Can be
monitored to determine spare time in the watchdog timer.
MPU clock – see Table 9
Indicates that the V3P3A pin voltage is ≥ 3.0 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M654x monitors the V3P3A pin voltage only.
Indicates that the V3P3A pin voltage is ≥ 2.8 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M654x monitors the V3P3A pin voltage only.
Internal multiplexer frame SYNC signal. See Figure 6 and Figure
7.
1C
1D
1F
CE_BUSY interrupt
CE_XFER interrupt
RTM output from CE
TMUX[5:0]
See 2.3.3 on page 25 and Figure 16 on page 47
See 2.3.5 on page 25
Note:
All TMUX[5:0] values which are not shown are reserved.
Table 66: TMUX2[4:0] Selections
Signal Name
Description
0
WD_OVF
1
PULSE_1S
2
PULSE_4S
3
RTCLK
SPARE[1] bit – I/O RAM
0x2704[1]
SPARE[2] bit – I/O RAM
0x2704[2]
Indicates when the watchdog timer has expired (overflowed).
One second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC from an ideal 1 second
interval. Multiple cycles should be averaged together to filter out
jitter.
Four second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC from an ideal 4 second
interval. Multiple cycles should be averaged together to filter out
jitter. The 4 second pulse provides a more precise measurement
than the 1 second pulse.
32.768 kHz clock waveform
Copies the value of the bit stored in 0x2704[1]. For general
purpose use.
Copies the value of the bit stored in 0x2704[2]. For general
purpose use.
Indicates when a WAKE event has occurred.
Internal multiplexer frame SYNC signal. See Figure 6 and Figure
7.
See 2.5.3 on page 50
Digital GND. Use this signal to make the TMUX2OUT pin static.
TMUX2[4:0]
8
9
A
WAKE
B
MUX_SYNC
C
E
12
13
14
15
16
17
18
1F
MCK
GNDD
INT0 – DIG I/O
INT1 – DIG I/O
INT2 – CE_PULSE
INT3 – CE_BUSY
INT4 - VSTAT
INT5 – EEPROM/SPI
INT6 – XFER, RTC
RTM_CK (flash)
Interrupt 0. See 2.4.8 on page 40. Also see Figure 16 on page 47.
See 2.3.5 on page 25.
Note:
All TMUX2[4:0] values which are not shown are reserved.
Rev 2
79
71M6541D/F/G and 71M6542F/G Data Sheet
3
Functional Description
3.1
Theory of Operation
The energy delivered by a power source into a load can be expressed as:
t
E = ∫ V (t ) I (t )dt
0
Assuming phase angles are constant, the following formulae apply:


P = Real Energy [Wh] = V * A * cos φ* t

S = Apparent Energy [VAh] =
Q = Reactive Energy [VARh] = V * A * sin φ * t
P2 + Q2
For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content
may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state
electricity meter IC such as the Teridian 71M654x functions by emulating the integral operation above,
i.e., it processes current and voltage samples through an ADC at a constant frequency. As long as the
ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest, the
current and voltage samples, multiplied with the time period of sampling yield an accurate quantity for the
momentary energy. Summing up the momentary energy quantities over time results in very accurate
results for accumulated energy.
500
400
300
200
100
0
0
5
10
15
20
-100
-200
Current [A]
-300
Voltage [V]
Energy per Interval [Ws]
-400
Accumulated Energy [Ws]
-500
Figure 28: Voltage, Current, Momentary and Accumulated Energy
Figure 28 shows the shapes of V(t), I(t), the momentary power and the accumulated power, resulting from
50 samples of the voltage and current signals over a period of 20 ms. The application of 240 VAC and
100 A results in an accumulation of 480 Ws (= 0.133 Wh) over the 20 ms period, as indicated by the
accumulated power curve. The described sampling method works reliably, even in the presence of dynamic
phase shift and harmonic distortion.
80
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
3.2
Battery Modes
Shortly after system power (V3P3SYS) is applied, the part is in mission mode (MSN mode). MSN mode
means that the part is operating with system power and that the internal PLL is stable. This mode is the
normal operating mode where the part is capable of measuring energy.
When system power is not available, the 71M654x is in one of three battery modes:
•
•
•
BRN mode (brownout mode)
LCD mode (LCD-only mode)
SLP mode (sleep mode).
An internal comparator monitors the voltage at the V3P3SYS pin (note that V3P3SYS and V3P3A are
typically connected together at the PCB level). When the V3P3SYS dc voltage drops below 3.0 VDC, the
comparator resets an internal power status bit called V3OK . As soon as system power is removed and
V3OK = 0, the 71M654x switches to battery power (VBAT pin), notifies the MPU by issuing an interrupt and
updates the VSTAT[2:0] register (SFR 0xF9[2:0], see Table 68). The MPU continues to execute code when
the system transitions from MSN to BRN mode. Refer to 3.2.1 BRN Mode for the settings that result in the
lowest possible power during BRN mode. Depending on the MPU code, the MPU can choose to stay in
BRN mode, or transition to LCD or to SLP mode (via the I/O RAM bits LCD_ONLY, I/O RAM 0x28B2[6] and
SLEEP, I/O RAM 0x28B2[7]). BRN mode is similar to MSN mode except that resources powered by V3P3A
power, such as the ADC are inaccurate. In BRN mode the CE continues to run and should be turned off
to conserve VBAT power. Also, the PLL continues to function at the same frequency as in MSN mode
and its frequency should be reduced to save power (CKGN = 0x24 (I/O RAM 0x2200).
When system power is restored, the 71M654x automatically transitions from any of the battery modes
(BRN, LCD, SLP) back to MSN mode, switches back to using system power (V3P3SYS, V3P3A), issues
an interrupt and updates VSTAT[1:0]. The MPU software should restore MSN mode operation by issuing
a soft reset to restore system settings to values appropriate for MSN mode.
Figure 29 shows a state diagram of the various operating modes, with the possible transitions between modes.
When the part wakes-up under battery power, the part automatically enters BRN mode (see 3.4 Wake Up
Behavior). From BRN mode, the part may enter either LCD mode or SLP mode, as controlled by the MPU.
RESET
MSN
V3P3SYS
falls
VSTAT=00X
V3P3SYS
rises
System Power
Battery Power
VSTAT=001
V3P3SYS
rises
LCD_ONLY
BRN
V3P3SYS
rises
RESET &
VBAT
sufficient
Wake Flags
SLEEP or
VBAT
insufficient
Wake
event
LCD
Wake
event
VBAT
insufficient
VBAT
insufficient
RESET &
VBAT
insufficient
SLP
Figure 29: Operation Modes State Diagram
Rev 2
81
71M6541D/F/G and 71M6542F/G Data Sheet
Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events:
• Wake-up timer timeout.
• Pushbutton (PB) is activated.
• A rising edge on SEGDIO4, SEGDIO52 (71M6542F/G only) or SEGDIO55.
• Activity on the RX or OPT_RX pins.
The MPU has access to a variety of registers that signal the event that caused the wake up. See 3.4
Wake Up Behavior for details.
Table 67 shows the circuit functions available in each operating mode.
Table 67: Available Circuit Functions
Circuit Function
CE (Computation Engine)
FIR
ADC, VREF
PLL
Battery Measurement
Temperature sensor
Max MPU clock rate
System Power
MSN (Mission Mode)
PLL_FAST=1 PLL_FAST=0
Yes
Yes
Yes
Yes
Yes
Yes
4.92MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.4kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1.57MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.9kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Battery Power
BRN (Brownout Mode)
LCD
PLL_FAST=1 PLL_FAST=0
Note 1
--Yes
Yes
Yes
4.92MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.4kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note 1
--Yes
Yes
Yes
1.57MHz
(from PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
38.9kHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2
SLEEP
---2
Boost
-Yes
-----Yes
--
--
MPU_DIV clk. divider
--ICE
--DIO Pins
--Watchdog Timer
--LCD
Yes
-LCD Boost
Yes
EEPROM Interface (2-wire)
--EEPROM Interface (3-wire)
--UART (full speed)
--Optical TX modulation
--Flash Read
--Flash Page Erase
--Flash Write
--RAM Read and Write
--Wakeup Timer
Yes
Yes
OSC and RTC
Yes
Yes
DRAM data preservation
--NV RAM data preservation
Yes
Yes
Notes:
1. The CE is active in BRN mode, but ADC data is inaccurate. The MPU should halt the CE to conserve power (CE_E = 0,
I/O RAM 0x2106[0]).
2. “--“ indicates that the corresponding circuit is not active
3. “Boost” implies that the LCD boost circuit is active (i.e., LCD_VMODE[1:0] = 10 (I/O RAM 0x2401[7:6]). The LCD boost
circuit requires a clock from the PLL to function. Thus, the PLL is automatically kept active if LCD boost is active while in
LCD mode, otherwise the PLL is de-activated.
82
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71M6541D/F/G and 71M6542F/G Data Sheet
3.2.1
BRN Mode
In BRN mode, most non-metering digital functions are active (as shown in Table 67) including ICE, UART,
EEPROM, LCD and RTC. In BRN mode, the PLL continues to function at the same frequency as MSN
mode. It is up to the MPU to scale down the PLL (using PLL_FAST, I/O RAM 0x2200[4]) or the MPU
frequency (using MPU_DIV[2:0], I/O RAM 0x2200[2:0]) in order to save power.
From BRN mode, the MPU can choose to enter LCD or SLP modes. When system power is restored
while the 71M654x is in BRN mode, the part automatically transitions to MSN mode.
The recommended minimum power configuration for BRN mode is as follows:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RCE0 = 0x00 (I/O RAM 0x2709[7:0]) - remote sensors disabled
LCD_BAT = 1 (I/O RAM 0x2402[7]) - LCD powered from VBAT
LCD_VMODE[1:0] = 0 (I/O RAM 0x2401[7:6]) - 5V LCD boost disabled
CE6 = 0x00 (I/O RAM 0x2106) - CE, RTM and CHOP are disabled
MUX_DIV[3:0] = 0 (I/O RAM 0x2100[7:4]) - the ADC multiplexer is disabled
ADC_E = 0 (I/O RAM 0x2704[4]) - ADC disabled
VREF_CAL = 0 (I/O RAM 0x2704[7]) – Vref not driven out
VREF_DIS = 1 (I/O RAM 0x2704[6]) - Vref disabled
PRE_E = 0 (I/O RAM 0x2704[5] - pre-amp disabled
BCURR = 0 (I/O RAM 0x2704[3]) - battery 100µA current load OFF
TMUX[5:0] = 0x0E (I/O RAM 0x2502[5:0]) – TMUXOUT output set to a dc value
TMUX2[4:0] = 0x0E (I/O RAM 0x2503[4:0]) – TMUXOUT2 output set to a dc value
CKGN = 0x24 (I/O RAM 0x2200) - PLL set slow, MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) set to maximum
TEMP_PER[2:0] = 6 (I/O RAM 0x28A0[2:0]) - temp measurement set to automatic every 512 s
TEMP_BSEL = 1 (I/O RAM 0x28A0[7]) - temperature sensor monitors VBAT
PCON = 1 (SFR 0x87) - at the end of the main BRN loop, halt the MPU and wait for an interrupt
The baud rate registers are adjusted as desired
All unused interrupts are disabled
3.2.2
LCD Mode
LCD mode may be commanded by the MPU at any time by setting the LCD_ONLY control bit (I/O RAM
0x28B2[6]). However, it is recommended that the LCD_ONLY control bit be set by the MPU only after the
71M654x has entered BRN mode. For example, if the 71M654x is in MSN mode when LCD_ONLY is set,
the duration of LCD mode is very brief and the 71M654x immediately 'wakes'.
In LCD mode, V3P3D is disabled, thus removing all current leakage from the VBAT pin. Before asserting
LCD_ONLY mode, it is recommended that the MPU minimize PLL current by reducing the output
frequency of the PLL to 6.2 MHz (i.e., write PLL_FAST = 0, I/O RAM 0x2200[4]). The LCD boost system
requires a clock from the PLL for its operation. Thus, if the LCD boost system is enabled (i.e.,
LCD_VMODE[1:0] = 10, I/O RAM 0x2401[7:6]), then the PLL is automatically kept active during LCD
mode, otherwise the PLL is de-activated.
In LCD mode, the data contained in the LCD_SEG registers is displayed using the segment driver pins.
Up to two LCD segments connected to the pins SEGDIO22 and SEGDIO23 can be made to blink without
the involvement of the MPU, which is disabled in LCD mode. To minimize battery power consumption,
only segments that are used should be enabled.
After the transition from LCD mode to MSN or BRN mode, the PC (Program Counter) is at 0x0000, the
XRAM is in an undefined state, and configuration I/O RAM bits are reset (see Table 76 for I/O RAM state
upon wake). The data stored in non-volatile I/O RAM locations is preserved in LCD mode (the shaded
locations in Table 76 are non-volatile).
Rev 2
83
71M6541D/F/G and 71M6542F/G Data Sheet
3.2.3
SLP Mode
When the V3P3SYS pin voltage drops below 2.8 VDC, the 71M654x enters BRN mode and the V3P3D
pin obtains power from the VBAT pin instead of the V3P3SYS pin. Once in BRN mode, the MPU may
invoke SLP mode by setting the SLEEP bit (I/O RAM 0x28B2[7]). The purpose of SLP mode is to
consume the least amount power while still maintaining the RTC (Real Time Clock), temperature
compensation of the RTC, and the non-volatile portions of the I/O RAM.
In SLP mode, the V3P3D pin is disconnected, removing all sources of current leakage from the VBAT pin.
The non-volatile I/O RAM locations and the SLP mode functions, such as the temperature sensor,
oscillator, RTC, and the RTC temperature compensation are powered by the VBAT_RTC pin. SLP mode
can be exited only by a system power-up event or one of the wake methods described in 3.4 Wake Up
Behavior.
If the SLEEP bit is asserted when V3P3SYS pin power is present (i.e., while in MSN mode), the 71M654x
enters SLP mode, resetting the internal WAKE signal, at which point the 71M654x begins the standard
wake from sleep procedures as described in 3.4 Wake Up Behavior.
When power is restored to the V3P3SYS pin, the 71M654x transitions from SLP mode to MSN mode and
the MPU PC (Program Counter) is initialized to 0x0000. At this point, the XRAM is in an undefined state,
but non-volatile I/O RAM locations are preserved (the shaded locations in Table 76 are non-volatile).
84
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
3.3
Fault and Reset Behavior
3.3.1
Events at Power-Down
Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and
also monitor the internally generated VDD pin voltage (2.5 VDC). The V3P3SYS and V3P3A pins must be
tied together at the PCB level, so that the comparators, which are internally connected only to the V3P3A
pin, are able to simultaneously monitor the common V3P3SYS and V3P3A pin voltage. The following
discussion assumes that the V3P3A and V3P3SYS pins are tied together at the PCB level.
During a power failure, as V3P3A falls, two thresholds are detected:
•
•
The first threshold, at 3.0 VDC (VSTAT[2:0] = 001), warns the MPU that the analog modules are no
longer accurate. Other than warning the MPU, the hardware takes no action when this threshold is
crossed.
The second threshold, at 2.8 VDC, causes the 71M654x to switch to battery power. This switching
happens while the FLASH and RAM systems are still able to read and write.
The power quality is reflected by the SFR VSTAT[2:0] field, as shown in Table 68. The VSTAT[2:0] field is
located at SFR address 0xF9 and occupies bits [2:0], and it is read-only.
In addition to the state of the main power, the VSTAT[2:0] register provides information about the internal
VDD voltage under battery power. Note that if system power (V3P3A) is above 2.8 VDC, the
71M6541D/F/G and 71M6542F/G always switch from battery to system power.
Table 68: VSTAT[2:0] (SFR 0xF9[2:0])
VSTAT[2:0]
000
001
010
011
101
Description
System Power OK. V3P3A > 3.0 VDC. Analog modules are functional and accurate.
System Power is low. 2.8 VDC < V3P3A < 3.0 VDC. Analog modules not accurate.
Switch over to battery power is imminent.
The IC is on battery power and VDD is OK. VDD > 2.25 VDC. The IC has full digital
functionality.
The IC is on battery power and 2.25 VDC > VDD > 2.0 VDC. Flash write operations are
inhibited.
The IC is on battery power and VDD < 2.0, which means that the MPU is nearly out of
voltage. A reset occurs in 4 cycles of the crystal clock CK32.
The response to a system power fault is almost entirely controlled by firmware. During a power failure,
system power slowly falls. This is monitored by internal comparators that cause the hardware to
automatically switch over to taking power from the VBAT input. An interrupt notifies the MPU that the part
is now battery powered. At this point, it is the MPU’s responsibility to reduce power by slowing the clock
rate, disabling the PLL, etc.
Precision analog components such as the bandgap reference, the bandgap buffer, and the ADC are
powered only by the V3P3A pin and become inaccurate and ultimately unavailable as the V3P3A pin
voltage continues to drop (i.e., circuits powered by the V3P3A pin are not backed by the VBAT pin).
When the V3P3A pin falls below 2.8 VDC, the ADC clocks are halted and the amplifiers are unbiased.
Meanwhile, control bits such as ADC_E bit (I/O RAM 0x2704[4]) are not affected, since their I/O RAM
storage is powered from the VDD pin (2.5 VDC). The VDD pin is supplied with power through an internal
2.5 VDC regulator that is connected to the V3P3D pin. In turn, the V3P3D pin is switched to receive
power from the VBAT pin when the V3P3SYS pin drops below 3.0 VDC. Note that the V3P3SYS and
V3P3A pins are typically tied together at the PCB level.
Rev 2
85
71M6541D/F/G and 71M6542F/G Data Sheet
3.3.2
IC Behavior at Low Battery Voltage
When system power is not present, the 71M6541D/F/G and 71M6542F/G rely on the VBAT pin for power.
If the VBAT voltage is not sufficient to maintain VDD at 2.0 VDC or greater, the MPU cannot operate
reliably. Low VBAT voltage can occur while the part is operating in BRN mode, or while it is dormant in
SLP or LCD mode. Two cases can be distinguished, depending on MPU code:
•
•
Case 1: System power is not present, and the part is waking from SLP or LCD mode. In this case,
the hardware checks the value of VDD to determine if processor operation is possible. If it is not
possible, the part configures itself for BRN operation, and holds the processor in reset (WAKE=0). In
this mode, VBAT powers the 1.0 VDC reference for the LCD system, the VDD regulator, the PLL, and
the fault comparator. The part remains in this waiting mode until VDD becomes high due to system
power being applied or the VBAT battery being replaced or recharged.
Case 2: The part is operating under VBAT power and VSTAT[2:0] (SFR 0xF9[2:0]) becomes 101,
indicating that VDD falls below 2.0 VDC. In this case, the firmware has two choices:
1) One choice is to assert the SLEEP bit (I/O RAM 0x28B2[7]) immediately. This assertion
preserves the remaining charge in VBAT. Of course, if the battery voltage is not increased, the
71M654x enters Case 1 as soon as it tries to wake up.
2) The alternative choice is to enter the waiting mode described in Case 1 immediately. Specifically, if the
firmware does not assert the SLEEP bit, the hardware resets the processor four CE32 clock cycles (i.e.,
122 µs) after VSTAT[2:0] becomes 101 and, as described in Case 1, it begins waiting for VDD to
become greater than 2.0 VDC. The MPU wakes up when system power returns, or when VDD
becomes greater than 2.0 VDC.
In either case, when VDD recovers, and when the MPU wakes up, the WF_BADVDD flag (I/O RAM 0x28B0[2])
can be read to determine that the processor is recovering from a bad VBAT condition. The WF_BADVDD
flag remains set until the next time WAKE falls. This flag is independent of the other WF flags.
In all cases, low VBAT voltage does not corrupt RTC operation, the state of NV memory, or the state of
non-volatile memory. These circuits depend on the VBAT_RTC pin for power.
3.3.3
Reset Sequence
When the RESET pin is pulled high, all digital activity in the chip stops, with the exception of the oscillator
and RTC. Additionally, all I/O RAM bits are forced to their RST state. Reliable reset does not occur until
RESET has been high at least for 2 µs. Note that TMUX and the RTC do not reset unless the TEST pin
is pulled high while RESET is high.
The RESET control bit (I/O RAM 0x 2200[3]) performs an identical reset to the RESET pin except that a
significantly shorter reset timer is used.
Once initiated, the reset sequence waits until the reset timer times out. The time-out occurs in 4100
CE32 cycles (125 ms), at which time the MPU begins executing its pre-boot and boot sequences from
address 0x0000. See 2.5.1.1 Hardware Watchdog Timer for a detailed description of the pre-boot and
boot sequences.
If system power is not present, the reset timer duration is two CE32 cycles, at which time the MPU begins
executing in BRN mode, starting at address 0x0000.
A softer form of reset is initiated when the E_RST pin of the ICE interface is pulled low. This event
causes the MPU and other registers in the MPU core to be reset but does not reset the remainder of the
IC, for example the I/O RAM. It does not trigger the reset sequence. This type of reset is intended to reset
the MPU program, but not to make other changes to the chip’s state.
3.3.4
Watchdog Timer Reset
The watchdog timer (WDT) is described in 2.5.11 Hardware Watchdog Timer.
A status bit, WF_OVF (I/O RAM 0x28B0[4]), is set when a WDT overflow occurs. Similar to the other wake
flags, this bit is powered by the non-volatile supply and can be read by the MPU to determine if the part is
initializing after a WD overflow event or after a power up. The WF_OVF bit is cleared by the RESET pin.
86
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
There is no internal digital state that could deactivate the WDT. For debug purposes, however, the WDT
can be disabled by raising the ICE_E pin to 3.3 VDC.
In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit (I/O RAM
0x28B4[7]). The watchdog timer is also reset when the 71M654x wakes from LCD or SLP mode, and
when ICE_E = 1.
3.4
Wake Up Behavior
As described above, the part always wakes-up in MSN mode when system power is restored. As
described in 3.2 Battery Modes, transitions from both LCD and SLP mode to BRN mode can be initiated
by a wake-up timer timeout, when the pushbutton (PB) input is high, a high level on SEGDIO4,
SEGDIO52 or SEGDIO55, or by activity on the RX or OPT_RX pins.
3.4.1
Wake on Hardware Events
The following pin signal events wake the 71M654x from SLP or LCD mode: a high level on the PB pin, either
edge on the RX pin, a rising edge on the SEGDIO4 pin, a high level on the SEGDIO52 pin (71M6542F/G
only), or a high level on the SEGDIO55 pin or either edge on the OPT_RX pin. See Table 69 for de-bounce
details on each pin and for further details on the OPT_RX/SEGDIO55 pin. The SEGDIO4, SEGDIO52
(71M6542F/G only), and SEGDIO55 pins must be configured as DIO inputs and their wake enable (EW_x
bits) must be set. In SLP and LCD modes, the MPU is held in reset and cannot poll pins or react to
interrupts. When one of the hardware wake events occurs, the internal WAKE signal rises and within
three CK32 cycles the MPU begins to execute. The MPU can determine which one of the pins
awakened it by checking the WF_PB, WF_RX, WF_SEGDIO4, WF_DIO52 (71M6542F/G only), or
WF_DIO55 flags (see Table 69).
If the part is in SLP or LCD mode, it can be awakened by a high level on the PB pin. This pin is normally
pulled to GND and can be connected externally so it may be pulled high by a push button depression.
Some pins are de-bounced to reject EMI noise. Detection hardware ignores all transitions after the initial
transition. Table 69 shows which pins are equipped with de-bounce circuitry.
Pins that do not have de-bounce circuits must still be high for at least 2 µs to be recognized.
The wake enable and flag bits are also shown in Table 69. The wake flag bits are set by hardware when
the MPU wakes from a wake event. Note that the PB flag is set whenever the PB is pushed, even if the
part is already awake.
Table 71 lists the events that clear the WF flags.
In addition to push buttons and timers, the part can also reboot due to the RESET pin, the RESET bit (I/O
RAM 0x2200[3]), the WDT, the cold start detector, and E_RST. As seen in Table 69, each of these
mechanisms has a flag bit to alert the MPU to the source of the wakeup. If the wake-up is caused by
return of system power, there is no active WF flag and the VSTAT[2:0] field (SFR 0xF9[2:0]) indicate that
system power is stable.
Table 69: Wake Enables and Flag Bits
Wake Enable
Wake Flag
De-bounce Description
Name
Location
Name
Location
WAKE_ARM
28B2[5]
WF_TMR
28B1[5]
No
Wake on Timer.
EW_PB
28B3[3]
WF_PB
28B1[3]
Yes
Wake on PB*.
EW_RX
28B3[4]
WF_RX
28B1[4]
2 µs
Wake on either edge of RX.
EW_DIO4
28B3[2]
WF_DIO4
28B1[2]
2 µs
Wake on SEGDIO4.
EW_DIO52†
28B3[1]
WF_DIO52
28B1[1]
Yes
Wake on SEGDIO52*.
EW_DIO55
28B3[0]
WF_DIO55
28B1[0]
Yes
OPT_RXDIS = 1: Wake on DIO55*
with 64 ms de-bounce.
OPT_RXDIS = 0: Wake on either
Rev 2
87
71M6541D/F/G and 71M6542F/G Data Sheet
Wake Enable
Name
Location
Wake Flag
Name
Location
De-bounce Description
Always Enabled
Always Enabled
WF_RST
WF_RSTBIT
28B0[6]
28B0[5]
2 µs
No
Always Enabled
WF_ERST
28B0[3]
2 µs
Always Enabled
WF_OVF
28B0[4]
No
Always Enabled
WF_CSTART
28B0[7]
No
Always Enabled
WF_BADVDD
28B0[2]
No
edge of OPT_RX with 2 µs debounce.
OPT_RXDIS: I/O RAM 0x2457[2]
Wake after RESET.
Wake after RESET bit.
Wake after E_RST.
(ICE must be enabled)
Wake after WD reset.
Wake after cold start - the first
application of power.
Wake after insufficient VBAT
voltage.
† 71M6542F/G only.
*This pin is sampled every 2 ms and must remain high for 64 ms to be declared a valid high level. This
pin is high-level sensitive.
88
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 70: Wake Bits
Name
Location
RST
WK
Dir
EW_DIO4
28B3[2]
0
–
R/W
EW_DIO52
28B3[1]
0
–
R/W
EW_DIO55
28B3[0]
0
–
R/W
WAKE_ARM
28B2[5]
0
–
R/W
EW_PB
28B3[3]
0
–
R/W
EW_RX
28B3[4]
0
–
R/W
WF_DIO4
28B1[2]
0
–
R
WF_DIO52
28B1[1]
0
–
R
WF_DIO55
28B1[0]
0
–
R
WF_TMR
WF_PB
WF_RX
WF_RST
WF_RSTBIT
WF_ERST
WF_CSTART
WF_BADVDD
28B1[5]
28B1[3]
28B1[4]
28B0[6]
28B0[5]
28B0[3]
28B0[7]
28B0[2]
0
0
0
*
*
*
*
*
–
–
–
R
R
R
Rev 2
–
R
Description
Connects SEGDIO4 to the WAKE logic and permits
SEGDIO4 rising to wake the part. This bit has no effect
unless SEGDIO4 is configured as a digital input.
Connects DIO52 to the WAKE logic and permits DIO52
high-level to wake the part (71M6542F/G only). This bit
has no effect unless DIO52 is configured as a digital
input.
Connects DIO55 to the WAKE logic and permits DIO55
high-level to wake the part. This bit has no effect unless
DIO55 is configured as a digital input.
Arms the WAKE timer and loads it with the value in the
WAKE_TMR register (I/O RAM 0x2880). When SLP
mode or LCD mode is asserted by the MPU, the WAKE
timer becomes active.
Connects the PB pin to the WAKE logic and permits PB
high-level to wake the part. PB is always configured as
an input.
Connects the RX pin to the WAKE logic and permits RX
rising to wake the part. See 3.4.1 for de-bounce issues.
SEGDIO4 flag bit. If SEGDIO4 is configured to wake
the part, this bit is set whenever SEGDIO4 rises. It is
held in reset if SEGDIO4 is not configured for wakeup.
SEGDIO52 flag bit. If SEGDIO52 is configured to wake
the part, this bit is set whenever SEGDIO52 is a high
level. It is held in reset if SEGDIO52 is not configured
for wakeup (71M6542F/G only).
SEGDIO55 flag bit. If SEGDIO55 is configured to wake
the part, this bit is set whenever SEGDIO55 is a high
level. It is held in reset if SEGDIO55 is not configured
for wakeup.
Indicates that the Wake timer caused the part to wake up.
Indicates that the PB pin caused the part to wake.
Indicates that RX pin caused the part to wake.
Indicates that the RST pin, E_RST pin, RESET bit (I/O
RAM 0x2200[3]), the cold start detector, or low voltage
on the VBAT pin caused the part to reset.
*See Table 71 for details.
89
71M6541D/F/G and 71M6542F/G Data Sheet
Table 71: Clear Events for WAKE flags
Flag
Wake on:
Clear Events
WF_TMR
Timer expiration
WAKE falls
WF_PB
PB pin high level
WAKE falls
WF_RX
Either edge RX pin
WAKE falls
WF_DIO4
SEGDIO4 rising edge
WAKE falls
WF_DIO52
SEGDIO52 high level (71M6542F/G only)
If OPT_RXDIS = 1 (I/O RAM 0x2457[2]),
wake on SEGDIO55 high
If OPT_RXDIS = 0
wake on either edge of OPT_RX
WAKE falls
WF_DIO55
WF_RST
WF_RSTBIT
WF_ERST
WF_OVF
WF_CSTART
WAKE falls
RESET pin driven high
WAKE falls, WF_CSTART, WF_RSTBIT,
WF_OVF, WF_BADVDD
RESET bit is set (I/O RAM 0x2200[3])
WAKE falls, WF_CSTART, WF_OVF,
WF_BADVDD, WF_RST
E_RST pin driven high and the ICE
interface must be enabled by driving the
ICE_E pin high.
Watchdog (WD) reset
Coldstart (i.e., after the application of first
power)
WAKE falls, WF_CSTART, WF_RST,
WF_OVF, WF_RSTBIT
WAKE falls, WF_CSTART, WF_RSTBIT,
WF_BADVDD, WF_RST
WAKE falls, WF_RSTBIT, WF_OVF,
WF_BADVDD, WF_RST
Note:
“WAKE falls” implies that the internal WAKE signal has been reset, which happens automatically upon
entry into LCD mode or SLEEP mode (i.e., when the MPU sets the LCD_ONLY bit (I/O RAM 0x28B2[6]) or
the SLEEP (I/O RAM 0x28B2[7]) bit). When the internal WAKE signal resets, all wake flags are reset.
Since the various wake flags are automatically reset when WAKE falls, it is not necessary for the MPU to
reset these flags before entering LCD mode or SLEEP mode. Also, other wake events can cause the
wake flag to reset, as indicated above (e.g., the WF_RST flag can also be reset by any of the following
flags setting: WF_CSTART, WS_RSTBIT, WF_OVF, WF_BADVDD)
3.4.2
Wake on Timer
If the part is in SLP or LCD mode, it can be awakened by the Wake Timer. Until this timer times out, the
MPU is in reset due to the internal WAKE signal being low. When the Wake Timer times out, WAKE rises
and within three CK32 cycles, the MPU begins to execute. The MPU can determine that the timer woke it
by checking the WF_TMR wake flag (I/O RAM 0x28B1[2]).
The Wake Timer begins timing when the part enters LCD or SLP mode. Its duration is controlled by the
value in the WAKE_TMR[7:0] register (I/O RAM 0x2880). The timer duration is WAKE_TMR +1 seconds.
The Wake Timer is armed by setting WAKE_ARM = 1 (I/O RAM 0x28B2[5]). It must be armed at least
three RTC cycles before either SLP or LCD modes are initiated. Setting WAKE_ARM presets the timer
with the value in WAKE_TMR and readies the timer to start when the MPU writes to the SLEEP (I/O RAM
0x28B2[7]) or LCD_ONLY (I/O RAM 0x28B2[6]) bits. The timer is neither reset nor disarmed when the
MPU wakes-up. Thus, once armed and set, the MPU continues to be awakened WAKE_TMR[7:0]
seconds after it requests SLP mode or LCD mode (i.e., once written, the WAKE_TMR[7:0] register holds
its value and does not have to be re-written each time the MPU enters SLP or LCD mode. Also, since
WAKE_TMR[7:0] is non-volatile, it also holds its value through resets and power failures).
90
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
3.5
Data Flow and MPU/CE Communication
The data flow between the Compute Engine (CE) and the MPU is shown in Figure 30. In a typical
application, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IA, VA,
2
2
IB, etc., performing calculations to measure active power (Wh), reactive power (VARh), A h, and V h
for four-quadrant metering. These measurements are then accessed by the MPU, processed further and
output using the peripheral devices available to the MPU.
Both the CE and multiplexer are controlled by the MPU via shared registers in the I/O RAM and in RAM.
The CE outputs a total of six discrete signals to the MPU. These consist of four pulses and two interrupts:
•
•
•
•
CE_BUSY
XFER_BUSY
WPULSE, VPULSE (pulses for active and reactive energy)
XPULSE, YPULSE (auxiliary pulses)
These interrupts are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY
indicates that the CE is actively processing data. This signal occurs once every multiplexer cycle (typically
396 µs), and indicates that the CE has updated status information in its CESTATUS register (CE RAM 0x80).
XFER_BUSY indicates that the CE is updating data to the output region of the RAM. This indication
occurs whenever the CE has finished generating a sum by completing an accumulation interval
determined by SUM_SAMPS[12:0], I/O RAM 0x2107[4:0], 2108[7:0], (typically every 1000 ms). Interrupts to
the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
WPULSE and VPULSE are typically used to signal energy accumulation of real (Wh) and reactive (VARh)
energy. Tying WPULSE and VPULSE into the MPU interrupt system can support pulse counting.
XPULSE and YPULSE can be used to signal events such as sags and zero crossings of the mains voltage
to the MPU. Tying these outputs into the MPU interrupt system relieves the MPU from having to read the
CESTATUS register at every occurrence of the CE_BUSY interrupt in order to detect sag or zero crossing
events.
Pulses
XPULSE
YPULSE
Interrupts
VPULSE
WPULSE
CE_BUSY
XFER_BUSY
CE
Samples
Processed
Metering
Data
CESTATUS
CECONFIG
MUX
Control
MPU
Control
Control
XRAM
I/O RAM (Configuration RAM)
Figure 30: MPU/CE Data Flow
Refer to 5.3 CE Interface Description for additional information on setting up the device using the MPU
firmware.
Rev 2
91
71M6541D/F/G and 71M6542F/G Data Sheet
4
Application Information
4.1
Connecting 5 V Devices
All digital input pins of the 71M654x are compatible with external 5 V devices. I/O pins configured as
inputs do not require current-limiting resistors when they are connected to external 5 V devices.
4.2
Direct Connection of Sensors
Figure 31 through Figure 34 show voltage-sensing resistive dividers, current-sensing current transformers
(CTs) and current-sensing resistive shunts and how they are connected to the voltage and current inputs
of the 71M654x. All input signals to the 71M654x sensor inputs are voltage signals providing a scaled
representation of either a sensed voltage or current.
The analog input pins of the 71M654x are designed for sensors with low source impedance.
RC filters with resistance values higher than those implemented in the Teridian Demo Boards
must not be used. Please refer to the Demo Board schematics for complete sensor input
circuits and corresponding component values.
RIN
VA
VIN
ROUT
V3P3A
Figure 31: Resistive Voltage Divider (Voltage Sensing)
IIN
IOUT
IAP
CT
RBURDEN
VOUT
V3P3A
Noise Filter
1:N
Figure 32. CT with Single-Ended Input Connection (Current Sensing)
IIN
IOUT
IAP
V3P3A
CT
RBURDEN
VOUT
IAN
Bias Network and Noise Filter
1:N
Figure 33: CT with Differential Input Connection (Current Sensing)
IIN
IAP
V3P3A
RSHUNT
VOUT
IAN
Bias Network and Noise Filter
Figure 34: Differential Resistive Shunt Connections (Current Sensing)
92
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
4.3
71M6541D/F/G Using Local Sensors
Figure 35 shows a 71M6541D/F/G configuration using locally connected current sensors. The IAP-IAN
current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is
connected to a CT and is therefore isolated. This configuration implements a single-phase measurement
with tamper-detection using one current sensor to measure the neutral current. This configuration can
also be used to create a split phase meter (e.g., ANSI Form 2S). For best performance, both the IAP-IAN
and IBP-IBN current sensor inputs are configured for differential mode (i.e., DIFFA_E = 1 and DIFFB_E =
1, I/O RAM 0x210C[4] and 0x210C[5]). The IBP-IBN input must be configured as an analog differential
input disabling the remote sensor interface (i.e., RMT_E = 0, I/O RAM 0x2709[3]). See Figure 2 for the AFE
configuration corresponding to Figure 35.
NEUTRAL
CT
CT or
LOAD
Shunt
LINE
NEUTRAL
Note:
This system is referenced to LINE
POWER SUPPLY
Resistor Divider
LINE
MUX and ADC
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
LINE
IAP
IAN
TERIDIAN
WAKE-UP
71M6541D/F
REGULATOR
BATTERY
VBAT
VA
VBAT_RTC
IBP
IBN
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
AMR
IR
TX
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
RAM
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
11/5/2010
Figure 35. 71M6541D/F/G with Local Sensors
Rev 2
93
71M6541D/F/G and 71M6542F/G Data Sheet
4.4
71M6541D/F/G Using 71M6x01and Current Shunts
Figure 36 shows a typical connection for one isolated and one non-isolated shunt sensor, using the
71M6x01 Isolated Sensor Interface. This configuration implements a single-phase measurement with
tamper-detection using the second current sensor. This configuration can also be used to create a split
phase meter (e.g., ANSI Form 2S). For best performance, the IAP-IAN current sensor input is configured
for differential mode (i.e., DIFFA_E = 1, I/O RAM 0x210C[4]). The outputs of the 71M6x01 Isolated Sensor
Interface are routed through a pulse transformer, which is connected to the pins IBP-IBN. The IBP-IBN
pins must be configured for remote sensor communication (i.e., RMT_E =1, I/O RAM 0x2709[3]). See
Figure 3 for the AFE configuration corresponding to Figure 36.
NEUTRAL
Shunt
LOAD
Note:
This system is referenced to LINE
Shunt
LINE
NEUTRAL
POWER SUPPLY
LINE
Resistor Divider
LINE
TERIDIAN
71M6xx1
MUX and ADC
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
IAP
IAN
Pulse
Transformer
TERIDIAN
WAKE-UP
71M6541D/F
REGULATOR
BATTERY
VBAT
VA
VBAT_RTC
IBP
IBN
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
AMR
IR
TX
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
RAM
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
11/5/2010
Figure 36: 71M6541D/F/G with 71M6x01 isolated Sensor
94
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
4.5
71M6542F/G Using Local Sensors
Figure 38 shows a 71M6542F/G configuration using locally connected current sensors. The IAP-IAN
current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is
connected to a CT and is therefore isolated. This configuration implements a dual-phase measurement
utilizing Equation 2. For best performance, both the IAP-IAN and IBP-IBN current sensor inputs are
configured for differential mode (i.e., DIFFA_E = 1 and DIFFB_E = 1, I/O RAM 0x210C[4] and 0x210C[5]).
The IBP-IBN input must be configured as an analog differential input disabling the remote sensor
interface (i.e., RMT_E = 0, I/O RAM 0x2709[3]). See Figure 4 for the AFE configuration corresponding to
Figure 38.
CT or
Shunt
PHASE A
LOAD
NEUTRAL
Shunt
Note:
This system is referenced to PHASE A
LOAD
PHASE B
NEUTRAL
POWER SUPPLY
Resistor Dividers
PHASE A
MUX and ADC
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
IAP
IAN
PHASE A
TERIDIAN
71M6542F
WAKE-UP
REGULATOR
VB
VA
VBAT
VBAT_RTC
IBP
IBN
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
AMR
IR
TX
RAM
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
BATTERY
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
11/5/2010
Figure 37: 71M6542F/G with Local Sensors
Rev 2
95
71M6541D/F/G and 71M6542F/G Data Sheet
4.6
71M6542F/G Using 71M6x01 and Current Shunts
Figure 38 shows a typical two-phase connection for the 71M6542F/G using one isolated and one nonisolated sensor. For best performance, the IAP-IAN current sensor input is configured for differential mode
(i.e., DIFFA_E = 1, I/O RAM 0x210C[4]). The 71M6x01 Isolated Sensor Interface is used to isolate phase B.
The outputs of the 71M6x01 Isolated Sensor Interface are routed through a pulse transformer, which is
connected to the pins IBP-IBN. The IBP-IBN pins must be configured for remote sensor communication
(i.e., RMT_E =1, I/O RAM 0x2709[3]). See Figure 5 for the AFE configuration corresponding to Figure 38.
Shunt
PHASE A
LOAD
NEUTRAL
Shunt
Note:
This system is referenced to PHASE A
LOAD
PHASE B
NEUTRAL
POWER SUPPLY
PHASE A
Resistor Dividers
PHASE A
TERIDIAN
71M6XX1
MUX and ADC
Pulse
Transformer
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
IAP
IAN
TERIDIAN
71M6542F
VB
VA
VBAT_RTC
TEMPERATURE
SENSOR
VREF
SERIAL PORTS
IR
TX
RAM
COMPUTE
ENGINE
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
HOST
REGULATOR
BATTERY
VBAT
IBP
IBN
AMR
WAKE-UP
FLASH
MEMORY
MPU
RTC
TIMERS
BATTERY
MONITOR
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL
XIN
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
SPI INTERFACE
ICE
XOUT
Figure 38: 71M6542F/G with 71M6x01 Isolated Sensor
96
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
4.7
Metrology Temperature Compensation
4.7.1
Voltage Reference Precision
Since the VREF band-gap amplifier is chopper-stabilized, as set by the CHOP_E[1:0] (I/O RAM 0x2106[3:2])
control field, the dc offset voltage, which is the most significant long-term drift mechanism in the voltage
references (VREF), is automatically removed by the chopper circuit. Both the 71M654x and the 71M6x01
feature chopper circuits for their respective VREF voltage reference.
Teridian implements a trimming procedure of the VREF voltage reference during the device
manufacturing process.
The reference voltage (VREF) is trimmed to a target value of 1.195V. During this trimming process, the
TRIMT[7:0] (I/O RAM 0x2309) value is stored in non-volatile fuses. TRIMT[7:0] is trimmed to a value that
results in minimum VREF variation with temperature.
For the 71M654x device (±0.5% energy accuracy), the TRIMT[7:0] value can be read by the MPU
during initialization in order to calculate parabolic temperature compensation coefficients suitable for
each individual 71M654x device. The resulting temperature coefficient for VREF in the 71M654x is ±40
ppm/°C.
Considering the factory calibration temperature of VREF to be +22°C and the industrial temperature
range (-40°C to +85°C), the VREF error at the temperature extremes for the 71M654x device can be
calculated as:
(85o C − 22 o C ) ⋅ 40 ppm / oC = +2520 ppm = +0.252%
and
(−40 o C − 22 o C ) ⋅ 40 ppm / oC = −2480 ppm = −0.248%
The above calculation implies that both the voltage and the current measurements are individually
subject to a theoretical maximum error of approximately ±0.25%. When the voltage sample and current
sample are multiplied together to obtain the energy per sample, the voltage error and current error
combine resulting in approximately ±0.5% maximum energy measurement error. However, this
theoretical ±0.5% error considers only the voltage reference (VREF) as an error source. In practice,
other error sources exist in the system. The principal remaining error sources are the current sensors
(shunts or CTs) and their corresponding signal conditioning circuits, and the resistor voltage divider
used to measure the voltage. The 71M654x 0.5% grade devices should be used in Class 1% designs,
allowing sufficient margin for the other error sources in the system.
4.7.2
Temperature Coefficients for the 71M654x
The equations provided below for calculating TC1 and TC2 apply to the 71M654x (0.5% energy accuracy). In
order to obtain TC1 and TC2, the MPU reads TRIMT[7:0] (I/O RAM 0x2309) and uses the TC1 and TC2
equations provided. PPMC and PPMC2 are then calculated from TC1 and TC2, as shown. The resulting
tracking of the reference voltage (VREF) is within ±40 ppm/°C, corresponding to a ±0.5% energy
measurement accuracy. See 4.7.1 Voltage Reference Precision.
TC1 = 275 − 4.95 ⋅ TRIMT [7 : 0]
TC 2 = −0.557 + 2.8 ⋅ 10 −4 ⋅ TRIMT [7 : 0]
PPMC =
PPMC 2 =
2 21
57 ⋅ 1.195
2 29
5 8 ⋅1.195
⋅ TC1 = 22.4632 ⋅ TC1
⋅ TC 2 = 1150.116 ⋅ TC 2
The coefficients multiplying TC1 and TC2 to obtain PPMC and PPMC2 are derived from the 1.195V ADC
voltage reference and scaling performed in the CE, as shown above.
Rev 2
97
71M6541D/F/G and 71M6542F/G Data Sheet
See 4.7.3 and 4.7.4 below for further temperature compensation details.
4.7.3
Temperature Compensation for VREF with Local Sensors
This section discusses metrology temperature compensation for the meter designs where local sensors
are used, as shown in Figure 35 and Figure 37.
In these configurations where all sensors are directly connected to the 71M654x, each sensor channel’s
accuracy is affected by the voltage variation in the 71M654x VREF due to temperature. The VREF in the
71M654x can be compensated digitally using a second-order polynomial function of temperature. The
71M654x features an on-chip temperature sensor for the purpose of temperature compensating its VREF.
There are also error sources external to the 71M654x. The voltage sensor resistor dividers and the shunt
current sensor and/or CT and their corresponding signal conditioning circuits also have a temperature
dependency, which also may require compensation, depending on the required accuracy class. The
compensation for these external error sources may be optionally lumped with the compensation for VREF by
incorporating their compensation into the PPMC and PPMC2 coefficients for each corresponding channel.
The MPU has the responsibility of computing the necessary compensation values required for each sensor
channel based on the sensed temperature. Teridian provides demonstration code that implements the
GAIN_ADJn compensation equation shown below. The resulting GAIN_ADJn values are stored by the
MPU in three CE RAM locations GAIN_ADJ0-GAIN_ADJ2 (CE RAM 0x40-0x42). The demonstration code
thus provides a suitable implementation of temperature compensation, but other methods are possible in
MPU firmware by utilizing the on-chip temperature sensors and the CE RAM GAIN_ADJn storage locations.
The demonstration code maintains three separate sets of PPMC and PPMC2 coefficients and computes
three separate GAIN_ADJn values based on the sensed temperature using the equation below:
GAIN _ ADJ = 16385 +
10 ⋅ TEMP _ X ⋅ PPMC
214
+
100 ⋅ TEMP _ X 2 ⋅ PPMC 2
2 23
Where, TEMP_X is the deviation from nominal or calibration temperature expressed in multiples of
0.1 °C. For example, since the 71M654x calibration (reference) temperature is 22 oC and the measured
temperature is 27 oC, then TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 oC deviation
from 22 oC.
Table 73 shows the three GAIN_ADJn equation output values and the voltage or current measurements
for which they compensate.
•
•
•
GAIN_ADJ0 compensates for the VA and VB (71M6542F/G only) voltage measurements in the
71M654x and is used to compensate the VREF in the 71M654x. The designer may optionally add
compensation for the resistive voltage dividers into the PPMC and PPMC2 coefficients for this
channel.
GAIN_ADJ1 provides compensation for the IA current channel and compensates for the 71M654x
VREF. The designer may optionally add compensation for the shunt or CT and its corresponding
signal conditioning circuit into the PPMC and PPMC2 coefficients for this channel.
GAIN_ADJ2 provides compensation for the IB current channel and compensates for the 71M654x VREF.
The designer may optionally add compensation for the CT and its signal conditioning circuit into the
PPMC and PPMC2 coefficients for this channel.
Table 72: GAIN_ADJn Compensation Channels
Gain Adjustment Output
GAIN_ADJ0
GAIN_ADJ1
GAIN_ADJ2
CE RAM Address
0x40
0x41
0x42
71M6541D/F/G
VA
IA
IB
71M6542F/G
VA, VB
IA
IB
In the demonstration code, temperature compensation behavior is determined by the values stored in the
PPMC and PPMC2 coefficients for each of the three channels, which are setup by the MPU demo code at
initialization time from values that are previously stored in EEPROM.
98
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero
for each of the three GAIN_ADJn channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set with values that match the expected temperature variation of each corresponding
sensor channel.
For VREF compensation, both the linear coefficient PPMC and the quadratic coefficient PPMC2, are
determined as described in 4.7.2 Temperature Coefficients for the 71M654x.
The compensation for the external error sources is accomplished by summing the PPMC value
associated with VREF with the PPMC value associated with the external error source to obtain the final
PPMC value for the sensor channel. Similarly, the PPMC2 value associated with VREF is summed with
the PPMC2 value associated with the external error source.
To determine the contribution of the current shunt sensor or CT to the PPMC and PPMC2 coefficients,
the designer must either know the temperature coefficients of the shunt or the CT from its data sheet or
obtain them by laboratory measurement. The designer must consider component variation across mass
production to ensure that the product will meet its accuracy requirement across production.
4.7.4
Temperature Compensation for VREF with Remote Sensor
This section discusses metrology temperature compensation for the meter designs where current shunt
sensors are used in conjunction with the Teridian 71M6x01 isolated sensors, as shown in Figure 36 and
Figure 38.
Any sensors that are directly connected to the 71M654x are affected by the voltage variation in the
71M654x VREF due to temperature. On the other hand, sensors that are connected to the 71M6x01
isolated sensor, are affected by the VREF in the 71M6x01. The VREF in both the 71M654x and
71M6x01 can be compensated digitally using a second-order polynomial function of temperature. The
71M654x and 71M6x01 feature temperature sensors for the purposes of temperature compensating their
corresponding VREF.
Referring to Figure 36 and Figure 38, the VA voltage sensor is available in both the 71M6541D/F/G and
71M6542F/G and is directly connected to the 71M654x. The VB voltage sensor is available only in the
71M6542F/G and is also directly connected to it. Thus, the precision of these directly connected voltage
sensors is affected by VREF in the 71M654x. The 71M654x also has one shunt current sensor (IA) which is
connected directly to it, and therefore is also affected by the VREF in the 71M654x. The external current
sensor and its corresponding signal conditioning circuit also has a temperature dependency, which
also may require compensation, depending on the required accuracy class. Finally, the second current
sensor (IB) is isolated by the 71M6x01 and depends on the VREF of the 71M6x01, plus the variation of the
corresponding shunt resistance with temperature.
The MPU has the responsibility of computing the necessary compensation values required for each sensor
channel based on the sensed temperature. Teridian provides demonstration code that implements the
GAIN_ADJn compensation equation shown below. The resulting GAIN_ADJn values are stored by the
MPU in three CE RAM locations GAIN_ADJ0-GAIN_ADJ2 (CE RAM 0x40-0x42). The demonstration code
thus provides a suitable implementation of temperature compensation, but other methods are possible in
MPU firmware by utilizing the on-chip temperature sensors and the CE RAM GAIN_ADJn storage locations.
The demonstration code maintains three separate sets of PPMC and PPMC2 coefficients and computes
three separate GAIN_ADJn values based on the sensed temperature using the equation below:
GAIN _ ADJ = 16385 +
10 ⋅ TEMP _ X ⋅ PPMC
214
+
100 ⋅ TEMP _ X 2 ⋅ PPMC 2
2 23
Where, TEMP_X is the deviation from nominal or calibration temperature expressed in multiples of
o
0.1 °C. For example, since the 71M654x calibration (reference) temperature is 22 C and the measured
o
temperature is 27 C, then TEMP_X = (27-22) x 10 = 50 (decimal), which represents a +5 oC deviation
from 22 oC.
Table 73 shows the three GAIN_ADJn equation output values and the voltage or current measurements
for which they compensate.
•
GAIN_ADJ0 compensates for the VA and VB (71M6542F/G only) voltage measurements in the
71M654x and is used to compensate the VREF in the 71M654x. The designer may optionally add
Rev 2
99
71M6541D/F/G and 71M6542F/G Data Sheet
•
•
compensation for the resistive voltage dividers into the PPMC and PPMC2 coefficients for this
channel.
GAIN_ADJ1 provides compensation for the IA current channel and compensates for the 71M654x
VREF. The designer may optionally add compensation for the shunt and its corresponding signal
conditioning circuit into the PPMC and PPMC2 coefficients for this channel.
GAIN_ADJ2 provides compensation for the remotely connected IB shunt current sensor and compensates
for the 71M6x01 VREF. The designer may optionally add compensation for the shunt connected to the
71M6x01 into the PPMC and PPMC2 coefficients for this channel.
Table 73: GAIN_ADJn Compensation Channels
Gain Adjustment Output
GAIN_ADJ0
GAIN_ADJ1
GAIN_ADJ2
CE RAM Address
71M6541D/F/G
71M6542F/G
0x40
0x41
0x42
VA
IA
IB
VA, VB
IA
IB
In the demonstration code, temperature compensation behavior is determined by the values stored in the
PPMC and PPMC2 coefficients, which are setup by the MPU demo code at initialization time from values
that are previously stored in EEPROM.
To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero
for each of the three GAIN_ADJn channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set with values that match the expected temperature variation of the corresponding
channel.
For VREF compensation, both the linear coefficient PPMC and the quadratic coefficient PPMC2, are
determined for the 71M654x as described in 4.7.2 Temperature Coefficients for the 71M654x. For
information on determining the PPMC and PPMC2 coefficients for the 71M6x01 VREF, refer to the
71M6xxx Data Sheet.
The compensation for the external error sources is accomplished by summing the PPMC value
associated with VREF with the PPMC value associated with the external error source to obtain the final
PPMC value for the sensor channel. Similarly, the PPMC2 value associated with VREF is summed with
the PPMC2 value associated with the external error source.
To determine the contribution of the current shunt sensor to the PPMC and PPMC2 coefficients, the
designer must either know the temperature coefficients of the shunt from its data sheet or obtain it by
laboratory measurement. The designer must consider component variation across mass production to
ensure that the product will meet its accuracy requirement across production.
4.8
Connecting I2C EEPROMs
I2C EEPROMs or other I2C compatible devices should be connected to the DIO pins SEGDIO2 and
SEGDIO3, as shown in Figure 39.
Pull-up resistors of roughly 10 kΩ to V3P3D (to ensure operation in BRN mode) should be used for both
SDCK and SDATA signals. The DIO_EEX[1:0] (I/O RAM 0x2456[7:6]) field in I/O RAM must be set to 01
2
in order to convert the DIO pins SEGDIO2 and SEGDIO3 to I C pins SDCK and SDATA.
100
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
10 kΩ
V3P3D
10 kΩ
EEPROM
SEGDIO2/SDCK
SDCK
SEGDIO3/SDATA
SDATA
71M654x
Figure 39: I2C EEPROM Connection
4.9
Connecting Three-Wire EEPROMs
µWire EEPROMs and other compatible devices should be connected to the DIO pins SEGDIO2/SDCK
and SEGDIO3/SDATA, as described in 2.5.9 EEPROM Interface.
4.10
UART0 (TX/RX)
The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF
ceramic capacitor, as shown in Figure 40.
71M654x
RX
TX
100 pF 10 k Ω
RX
TX
Figure 40: Connections for UART0
4.11
Optical Interface (UART1)
The OPT_TX and OPT_RX pins can be used for a regular serial interface (by connecting a RS_232
transceiver for example), or they can be used to directly operate optical components (for example, an infrared
diode and phototransistor implementing a FLAG interface). Figure 41 shows the basic connections for
UART1. The OPT_TX pin becomes active when the I/O RAM control field OPT_TXE (I/O RAM 0x2456[3:2])
is set to 00.
The polarity of the OPT_TX and OPT_RX pins can be inverted with the configuration bits, OPT_TXINV
(I/O RAM 0x2456[0]) and OPT_RXINV (I/O RAM 0x2457[1]), respectively.
The OPT_TX output may be modulated at 38 kHz when system power is present. Modulation is not
available in BRN mode. The OPT_TXMOD bit (I/O RAM 0x2456[1]) enables modulation. The duty cycle is
controlled by OPT_FDC[1:0] (I/O RAM 0x2457[5:4]), which can select 50%, 25%, 12.5%, and 6.25% duty
cycle. A 6.25% duty cycle means OPT_TX is low for 6.25% of the period. The OPT_RX pin uses digital
signal thresholds. It may need an analog filter when receiving modulated optical signals.
With modulation, an optical emitter can be operated at higher current than nominal, enabling it to
increase the distance along the optical path.
Rev 2
101
71M6541D/F/G and 71M6542F/G Data Sheet
If operation in BRN mode is desired, the external components should be connected to V3P3D. However,
it is recommended to limit the current to a few mA.
V3P3SYS
R1
71M654x
OPT_RX
100 pF
10 kΩ
Phototransistor
V3P3SYS
R2
LED
OPT_TX
Figure 41: Connection for Optical Components
4.12
Connecting the Reset Pin
Even though a functional meter does not necessarily need a reset switch, it is useful to have a reset
pushbutton for prototyping as shown in Figure 42, left side. The RESET signal may be sourced from
V3P3SYS (functional in MSN mode only), V3P3D (MSN and BRN modes), or VBAT (all modes, if a
battery is present), or from a combination of these sources, depending on the application.
For a production meter, the RESET pin should be protected by the external components shown in
Figure 42, right side. R1 should be in the range of 100Ω and mounted as closely as possible to the IC.
Since the 71M6541D/F/G and 71M6542F/G generate their own power-on reset, a reset button or circuitry, as
shown in Figure 42, is only required for test units and prototypes.
VBAT/
V3P3D
V3P3D
R2
71M654x
71M654x
1k Ω
Reset
Switch
RESET
0.1µF
10kΩ
R1
GNDD
GNDD
Figure 42: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right)
4.13
Connecting the Emulator Port Pins
Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for
protection from EMI as illustrated in Figure 43. Production boards should have the ICE_E pin connected
to ground.
102
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
LCD Segments
(optional)
V3P3D
71M654x
ICE_E
62 Ω
E_RST
62 Ω
E_RXT
E_TCLK
62 Ω
22 pF 22 pF 22 pF
Figure 43: External Components for the Emulator Interface
Rev 2
103
71M6541D/F/G and 71M6542F/G Data Sheet
4.14
Flash Programming
4.14.1 Flash Programming via the ICE Port
Operational or test code can be programmed into the flash memory using either an in-circuit emulator or
the Flash Programmer Module (TFP-2) available from Teridian. The flash programming procedure uses
the E_RST, E_RXTX, and E_TCLK pins.
4.14.2 Flash Programming via the SPI Port
It is possible to erase, read and program the flash memory of the via the SPI port. See 2.5.10 SPI Slave
Port for a detailed description.
4.15
MPU Firmware Library
All application-specific MPU functions mentioned in 4 Application Information are featured in the
demonstration C source code supplied by Teridian. The code is available as part of the Demonstration Kit
for the 71M6541D/F/G and 71M6542F/G. The Demonstration Kits come with the preprogrammed with
demo firmware and mounted on a functional sample meter Demo Board. The Demo Boards allow for quick
and efficient evaluation of the IC without having to write firmware or having to supply an in-circuit
emulator (ICE).
4.16
Crystal Oscillator
The oscillator of the 71M6541D/F/G and 71M6542F/G drives a standard 32.768 kHz watch crystal. The
oscillator has been designed specifically to handle these crystals and is compatible with their high
impedance and limited power handling capability. The oscillator power dissipation is very low to
maximize the lifetime of any battery backup device attached to the VBAT_RTC pin.
Board layouts with minimum capacitance from XIN to XOUT require less battery current. Good layouts
have XIN and XOUT shielded from each other and from LCD and digital signals.
Since the oscillator is self-biasing, an external resistor must not be connected across the crystal.
4.17
Meter Calibration
Once the Teridian 71M654x energy meter device has been installed in a meter system, it must be
calibrated. A complete calibration includes the following:
•
•
Establishment of the reference temperature (e.g., typically 22 ⁰C)
Calibration of the metrology section, i.e., calibration for tolerances of the current sensors, voltage
dividers and signal conditioning components as well as of the internal reference voltage (VREF) at
the reference temperature (e.g., typically 22 ⁰C).
•
Calibration of the oscillator frequency using the RTCA_ADJ[7:0] I/O RAM register (I/O RAM 0x2504).
The metrology section can be calibrated using the gain and phase adjustment factors accessible to the
CE. The gain adjustment is used to compensate for tolerances of components used for signal conditioning,
especially the resistive components. Phase adjustment is provided to compensate for phase shifts
introduced by the current sensors or by the effects of reactive power supplies.
Due to the flexibility of the MPU firmware, any calibration method, such as calibration based on energy, or
current and voltage can be implemented. It is also possible to implement segment-wise calibration
(depending on current range).
The 71M6541D/F/G and 71M6542F/G support common industry standard calibration techniques, such
as single-point (energy-only), multi-point (energy, Vrms, Irms), and auto-calibration.
Teridian provides a calibration spreadsheet file to facilitate the calibration process. Contact your Teridian
representative to obtain a copy of the latest calibration spreadsheet file for the 71M654x.
104
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5
Firmware Interface
5.1
I/O RAM Map –Functional Order
In Table 74 and Table 75, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’.
Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with
an ‘R’, and must always be written with a zero. Writing values other than zero to reserved bits may have undesirable side effects and must be
avoided. Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected
to the VBAT pin.
The I/O RAM locations listed in Table 74 have sequential addresses to facilitate reading by the MPU (e.g., in order to verify their contents). These
I/O RAM locations are usually modified only at boot-up. The addresses shown in Table 74 are an alternative sequential address to the addresses
from Table 75 which are used throughout document. For instance, EQU[2:0] can be accessed at I/O RAM 0x2000[7:5] or at I/O RAM 0x2106[7:5].
Table 74: I/O RAM Map – Functional Order, Basic Configuration
Name
Addr
CE6
CE5
CE4
CE3
CE2
CE1
CE0
RCE0
RTMUX
Reserved
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
TEMP
LCD0
LCD1
LCD2
LCD_MAP6
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
200A
200B
200C
200D
200E
200F
2010
2011
2012
2013
2014
Rev 2
Bit 7
Bit 6
EQU[2:0]
U
Bit 5
Bit 4
U
Bit 3
Bit 2
Bit 1
Bit 0
CHOP_E[1:0]
RTM_E
CE_E
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
U
U
CE_LCTN[5:0]
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
R
R
DIFFB_E
DIFFA_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
CHOPR[1:0]
R
R
RMT_E
R
R
R
U
TMUXRB[2:0]
U
TMUXRA[2:0]
U
U
R
U
U
U
U
U
MUX_DIV[3:0]
MUX10_SEL
MUX9_SEL
MUX8_SEL
MUX7_SEL
MUX6_SEL
MUX5_SEL
MUX4_SEL
MUX3_SEL
MUX2_SEL
MUX1_SEL
MUX0_SEL
TEMP_BSEL
TEMP_PWR
OSC_COMP
TEMP_BAT TBYTE_BUSY
TEMP_PER[2:0]
LCD_E
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_CLK[1:0]
LCD_VMODE[1:0]
LCD_BLNKMAP23[5:0]
LCD_BAT
R
LCD_BLNKMAP22[5:0]
LCD_MAP[55:48]
105
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
U
U
U
DIO_R11[2:0]
U
DIO_R9[2:0]
U
DIO_R7[2:0]
U
DIO_R5[2:0]
U
DIO_R3[2:0]
U
U
U
OPT_TXE[1:0]
OPT_FDC[1:0]
U
OPT_RXDIS
U
U
U
U
EX_YPULSE
EX_RTCT
U
EX_RTC1M
EX_VPULSE
EW_RX
EW_PB
EW_DIO4
SFMM[7:0]*
SFMS[7:0]*
LCD_MAP5 2015
LCD_MAP4 2016
LCD_MAP3 2017
LCD_MAP2 2018
LCD_MAP1 2019
LCD_MAP0 201A
U
U
DIO_R5
201B
U
DIO_R4
201C
U
DIO_R3
201D
U
DIO_R2
201E
U
DIO_R1
201F
U
DIO_R0
2020
DIO_EEX[1:0]
DIO0
2021
DIO_PW
DIO_PV
DIO1
2022
DIO_PX
DIO_PY
DIO2
2023
EX_EEX
EX_XPULSE
INT1_E
2024
EX_SPI
EX_WPULSE
INT2_E
2025
WAKE_E
2026
SFMM
2080
SFMS
2081
Notes:
*SFMM and SFMS are accessible only through the SPI slave port. See Invoking SFM (page 77) for details.
†
Bit 1
Bit 0
DIO_RPB[2:0]
DIO_R10[2:0]
DIO_R8[2:0]
DIO_R6[2:0]
DIO_R4[2:0]
DIO_R2[2:0]
OPT_TXMOD
OPT_RXINV
U
EX_RTC1S
OPT_TXINV
OPT_BB
U
EX_XFER
EW_DIO52†
EW_DIO55
71M6542F/G only.
106
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 75 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits
have a darker gray background.
Table 75: I/O RAM Map – Functional Order
Name
Addr
CE and ADC
MUX5
2100
MUX4
2101
MUX3
2102
MUX2
2103
MUX1
2104
MUX0
2105
CE6
2106
CE5
2107
CE4
2108
CE3
2109
CE2
210A
CE1
210B
CE0
210C
RTM0
210D
RTM0
210E
RTM1
210F
RTM2
2110
RTM3
2111
CLOCK GENERATION
CKGN
2200
LCD/DIO
VREF TRIM FUSES
TRIMT
2309
LCD/DIO
LCD0
2400
LCD1
2401
LCD2
2402
LCD_MAP6
2405
LCD_MAP5
2406
Rev 2
Bit 7
U
Bit 6
Bit 5
MUX_DIV[3:0]
MUX9_SEL[3:0]
MUX7_SEL[3:0]
MUX5_SEL[3:0]
MUX3_SEL[3:0]
MUX1_SEL[3:0]
EQU[2:0]
U
U
U
U
R
U
R
U
DIFFB_E
U
U
U
ADC_DIV
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MUX10_SEL[3:0]
MUX8_SEL[3:0]
MUX6_SEL[3:0]
MUX4_SEL[3:0]
MUX2_SEL[3:0]
MUX0_SEL[3:0]
U
CHOP_E[1:0]
RTM_E
CE_E
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
CE_LCTN[5:0]
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
DIFFA_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
U
U
U
RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
PLL_FAST
RESET
MPU_DIV[2:0]
TRIMT[7:0]
LCD_E
LCD_VMODE[1:0]
LCD_BAT
R
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_CLK[1:0]
107
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Addr
Bit 7
Bit 6
Bit 5
LCD_MAP4
LCD_MAP3
LCD_MAP2
LCD_MAP1
LCD_MAP0
LCD4
LCD_DAC
SEGDIO0
…
SEGDIO15
SEGDIO16
…
SEGDIO45
SEGDIO46
…
SEGDIO50
SEGDIO51
…
SEGDIO55
2407
2408
2409
240A
240B
240C
240D
2410
…
241F
2420
…
243D
243E
…
2442
2443
…
2447
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
DIO_R5
DIO_R4
DIO_R3
DIO_R2
DIO_R1
DIO_R0
DIO0
DIO1
DIO2
NV BITS
RESERVED
RESERVED
TMUX
2450
2451
2452
2453
2454
2455
2456
2457
2458
108
2500
2501
2502
U
U
U
U
U
U
U
DIO_EEX[1:0]
DIO_PW
DIO_PV
DIO_PX
DIO_PY
U
U
U
U
U
U
Bit 4
Bit 3
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
U
U
Bit 1
LCD_RST
LCD_BLANK
LCD_DAC[4:0]
LCD_SEG0[5:0]
…
LCD_SEG15[5:0]
LCD_SEGDIO16[5:0]
…
LCD_SEGDIO45[5:0]
LCD_SEG46[5:0]
…
LCD_SEG50[5:0]
LCD_SEGDIO51[5:0]
…
LCD_SEGDIO55[5:0]
U
U
DIO_R11[2:0]
DIO_R9[2:0]
DIO_R7[2:0]
DIO_R5[2:0]
DIO_R3[2:0]
U
U
OPT_FDC[1:0]
U
U
U
R
Bit 2
U
U
U
U
U
U
U
U
OPT_TXE[1:0]
U
OPT_RXDIS
U
U
R
U
R
U
Bit 0
LCD_ON
DIO_RPB[2:0]
DIO_R10[2:0]
DIO_R8[2:0]
DIO_R6[2:0]
DIO_R4[2:0]
DIO_R2[2:0]
OPT_TXMOD
OPT_RXINV
U
OPT_TXINV
OPT_BB
U
R
U
R
U
TMUX[5:0]
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Addr
TMUX2
2503
RTC1
2504
71M6x01 Interface
REMOTE2
2602
REMOTE1
2603
RBITS
INT1_E
2700
INT2_E
2701
SECURE
2702
Analog0
2704
VERSION
2706
INTBITS
2707
FLAG0
SFR E8
FLAG1
SFR F8
STAT
SFR F9
REMOTE0 SFR FC
SPI1
SFR FD
SPI0
2708
RCE0
2709
RTMUX
270A
INFO_PG
270B
DIO3
270C
NV RAM and RTC
2800NVRAMxx
287F
WAKE
2880
STEMP1
2881
STEMP0
2882
BSENSE
2885
LKPADDR
2887
LKPDATA
2888
LKPCTRL
2889
RTC0
2890
Rev 2
Bit 7
U
U
Bit 6
U
Bit 5
U
Bit 4
Bit 3
Bit 2
TMUX2[4:0]
Bit 1
Bit 0
EX_RTC1M
U
FLSH_RDE
EX_RTC1S
U
FLSH_WRE
SPARE[2:0]
EX_XFER
U
R
INT2
IE_RTC1M
U
INT1
IE_RTC1S
U
VSTAT[2:0]
INT0
IE_XFER
PB_STATE
R
U
U
R
TMUXRA[2:0]
U
U
INFO_PG
U
U
U
U
U
U
LKP_RD
U
LKP_WR
U
RTCA_ADJ[6:0]
RMT_RD[15:8]
RMT_RD[7:0]
EX_EEX
EX_SPI
VREF_CAL
U
IE_EEX
IE_SPI
U
EX_XPULSE EX_YPULSE
EX_WPULSE EX_VPULSE
FLSH_UNLOCK[3:0]
VREF_DIS
PRE_E
INT6
IE_XPULSE
IE_WPULSE
U
PERR_RD
CHOPR[1:0]
U
U
U
R
U
U
INT5
IE_YPULSE
IE_VPULSE
U
PERR_WR
R
R
U
PORT_E
EX_RTCT
U
U
U
R
ADC_E
BCURR
VERSION[7:0]
INT4
INT3
IE_RTCT
U
U
U
PLL_OK
U
RCMD[4:0]
SPI_CMD[7:0]
SPI_STAT[7:0]
R
RMT_E
R
U
U
U
SPI_E
SPI_SAFE
R
NVRAM[0] – NVRAM[7F] – Direct Access
STEMP[2:0]
LKPAUTOI
U
RTC_WR
U
RTC_RD
U
U
WAKE_TMR[7:0]
STEMP[10:3]
U
U
BSENSE[7:0]
LKPADDR[6:0]
LKPDAT[7:0]
U
U
RTC_FAIL
U
109
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RTC_SBSC[7:0]
RTC_SEC[5:0]
RTC_MIN[5:0]
U
RTC_HR[4:0]
U
U
U
RTC_DAY[2:0]
U
RTC_DATE[4:0]
U
U
RTC_MO[3:0]
RTC_YR[7:0]
U
U
U
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
RTC_Q[1:0]
RTC_TMIN[5:0]
U
RTC_THR[4:0]
OSC_COMP
TEMP_BAT TBYTE_BUSY
TEMP_PER[2:0]
WF_RSTBIT
WF_OVF
WF_ERST
WF_BADVDD
WF_TMR
WF_RX
WF_PB
WF_DIO4
WF_DIO52
WF_DIO55
WAKE_ARM
U
EW_RX
EW_PB
EW_DIO4
EW_DIO52 †
EW_DIO55
U
U
U
U
U
U
RTC2
2892
U
U
RTC3
2893
U
U
RTC4
2894
U
U
RTC5
2895
U
U
RTC6
2896
U
U
RTC7
2897
U
U
RTC8
2898
RTC9
2899
U
U
RTC10
289B
RTC11
289C
RTC12
289D
U
U
RTC13
289E
U
U
RTC14
289F
TEMP_BSEL
TEMP_PWR
TEMP
28A0
WF_RST
WF1
28B0 WF_CSTART
U
U
WF2
28B1
SLEEP
LCD_ONLY
MISC
28B2
U
U
WAKE_E
28B3
WD_RST
TEMP_START
WDRST
28B4
MPU PORTS
DIO_DIR[15:12]
P3
SFR B0
DIO_DIR[11:8]
P2
SFR A0
DIO_DIR[7:4]
P1
SFR 90
DIO_DIR[3:0]
P0
SFR 80
FLASH
FLSH_ERASE[7:0]
ERASE
SFR 94
SECURE
U
U
FLSH_PEND
FLSHCTL SFR B2 PREBOOT
FLSH_PGADR[5:0]
PGADR
SFR B7
I2C
EEDATA[7:0]
EEDATA
SFR 9E
EECTRL[7:0]
EECTRL
SFR 9F
†
71M6542F/G only
110
DIO[15:12]
DIO[11:8]
DIO[7:4]
DIO[3:0]
FLSH_PSTWR FLSH_MEEN
U
FLSH_PWE
U
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5.2
I/O RAM Map – Alphabetical Order
Table 76 lists I/O RAM bits and registers in alphabetical order.
Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and
copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The
remaining bits are mapped to the address space 0x2XXX. Bits with R (read) direction can be read by the MPU. Columns labeled Rst and Wk
describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the
NV supply and is not initialized. Write-only bits return zero when they are read.
Locations that are shaded in grey are non-volatile (i.e., battery-backed).
Table 76: I/O RAM Map – Functional Order
Name
Location
ADC_E
2704[4]
ADC_DIV
2200[5]
BCURR
BSENSE[7:0]
CE_E
2704[3]
2885[7:0]
2106[0]
CE_LCTN[5:0]
2109[5:0]
CHIP_ID[15:8]
CHIP_ID[7:0]
2300[7:0]
2301[7:0]
CHOP_E[1:0]
2106[3:2]
Rev 2
Rst Wk Dir
0
Description
0
R/W Enables ADC and VREF. When disabled, reduces bias current.
ADC_DIV controls the rate of the ADC and FIR clocks.
The ADC_DIV setting determines whether MCK is divided by 4 or 8:
0 = MCK/4
1 = MCK/8
The
resulting
ADC and FIR clock is as shown below.
0 0 R/W
PLL_FAST = 0
PLL_FAST = 1
MCK
6.291456 MHz
19.660800 MHz
ADC_DIV = 0
1.572864 MHz
4.9152 MHz
ADC_DIV = 1
0.786432 MHz
2.4576 MHz
0 0 R/W Connects a 100 µA load to the battery selected by TEMP_BSEL.
– –
R The result of the battery measurement. See 2.5.6 71M654x Battery Monitor.
0 0 R/W CE enable.
CE program location. The starting address for the CE program is
31 31 R/W
1024*CE_LCTN.
0 0
R
These bytes contain the chip identification.
0 0
R
Chop enable for the reference bandgap circuit. The value of CHOP changes
on the rising edge of MUXSYNC according to the value in CHOP_E:
0 0 R/W
00 = toggle1 01 = positive 10 = reversed 11 = toggle
1
except at the mux sync edge at the end of an accumulation interval.
111
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
CHOPR[1:0]
2709[7:6]
DIFFA_E
DIFFB_E
DIO_R2[2:0]
DIO_R3[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_RPB[2:0]
210C[4]
210C[5]
2455[2:0]
2455[6:4]
2454[2:0]
2454[6:4]
2453[2:0]
2453[6:4]
2452[2:0]
2452[6:4]
2451[2:0]
2451[6:4]
2450[2:0]
DIO_DIR[15:12]
DIO_DIR[11:8]
DIO_DIR[7:4]
DIO_DIR[3:0]
DIO[15:12]
DIO[11:8]
DIO[7:4]
DIO[3:0]
SFR B0[7:4]
SFR A0[7:4]
SFR 90[7:4]
SFR 80[7:4]
Rst Wk Dir
Description
The CHOP settings for the remote sensor.
00 = Auto chop. Change every MUX frame.
00 00 R/W 01 = Positive
10 = Negative
11 = Auto chop. Same as 00.
0 0 R/W Enables differential configuration for the IA current input (IAP-IAN).
0 0 R/W Enables differential configuration for the IB current input (IBP-IBN).
0
Connects PB and dedicated I/O pins DIO2 through DIO11 to internal resources.
If more than one input is connected to the same resource, the MULTIPLE
0
column below specifies how they are combined.
0
0
MULTIPLE
DIO_Rx Resource
0
0
NONE
–
0 – R/W
1
Reserved
OR
0
2
T0 (Timer0 clock or gate)
OR
0
3
T1 (Timer1 clock or gate)
OR
0
4
IO
interrupt
(int0)
OR
0
5
IO interrupt (int1)
OR
0
F
SFR B0[3:0]
SFR A0[3:0] SFR 90[3:0] F
SFR 80[3:0]
F
Programs the direction of the first 16 DIO pins. 1 indicates output. Ignored if
the pin is not configured as I/O. See DIO_PV and DIO_PW for special option
R/W for the SEGDIO0 and SEGDIO1 outputs. See DIO_EEX for special option for
SEGDIO2 and SEGDIO3. Note that the direction of DIO pins above 15 is set by
SEGDIOx[1]. See PORT_E to avoid power-up spikes.
F
The value on the first 16 DIO pins. Pins configured as LCD reads zero.
When written, changes data on pins configured as outputs. Pins configured
R/W
as LCD or input ignore writes. Note that the data for DIO pins above 15 is
set by SEGDIOx[0].
When set, converts pins SEGDIO3/SEGDIO2 to interface with external
EEPROM. SEGDIO2 becomes SDCK and SEGDIO3 becomes bi-directional
SDATA, but only if LCD_MAP[2] and LCD_MAP[3] are cleared.
DIO_EEX[1:0]
2456[7:6]
0
–
R/W
DIO_EEX[1:0]
00
01
10
11
112
Function
Disable EEPROM interface
2-Wire EEPROM interface
3-Wire EEPROM interface
3-Wire EEPROM interface with separate DO (DIO3)
and DI (DIO8) pins.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
DIO_PV
DIO_PW
DIO_PX
DIO_PY
EEDATA[7:0]
EECTRL[7:0]
Location
2457[6]
2457[7]
2458[7]
2458[6]
SFR 9E
SFR 9F
Rst Wk Dir
0
0
0
0
0
0
–
–
–
–
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Causes VARPULSE to be output on pin SEGDIO1, if LCD_MAP[1] = 0.
Causes WPULSE to be output on pin SEGDIO0, if LCD_MAP[0] = 0.
Causes XPULSE to be output on pin SEGDIO6 , if LCD_MAP[6] = 0.
Causes YPULSE to be output on pin SEGDIO7 , if LCD_MAP[7] = 0.
Serial EEPROM interface data.
Serial EEPROM interface control.
Status
Bit
Name
Read/
Write
Reset
State
7
ERROR
R
0
6
BUSY
R
0
5
RX_ACK
R
1
Polarity Description
1 when an illegal command
is received.
Positive 1 when serial data bus is
busy.
1 indicates that the
Positive
EEPROM sent an ACK bit.
Positive
Specifies the power equation.
EQU
0
EQU[2:0]
2106[7:5]
0
0
R/W
1
2†
Watt & VAR Formula
(WSUM/VARSUM)
VA*IA
1 element, 2W 1φ
VA*(IA-IB)/2
1 element, 3W 1φ
VA*IA + VB*IB
2 element, 3W 3φ Delta
Inputs Used for Energy/Current
Calculation
W0SUM/
W1SUM/
I0SQ I1SQ
VAR0SUM
VAR1SUM SUM SUM
VA*IA
VA*IB1
IA
IB1
VA*(IA-IB)/2
–
IA-IB
IB
VA*IA
VB*IB
IA
IB
Note:
1. Optionally, IB may be used to measure neutral current.
†
71M6542F/G only
Rev 2
113
71M6541D/F/G and 71M6542F/G Data Sheet
Name
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
Location
Rst Wk Dir
Description
2700[0]
2700[1]
2700[2]
2700[3]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
0
0
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC,
etc. The bits are set by hardware and cannot be set by writing a 1. The bits
R/W are reset by writing 0. Note that if one of these interrupts is to enabled, its
corresponding 8051 EX enable bit must also be set. See 2.4.8 Interrupts for
details.
EW_DIO4
28B3[2]
0
–
R/W
EW_DIO52
28B3[1]
0
–
R/W
EW_DIO55
28B3[0]
0
–
R/W
EW_PB
28B3[3]
0
–
R/W
EW_RX
28B3[4]
0
–
R/W
210C[2:1]
0
0
R/W
FIR_LEN[1:0]
114
Connects SEGDIO4 to the WAKE logic and permits SEGDIO4 rising to wake
the part. This bit has no effect unless DIO4 is configured as a digital input.
Connects SEGDIO52 to the WAKE logic and permits SEGDIO52 rising to
wake the part. This bit has no effect unless SEGDIO52 is configured as a
digital input.
The SEGDIO52 pin is only available in the 71M6542F/G.
Connects SEGDIO55 to the WAKE logic and permits SEGDIO55 rising to
wake the part. This bit has no effect unless SEGDIO55 is configured as a
digital input.
Connects PB to the WAKE logic and permits PB rising to wake the part. PB
is always configured as an input.
Connects RX to the WAKE logic and permits RX rising to wake the part. See
the WAKE description on page 87 for de-bounce issues.
Determines the number of ADC cycles in the ADC decimation FIR filter.
PLL_FAST = 1:
FIR_LEN[1:0]
ADC Cycles
00
141
01
288
10
384
PLL_FAST = 0:
FIR_LEN[1:0]
ADC Cycles
00
135
01
276
10
Not Allowed
The ADC LSB size and full-scale values depend on the FIR_LEN[1:0] setting.
Refer to 6.4.15 ADC Converter on page 149.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
Rst Wk Dir
SFR 94[7:0]
0
0
FLSH_MEEN
SFR B2[1]
0
0
FLSH_PEND
SFR B2[3]
0
0
SFR B7[7:2]
0
0
FLSH_PSTWR
SFR B2[2]
0
0
FLSH_PWE
SFR B2[0]
0
0
FLSH_RDE
2702[2]
–
–
2702[7:4]
0
0
2702[1]
–
–
FLSH_ERASE[7:0]
FLSH_PGADR[5:0]
FLSH_UNLOCK[3:0]
FLSH_WRE
Rev 2
Description
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash
Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order
to initiate the appropriate Erase cycle.
(default = 0x00).
W
0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR[5:0] (SFR 0xB7[7:2]).
0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN and the ICE port must be enabled.
Any other pattern written to FLSH_ERASE has no effect.
Mass Erase Enable
0 = Mass Erase disabled (default).
W
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Indicates that a timed flash write is pending. If another flash write is attempted,
R
it is ignored.
Flash Page Erase Address
FLSH_PGADR[5:0] – Flash Page Address (page 0 thru 63) that is erased during
W
the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
Enables timed flash writes. When 1, and if CE_E = 1, flash write requests are
stored in a one-element deep FIFO and are executed when CE_BUSY falls.
R/W
FLSH_PEND can be read to determine the status of the FIFO. If
FLSH_PSTWR = 0 or if CE_E = 0, flash writes are immediate.
Program Write Enable
0 = MOVX commands refer to External RAM Space, normal operation (default).
R/W 1 = MOVX @DPTR,A moves A to External Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to this bit
are inhibited when interrupts are enabled.
Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE =
R
(!SECURE)
Must be a ‘2’ to enable any flash modification. See the description of Flash
R/W
security for more details.
R Indicates that the flash may be written through ICE or SPI slave ports.
115
71M6541D/F/G and 71M6542F/G Data Sheet
Name
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR E8[0]
SFR E8[1]
SFR E8[2]
SFR E8[4]
SFR F8[7]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[4]
SFR F8[3]
0
0
INTBITS
2707[6:0]
–
–
LCD_ALLCOM
2400[3]
0
–
LCD_BAT
2402[7]
0
–
2401[5:0]
2402[5:0]
0
–
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
Location
Rst Wk Dir
Description
Interrupt flags for external interrupts 2 and 6. These flags monitor the source
of the int6 and int2 interrupts (external interrupts to the MPU core). These
flags are set by hardware and must be cleared by the software interrupt
handler. The IEX2 (SFR 0xC0[1]) and IEX6 (SFR 0xC0[5]) interrupt flags are
R/W
automatically cleared by the MPU core when it vectors to the interrupt
handler. IEX2 and IEX6 must be cleared by writing zero to their corresponding
bit positions in SFR 0xC0, while writing ones to the other bit positions that are
not being cleared.
Interrupt inputs. The MPU may read these bits to see the input to external
interrupts INT0, INT1, up to INT6. These bits do not have any memory and
are primarily intended for debug use.
Configures SEG/COM bits as COM. Has no effect on pins whose LCD_MAP
R/W
bit is zero.
R/W Connects the LCD power supply to VBAT in all modes.
Identifies which segments connected to SEG23 and SEG22 should blink. 1
R/W means ‘blink.’ The most significant bit corresponds to COM5, the least
significant, to COM0.
Sets the LCD clock frequency. Note: fw = 32768 Hz
R
LCD_CLK LCD Clock Frequency
LCD_CLK[1:0]
2400[1:0]
0
–
R/W
00
01
LCD_DAC[4:0]
LCD_E
116
240D[4:0]
0
–
2400[7]
0
–
fW
= 64 Hz
29
fW
= 128 Hz
28
LCD_CLK
10
11
LCD Clock Frequency
fW
= 256 Hz
27
fW
= 512 Hz
26
The LCD contrast DAC. This DAC controls the VLCD voltage and has an
output range of 2.5 V to 5 V. The VLCD voltage is
VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31
R/W
Thus, the LSB of the DAC is 80.6 mV. The maximum DAC output voltage is
limited by V3P3SYS, VBAT, and whether LCD_BSTE = 1.
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are
R/W
ground as are the COM and SEG outputs if their LCD_MAP bit is 1.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
Location
2405[7:0]
2406[7:0]
2407[7:0]
2408[7:0]
2409[7:0]
240A[7:0]
240B[7:0]
Rst Wk Dir
0
0
0
0
0
0
0
–
–
–
–
–
–
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Enables LCD segment driver mode of combined SEGDIO pins. Pins that
cannot be configured as outputs (SEG48 through SEG50) become inputs with
internal pull ups when their LCD_MAP bit is zero. Also, note that SEG48
through SEG50 are multiplexed with the in-circuit emulator signals. When the
ICE_E pin is high, the ICE interface is enabled, and SEG48 through SEG50
become E_RXTX, E_TCLK and E_RST, respectively.
Selects the LCD bias and multiplex mode.
LCD_MODE
000
001
010
011
Output
4 states, 1/3 bias
3 states, 1/3 bias
2 states, ½ bias
3 states, ½ bias
LCD_MODE
100
101
110
Output
Static display
5 states, 1/3 bias
6 states, 1/3 bias
2400[6:4]
0
–
R/W
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
–
LCD_ONLY
28B2[6]
0
0
LCD_RST
240C[2]
0
–
R/W Turns on or off all LCD segments without changing LCD data. If both bits are
R/W set, the LCD display is turned on.
Puts the IC to sleep, but with LCD display still active. Ignored if system power
W is present. It awakens when Wake Timer times out, when certain DIO pins
are raised, or when system power returns. See 3.2 Battery Modes.
Clear all bits of LCD data. These bits affect SEGDIO pins that are configured
R/W
as LCD drivers. This bit does not auto clear.
2410[5:0] to
241F[5:0]
0
–
R/W
2420[5:0] to
243D[5:0]
0
–
SEG and DIO data for SEGDIO16 through SEGDIO45. If configured as DIO,
R/W bit 1 is direction (1 is output, 0 is input), bit 0 is data, and the other bits are
ignored.
243E[5:0] to 2442[5:0]
0
–
R/W
–
SEG and DIO data for SEGDIO51 through SEGDIO55. If configured as DIO,
bit 1 is direction (1 is output, 0 is input), bit 0 is data, and the other bits are
R/W
ignored.
SEGDIO52 through SEDIO54 are available only on the 71M6542F/G.
LCD_MODE[2:0]
LCD_SEG0[5:0]
to
LCD_SEG15[5:0]
LCD_SEGDIO16[5:0]
to
LCD_SEGDIO45[5:0]
LCD_SEG46[5:0]
to
LCD_SEG50[5:0]
LCD_SEGDIO51[5:0]
to
LCD_SEGDIO55[5:0]
Rev 2
2443[5:0] to 2447[5:0]
0
SEG Data for SEG0 through SEG15. DIO data for these pins is in SFR
space.
SEG data for SEG46 through SEG50. These pins cannot be configured as
DIO.
117
71M6541D/F/G and 71M6542F/G Data Sheet
Name
LCD_VMODE[1:0]
LCD_Y
LKPADDR[6:0]
LKPAUTOI
LKPDAT[7:0]
LKP_RD
LKP_WR
Location
2401[7:6]
Rst Wk Dir
00 00 R/W
2400[2]
0
–
R/W
2887[6:0]
0
0
R/W
2887[7]
0
0
R/W
2888[7:0]
0
0
R/W
2889[1]
2889[0]
0
0
0
0
R/W
R/W
MPU_DIV[2:0]
2200[2:0]
0
0
R/W
MUX0_SEL[3:0]
MUX1_SEL[3:0]
MUX2_SEL[3:0]
MUX3_SEL[3:0]
MUX4_SEL[3:0]
MUX5_SEL[3:0]
MUX6_SEL[3:0]
MUX7_SEL[3:0]
MUX8_SEL[3:0]
MUX9_SEL[3:0]
MUX10_SEL[3:0]
2105[3:0]
2105[7:4]
2104[3:0]
2104[7:4]
2103[3:0]
2103[7:4]
2102[3:0]
2102[7:4]
2101[3:0]
2101[7:4]
2100[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
118
Description
Specifies how VLCD is generated. See 2.5.8.4 for the definition of V3P3L.
LCD_VMODE
11
10
01
00
Description
External VLCD
LCD boost and LCD DAC enabled
LCD DAC enabled
No boost and no DAC. VLCD=V3P3L.
LCD Blink Frequency (ignored if blink is disabled).
1 = 1 Hz, 0 = 0.5 Hz
The address for reading and writing the RTC lookup RAM
Auto-increment flag. When set, LKPADDR auto-increments every time
LKP_RD or LKP_WR is pulsed. The incremented address can be read at
LKPADDR[6:0].
The data for reading and writing the RTC lookup RAM.
Strobe bits for the RTC lookup RAM read and write. When set, the
LKPADDR[6:0] field and LKPDAT register is used in a read or write
operation. When a strobe is set, it stays set until the operation completes, at
which time the strobe is cleared and LKPADDR[6:0] is incremented if the
LKPAUTOI bit is set.
MPU clock rate is:
MPU Rate = MCK Rate * 2-(2+MPU_DIV[2:0]).
The maximum value for MPU_DIV[2:0] is 4. Based on the default values of
the PLL_FAST bit and MPU_DIV[2:0], the power up MPU rate is 6.29 MHz / 4
= 1.5725 MHz. The minimum MPU clock rate is 38.4 kHz when PLL_FAS T =
1.
Selects which ADC input is to be converted during time slot 0.
Selects which ADC input is to be converted during time slot 1.
Selects which ADC input is to be converted during time slot 2.
Selects which ADC input is to be converted during time slot 3.
Selects which ADC input is to be converted during time slot 4.
Selects which ADC input is to be converted during time slot 5.
Selects which ADC input is to be converted during time slot 6.
Selects which ADC input is to be converted during time slot 7.
Selects which ADC input is to be converted during time slot 8.
Selects which ADC input is to be converted during time slot 9.
Selects which ADC input is to be converted during time slot 10.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
MUX_DIV[3:0]
2100[7:4]
0
0
2457[0]
0
–
OPT_BB
Rst Wk Dir
Description
MUX_DIV[3:0] is the number of ADC time slots in each MUX frame. The
R/W
maximum number of time slots is 11.
Configures the input of the optical port to be a DIO pin to allow it to be
bit-banged. In this case, DIO5 becomes a third high speed UART. Refer to
R/W 2.5.7 UART and Optical Interface under the “Bit Banged Optical UART
(Third UART)” sub-heading on page 58.
Selects OPT_TX modulation duty cycle.
OPT_FDC[1:0]
2457[5:4]
0
–
R/W
OPT_RXDIS
2457[2]
0
–
R/W
OPT_RXINV
2457[1]
0
–
R/W
00 –
R/W
OPT_TXE [1:0]
2456[3:2]
OPT_TXINV
2456[0]
0
–
R/W
OPT_TXMOD
2456[1]
0
–
R/W
OSC_COMP
28A0[5]
0
–
R/W
PB_STATE
SFR F8[0]
0
0
R
PERR_RD
PERR_WR
SFR FC[6]
SFR FC[5]
0
0
R/W
PLL_OK
SFR F9[4]
0
0
R
Rev 2
OPT_FDC
00
01
10
11
Function
50% Low
25% Low
12.5% Low
6.25% Low
OPT_RX can be configured as an input to the optical UART or as SEGDIO55.
OPT_RXDIS = 0 and LCD_MAP[55] = 0: OPT_RX
OPT_RXDIS = 1 and LCD_MAP[55] = 0: DIO55
OPT_RXDIS = 0 and LCD_MAP[55] = 1: SEG55
OPT_RXDIS = 1 and LCD_MAP[55] = 1: SEG55
Inverts result from OPT_RX comparator when 1. Affects only the UART input.
Has no effect when OPT_RX is used as a DIO input.
Configures the OPT_TX output pin.
If LCD_MAP[51] = 0:
00 = DIO51, 01 = OPT_TX, 10 = WPULSE, 11 = VARPULSE
If LCD_MAP[51] = 1:
xx = SEG51
Invert OPT_TX when 1. This inversion occurs before modulation.
Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is
modulated when it would otherwise have been zero. The modulation is applied
after any inversion caused by OPT_TXINV.
Enables the automatic update of RTC_P and RTC_Q every time the temperature
is measured.
The de-bounced state of the PB pin.
The IC sets these bits to indicate that a parity error on the remote sensor has
been detected. Once set, the bits are remembered until they are cleared by
the MPU.
Indicates that the clock generation PLL is settled.
119
71M6541D/F/G and 71M6542F/G Data Sheet
Name
PLL_FAST
Location
2200[4]
PLS_MAXWIDTH[7:0]
210A[7:0]
PLS_INTERVAL[7:0]
210B[7:0]
Rst Wk Dir
Description
Controls the speed of the PLL and MCK.
R/W 1 = 19.66 MHz (XTAL * 600)
0 = 6.29 MHz (XTAL * 192)
PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going
pulse if PLS_INV=0 or high-going pulse if PLS_INV=1). The maximum pulse
width is (2*PLS_MAXWIDTH[7:0] + 1)*TI. Where TI is PLS_INTERVAL[7:0] in
FF FF R/W
units of CK_FIR clock cycles. If PLS_INTERVAL[7:0] = 0 or
PLS_MAXWIDTH[7:0] = 255, no pulse width checking is performed and the
output pulses have 50% duty cycle. See 2.3.6.2 VPULSE and WPULSE.
PLS_INTERVAL[7:0] determines the interval time between pulses. The time
between output pulses is PLS_INTERVAL[7:0]*4 in units of CK_FIR clock
cycles. If PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output
as soon as the CE issues them. PLS_INTERVAL[7:0] is calculated as follows:
PLS_INTERVAL[7:0] = Floor ( Mux frame duration in CK_FIR cycles / CE pulse
0
0
0
0
updates per Mux frame / 4 )
PLS_INV
210C[0]
0
0
PORT_E
270C[5]
0
0
PRE_E
PREBOOT
2704[5]
SFRB2[7]
0
–
0
–
RCMD[4:0]
SFR FC[4:0]
0
0
RESET
2200[3]
0
0
RFLY_DIS
210C[3]
0
0
120
R/W
For example, since the 71M654x CE code is written to generate 6 pulses in one
integration interval, when the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0)
and that the frame duration is 1950 CK_FIR clock cycles, PLS_INTERVAL[7:0]
should be written with Floor(1950 / 6 / 4) = 81 so that the five pulses are
evenly spaced in time over the integration interval and the last pulse is issued
just prior to the end of the interval. See 2.3.6.2 VPULSE and WPULSE.
Inverts the polarity of WPULSE, VARPULSE, XPULSE and YPULSE.
R/W Normally, these pulses are active low. When inverted, they become active
high.
Enables outputs from the pins SEGDIO0-SEGDIO15. PORT_E = 0 after reset
R/W and power-up blocks the momentary output pulse that would occur on
SEGDIO0 to SEGDIO15.
R/W Enables the 8x pre-amplifier.
R Indicates that pre-boot sequence is active.
When the MPU writes a non-zero value to RCMD[4:0], the IC issues a
R/W command to the appropriate remote sensor. When the command is complete,
the IC clears RCMD[4:0].
W When set, writes a one to WF_RSTBIT and then causes a reset.
Controls how the IC drives the power pulse for the 71M6x01. When set, the
R/W power pulse is driven high and low. When cleared, it is driven high followed
by an open circuit fly-back interval.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
RMT_E
2709[3]
0
0
2602[7:0]
2603[7:0]
0
0
R
2890[4]
0
0
R/W
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
289B[2:0]
289C[7:0]
289D[7:2]
4
0
0
4
0
0
R/W
RTC_Q[1:0]
289D[1:0]
0
0
R/W
2890[6]
0
0
R/W
RTC_SBSC[7:0]
RTC_TMIN[5:0]
2892[7:0]
289E[5:0]
–
0
–
–
R
R/W
RTC_THR[4:0]
289F[4:0]
0
–
R/W
2890[7]
0
0
R/W
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2893[5:0]
2894[5:0]
2895[4:0]
2896[2:0]
2897[4:0]
2898[3:0]
2899[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
R/W
RTCA_ADJ[6:0]
2504[7:0]
40 –
R/W
RMT_RD[15:8]
RMT_RD[7:0]
RTC_FAIL
RTC_RD
RTC_WR
Rev 2
Rst Wk Dir
Description
Enables the remote digital isolation interface, which transforms the IBP-IBN
R/W pins into a digital balanced differential pair. Thus, enabling these pins to
interface to the 71M6x01 isolated sensor.
Response from remote read request.
Indicates that a count error has occurred in the RTC and that the time is not
trustworthy. This bit can be cleared by writing a 0.
RTC adjust. See 2.5.4 Real-Time Clock (RTC).
0x0FFBF ≤ RTC_P ≤ 0x10040
Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value.
RTC adjust. See 2.5.4 Real-Time Clock (RTC).
Note: RTC_P[16:0] and RTC_Q[1:0] form a single 19-bit RTC adjustment value.
Freezes the RTC shadow register so it is suitable for MPU reads. When
RTC_RD is read, it returns the status of the shadow register: 0 = up to date, 1
= frozen.
Time remaining until the next 1 second boundary. LSB = 1/256 second.
The target minutes register. See RTC_THR below.
The target hours register. The RTC_T interrupt occurs when RTC_MIN
becomes equal to RTC_TMIN and RTC_HR becomes equal to RTC_THR.
Freezes the RTC shadow register so it is suitable for MPU writes. When
RTC_WR is cleared, the contents of the shadow register are written to the
RTC counter on the next RTC clock (~500 Hz). When RTC_WR is read, it
returns 1 as long as RTC_WR is set. It continues to return one until the RTC
counter actually updates.
The RTC interface registers. These are the year, month, day, hour, minute
and second parameters for the RTC. The RTC is set by writing to these
registers. Year 00 and all others divisible by 4 are defined as a leap year.
SEC 00 to 59
MIN 00 to 59
HR
00 to 23 (00 = Midnight)
DAY 01 to 07 (01 = Sunday)
DATE 01 to 31
MO
01 to 12
YR
00 to 99
Each write operation to one of these registers must be preceded by a write to
0x20A0.
Analog RTC frequency adjust register.
121
71M6541D/F/G and 71M6542F/G Data Sheet
Name
RTM_E
RTM0[9:8]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
2106[1]
210D[1:0]
210E[7:0]
210F[7:0]
2110[7:0]
2111[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
SECURE
SFR B2[6]
0
0
28B2[7]
0
0
SFR FD[7:0]
–
–
SPI_E
270C[4]
1
1
SPI_SAFE
270C[3]
0
0
SPI_STAT[7:0]
2708[7:0]
0
0
STEMP[10:3]
STEMP[2:0]
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
2881[7:0]
2882[7:5]
2107[4:0]
2108[7:0]
–
–
–
–
0
0
28A0[3]
0
0
SLEEP
SPI_CMD[7:0]
TBYTE_BUSY
122
Location
Rst Wk Dir
Description
R/W Real Time Monitor enable. When 0, the RTM output is low.
Four RTM probes. Before each CE code pass, the values of these registers
are serially output on the RTM pin. The RTM registers are ignored when
R/W
RTM_E = 0. Note that RTM0 is 10 bits wide. The others assume the upper
two bits are 00.
Inhibits erasure of page 0 and flash addresses above the beginning of CE code
R/W as defined by CE_LCTN[5:0]. Also inhibits the read of flash via the SPI and ICE
port.
Puts the part to SLP mode. Ignored if system power is present. The part
W wakes when the Wake timer times out, when push button is pushed, or when
system power returns.
R SPI command register for the 8-bit command from the bus master.
SPI port enable. Enables SPI interface on pins SEGDIO36 – SEGDIO39.
R/W
Requires that LCD_MAP[36-39] = 0.
Limits SPI writes to SPI_CMD and a 16-byte region in DRAM. No other
R/W
writes are permitted.
SPI_STAT contains the status results from the previous SPI transaction.
Bit 7: Ready error: The 71M654x was not ready to read or write as directed
by the previous command.
Bit 6: Read data parity: This bit is the parity of all bytes read from the
71M654x in the previous command. Does not include the SPI_STAT byte.
Bit 5: Write data parity: This bit is the overall parity of the bytes written to the
R 71M654x in the previous command. It includes CMD and ADDR bytes.
Bit 4-2: Bottom 3 bits of the byte count. Does not include ADDR and CMD
bytes. One, two, and three byte
instructions return 111.
Bit 1: SPI FLASH mode: This bit is zero when the TEST pin is zero.
Bit 0: SPI FLASH mode ready: Used in SPI FLASH mode. Indicates that the
flash is ready to receive another write instruction.
R
The result of the temperature measurement.
R
The number of multiplexer cycles per XFER_BUSY interrupt. Maximum value
R/W
is 8191 cycles.
Indicates that hardware is still writing the 0x28A0 byte. Additional writes to
R this byte are locked out while it is one. Write duration could be as long as
6ms.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Name
TEMP_22[10:8]
TEMP_22[7:0]
Location
Rst Wk Dir
230A[2:0]
230B[7:0]
0
–
R
TEMP_BAT
28A0[4]
0
–
R/W
TEMP_BSEL
28A0[7]
0
–
TBYTE_BUSY
28A0[3]
0
0
28A0[2:0]
0
–
TEMP_PER[2:0]
Description
Storage location for STEMP at 22C. STEMP is an 11-bit word.
Causes VBAT to be measured whenever a temperature measurement is
performed.
Selects which battery is monitored by the temperature sensor: 1 = VBAT,
R/W
0 = VBAT_RTC
Indicates that hardware is still writing the 0x28A0 byte. Additional writes to
R this byte will be locked out while it is one. Write duration could be as long as
6ms.
Sets the period between temperature measurements. Automatic measurements
can be enabled in any mode (MSN, BRN, LCD, or SLP). TEMP_PER = 0
disables automatic temperature updates, in which case TEMP_START may be
used by the MPU to initiate a one-shot temperature measurement.
R/W TEMP_PER Time (seconds)
0
1-6
7
TEMP_PWR
28A0[6]
TEMP_START
28B4[6]
TMUX[5:0]
TMUX2[4:0]
TMUXRA[2:0]
2502[5:0]
2503[4:0]
270A[2:0]
VERSION[7:0]
Selects the power source for the temp sensor:
R/W 1 = V3P3D, 0 = VBAT_RTC. This bit is ignored in SLP and LCD modes,
where the temp sensor is always powered by VBAT_RTC.
When TEMP_PER = 0 automatic temperature measurements are disabled,
and TEMP_START may be set by the MPU to initiate a one-shot temperature
0 0 R/W
measurement. TEMP_START is ignored in SLP and LCD modes. Hardware
clears TEMP_START when the temperature measurement is complete.
– – R/W Selects one of 32 signals for TMUXOUT. See 2.5.12 for details.
– – R/W Selects one of 32 signals for TMUX2OUT. See 2.5.12 for details.
000 000 R/W The TMUX setting for the remote isolated sensor (71M6x01).
The silicon version index. This word may be read by firmware to determine
the silicon version.
0
–
2706[7:0]
–
–
VREF_CAL
2704[7]
0
0
VREF_DIS
2704[6]
0
1
Rev 2
No temperature updates
2(3+TEMP_PER)
Continuous updates
R
VERSION[7:0]
0001 0011
0010 0010
Silicon Version
B01
B02
Brings the ADC reference voltage out to the VREF pin. This feature is disabled
when VREF_DIS=1.
R/W Disables the internal ADC voltage reference.
R/W
123
71M6541D/F/G and 71M6542F/G Data Sheet
Name
Location
Rst Wk Dir
VSTAT[2:0]
SFR F9[2:0]
–
–
WAKE_ARM
28B2[5]
0
–
2880[7:0]
0
–
WD_RST
28B4[7]
0
0
WF_DIO4
28B1[2]
0
–
WF_DIO52
28B1[1]
0
–
WF_DIO55
28B1[0]
0
–
WF_TMR
WF_PB
WF_RX
WF_CSTART
WF_RST
WF_RSTBIT
WF_OVF
WF_ERST
WF_BADVDD
28B1[5]
28B1[3]
28B1[4]
28B0[7]
28B0[6]
28B0[5]
28B0[4]
28B0[3]
28B0[2]
0
0
0
0
1
0
0
0
0
–
–
–
WAKE_TMR[7:0]
124
–
Description
This word describes the source of power and the status of the VDD.
VSTAT Description
000
System Power OK. V3P3A>3.0v. Analog modules are functional
and accurate. [V3AOK,V3OK] = 11
001
System Power Low. 2.8v<V3P3A<3.0v. Analog modules not
accurate. Switch over to battery power is imminent.
[V3AOK,V3OK] = 01
010
Battery power and VDD OK. VDD>2.25v. Full digital functionality.
R
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 11
011
Battery power and VDD>2.0. Flash writes are inhibited. If the
TRIMVDD[5] fuse is blown, PLL_FAST (I/O RAM 0x2200[4]) is
cleared.
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 01
101
Battery power and VDD<2.0. When VSTAT=101, processor is
nearly out of voltage. Processor failure is imminent.
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 00
Arms the WAKE timer and loads it with WAKE_TMR[7:0]. When SLEEP or
R/W
LCD_ONLY is asserted by the MPU, the WAKE timer becomes active.
R/W Timer duration is WAKE_TMR+1 seconds.
Reset the WD timer. The WD is reset when a 1 is written to this bit. Writing a
W
one clears and restarts the watch dog timer.
DIO4 wake flag bit. If DIO4 is configured to wake the part, this bit is set
R whenever the de-bounced version of DIO4 rises. It is held in reset if DI04 is
not configured for wakeup.
DIO52 wake flag bit. If DIO52 is configured to wake the part, this bit is set
R whenever the de-bounced version of DIO52 rises. It is held in reset if DI052 is
not configured for wakeup.
DIO55 wake flag bit. If DIO55 is configured to wake the part, this bit is set
R whenever the de-bounced version of DIO55 rises. It is held in reset if DI055 is
not configured for wakeup.
R Indicates that the wake timer caused the part to wake up.
R Indicates that the PB caused the part to wake.
R Indicates that RX caused the part to wake.
R
Indicates that the Reset pin, Reset bit, ERST pin, Watchdog timer, the cold
start detector, or bad VBAT caused the part to reset.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5.3
CE Interface Description
5.3.1
CE Program
The CE performs the precision computations necessary to accurately measure energy. These computations
include offset cancellation, phase compensation, product smoothing, product summation, frequency
detection, VAR calculation, sag detection and voltage phase measurement. All data computed by the CE
is dependent on the selected meter equation as given by EQU[2:0] (I/O RAM 0x2106[7:5]).
The CE program is supplied by Teridian as a data image that can be merged with the MPU operational
code for meter applications. Typically, the CE program provided with the demonstration code covers
most applications and does not need to be modified. Other variations of CE code are available from
Teridian. The descriptions provided in this section apply to the CE code revisions shown in Table 77.
Please contact the local Teridian representative to obtain the appropriate CE code required for a specific
application.
Table 77. Standard CE Codes
Device
Local Sensors
Remote Sensor
71M6541D/F/G
CE41A01 (Eq. 0 or 1)
CE41B016601
CE41A01 (Eq. 0 or 1)
CE41B016201
CE41A04 (Eq. 2)
(Eq. 0, 1 or 2)
71M6542F/G
5.3.2
CE Data Format
All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s complement format
(-1 = 0xFFFFFFFF). Calibration parameters are defined in flash memory (or external EEPROM) and
must be copied to CE data memory by the MPU before enabling the CE. Internal variables are used in
internal CE calculations. Input variables allow the MPU to control the behavior of the CE code. Output
variables are outputs of the CE calculations. The corresponding MPU address for the most significant
byte is given by 0x0000 + 4 x CE_address and by 0x0003 + 4 x CE_address for the least significant byte.
5.3.3
Constants
Constants used in the CE Data Memory tables are:
•
•
•
•
•
•
•
•
Sampling Frequency: FS = 32768 Hz/13 = 2520.62 Hz.
F0 is the fundamental frequency of the mains phases.
IMAX is the external rms current corresponding to 250 mV pk (176.8 mV rms) at the inputs IA and IB.
IMAX needs to be adjusted if the pre-amplifier is activated for the IAP-IAN inputs. For a 250 µΩ shunt
resistor, IMAX becomes 707 A (176.8 mV rms / 250 µΩ = 707.2 A rms).
VMAX is the external rms voltage corresponding to 250 mV pk at the VA and VB inputs.
NACC, the accumulation count for energy measurements is SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0],
0x2108[7:0]).
The duration of the accumulation interval for energy measurements is SUM_SAMPS[12:0] / FS.
X is a gain constant of the pulse generators. Its value is determined by PULSE_FAST and PULSE_SLOW
(see Table 83).
Voltage LSB (for sag threshold) = VMAX * 7.879810-9 V.
The system constants IMAX and VMAX are used by the MPU to convert internal digital quantities (as
used by the CE) to external, i.e., metering quantities. Their values are determined by the scaling of the
voltage and current sensors used in an actual meter. The LSB values used in this document relate digital
quantities at the CE or MPU interface to external meter input quantities. For example, if a SAG threshold
of 80 V rms is desired at the meter input, the digital value that should be programmed into SAG_THR (CE
RAM 0x24) would be 80 Vrms * SQRT(2)/SAG_THRLSB, where SAG_THRLSB is the LSB value in the
description of SAG_THR (see Table 84).
Rev 2
125
71M6541D/F/G and 71M6542F/G Data Sheet
The parameters EQU[2:0] (I/O RAM 0x2106[7:5]), CE_E (I/O RAM 0x2106[0]), and SUM_SAMPS[12:0] are
essential to the function of the CE are stored in I/O RAM (see 5.2 I/O RAM Map – Alphabetical Order for
details).
5.3.4
Environment
Before starting the CE using the CE_E bit (I/O RAM 0x2106[0]), the MPU has to establish the proper
environment for the CE by implementing the following steps:
•
•
•
•
Locate the CE code in Flash memory using CE_LCTN[5:0] (I/O RAM 0x2109[5:0])
Load the CE data into RAM
Establish the equation to be applied in EQU[2:0] (I/O RAM 0x2106[7:5])
Establish the number of samples per accumulation period in SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0],
0x2108[7:0])
Establish the number of cycles per ADC multiplexer frame (MUX_DIV[3:0] (I/O RAM 0x2100[7:4]))
Apply proper values to MUXn_SEL, as well as proper selections for DIFFn_E (I/O RAM 0x210C[5:4])
and RMT_E (I/O RAM 0x2709[3]) in order to configure the analog inputs
Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or the power failure detection interrupt
VMAX = 600 V, IMAX = 707 A, and kH = 1 Wh/pulse are assumed as default settings
•
•
•
•
When different CE codes are used, a different set of environment parameters need to be established.
The exact values for these parameters are listed in the Application Notes and other documentation which
accompanies the CE code.
Operating CE codes with environment parameters deviating from the values specified by Teridian
leads to unpredictable results. See Table 1 and Table 2.
Typically, there are thirteen 32768 Hz cycles per ADC multiplexer frame (see 2.2.2 Input Multiplexer).
This means that the product of the number of cycles per slot and the number of conversions per frame
must be 12 (plus one settling cycle per frame, see Figure 6 and Figure 7). The default configuration is
FIR_LEN[1:0] = 01, I/O RAM 0x210C[2:1], (three cycles per conversion) and MUX_DIV[3:0] = 3 (3
conversions per multiplexer cycle).
Sample configurations can be copied from Demo Code provided by Teridian with the Demo Kits.
5.3.5
CE Calculations
Referring to Table 78, The MPU selects the desired equation by writing the EQU[2:0] (I/O RAM
0x2106[7:5]).
Table 78: CE EQU Equations and Element Input Mapping
EQU
Watt & VAR Formula
(WSUM/VARSUM)
0
VA IA – 1 element, 2W 1φ
VA*(IA-IB)/2 – 1 element, 3W 1φ
1
†
2
VA*IA + VB*IB – 2 element, 3W 3φ Delta
Note:
†
71M6542F/G only.
126
Inputs Used for Energy/Current Calculation
W0SUM/
VAR0SUM
W1SUM/
VAR1SUM
I0SQ
SUM
I1SQ
SUM
VA*IA
VA*(IA-IB)/2
VA*IA
VA*IB
–
VB*IB
IA
IA-IB
IA
IB
IB
–
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5.3.6
CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by reading addresses 0-3, 9 and 10 (decimal) shown
in Table 79.
The MUX_SEL column in Table 79 shows the MUX_SEL handles for the various sensor input pins. For
example, if differential mode is enable via control bit DIFFA_E = 1 (I/O RAM 0x210C[4]), then the inputs IAP
and IAN are combined together to form a single differential input and the corresponding MUX_SEL handle is
0. Similarly, the CE RAM location column provides the CE RAM address where the sample data is stored.
Continuing with the same example, if DIFFA_E = 1, the corresponding CE RAM location where the
samples for the IAP-IAN differential input are stored is 0 and CE RAM location is not disturbed.
The IB input can be configured as a direct-connected sensor (i.e., directly connected to the 71M654x) or as a
remote sensor (i.e., using a 71M6x01 Isolated Sensor). If the remote sensor is disabled by RMT_E = 0 and
differential mode is enabled by DIFFB_E = 1 (I/O RAM 0x210C[5]), then IBP and IBN form a differential
input with a MUX_SEL handle of 2, and the corresponding samples are stored in CE RAM location 2 (CE
RAM location 3 is not disturbed). If the remote sensor enable bit RMT_E = 1 and DIFFB_E = 0 or 1, then the
MUX_SEL handle is undefined (i.e., the sensor is not connected to the 71M654x, so MUX_SEL does not
apply, see 2.2 Analog Front End (AFE) on page 12), and the samples corresponding to this remote
differential IBP-IBN input are stored in CE RAM location 2 (CE RAM location 3 is not disturbed).
The voltage sensor inputs (VA and VB) do not have any associated configuration bits. VA has a MUX_SEL
handle value of 10, and its samples are stored in CE RAM location 10. VB has a MUX_SEL handle value of 9
and its samples are stored in CE RAM location 9.
Table 79: CE Raw Data Access Locations
ADC
Location
MUX_SEL Handle
Pin
ADC0
ADC1
IAP
IAP
ADC2
ADC3
IBP
IBN
CE RAM Location
DIFFA_E
DIFFA_E
0
1
0
1
0
0
0
0
1
1
RMT_E, DIFFB_E
RMT_E, DIFFB_E
0,0
0,1
1,0
1,1
0,0
0,1
1,0
1,1
2
2
2
–
–
2
2*
2*
3
3
There are no configuration bits for ADC9, 10
9
9
10
10
ADC9
VB†
ADC10
VA
Notes:
* Remote interface data.
†
71M6542F/G only.
5.3.7
FCE Status and Control
The CE Status Word, CESTATUS, is useful for generating early warnings to the MPU (Table 80). It contains
sag warnings for phase A and B, as well as F0, the derived clock operating at the fundamental input frequency. The MPU can read the CE status word at every CE_BUSY interrupt. Since the CE_BUSY interrupt occurs at 2520.6 Hz, it is desirable to minimize the computation required in the interrupt handler of
the MPU.
Table 80: CESTATUS Register
CE Address
0x80
Name
CESTATUS
Description
See description of CESTATUS bits in Table 81.
CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful
for generating an early power fail warning to initiate necessary data storage. CESTATUS represents the
Rev 2
127
71M6541D/F/G and 71M6542F/G Data Sheet
status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in
CESTATUS is shown in Table 81.
Table 81: CESTATUS (CE RAM 0x80) Bit Definitions
CESTATUS
bit
31:4
3
2
Not Used
F0
Not Used
1
SAG_B
0
SAG_A
Name
Description
These unused bits are always zero.
F0 is a square wave at the exact fundamental input frequency.
This unused bit is always zero.
Normally zero. Becomes one when VB remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VB rises above
SAG_THR.
Normally zero. Becomes one when VA remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VA rises above
SAG_THR.
The CE is initialized by the MPU using CECONFIG (Table 82). This register contains in packed form
SAG_CNT, FREQSEL[1:0], EXT_PULSE, PULSE_SLOW and PULSE_FAST. The CECONFIG bit definitions are
given in Table 83.
Table 82: CECONFIG Register
CE
Address
Name
Data
Description
1
0x0030DB00
See description of the CECONFIG bits in
0x00B0DB002 Table 83.
1. Default for CE41A01 (71M6541D/F/G or CE41A04 (71M6542F/G) CE code for use with local
sensors.
2. Default for CE41B016201 and CE41B016601 codes that support the 71M6x01 remote
sensors.
0x20
CECONFIG
Table 83: CECONFIG (CE RAM 0x20) Bit Definitions
CECONFIG
bit
Name
23
Reserved
0
22
EXT_TEMP
0
21
EDGE_INT
1
20
SAG_INT
1
19:8
SAG_CNT
252
(0xFC)
7:6
FREQSEL[1:0]
0
Default Description
When this bit is set, control of temperature compensation is
enabled for the 71M6x01 Isolated Sensor Interface.
When 1, the MPU controls temperature compensation via the
GAIN_ADJn registers (CE RAM 0x40-0x42), when 0, the CE is in
control.
When 1, XPULSE produces a pulse for each zero-crossing of
the mains phase selected by FREQSEL[1:0] , which can be used
to interrupt the MPU.
When 1, activates YPULSE output when a sag condition is
detected.
The number of consecutive voltage samples below SAG_THR
(CE RAM 0x24) before a sag alarm is declared. The default value
is equivalent to 100 ms.
FREQSEL[1:0] selects the phase to be used for the frequency
monitor, sag detection, and for the zero crossing counter
(MAINEDGE_X, CE RAM 0x83).
FREQ SEL[1:0]
0
0
1
*71M6542F/G only
128
0
1
X
Phase Selected
A
B*
Not allowed
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5
EXT_PULSE
1
4:2
Reserved
0
1
PULSE_FAST
0
0
PULSE_SLOW
0
When zero, causes the pulse generators to respond to internal
data (WPULSE = WSUM_X (CE RAM 0x84), VPULSE = VARSUM_X
(CE RAM 0x88)). Otherwise, the generators respond to values the
MPU places in APULSEW and APULSER (CE RAM 0x45 and 0x49).
Reserved.
When PULSE_FAST = 1, the pulse generator input is increased
16x. When PULSE_SLOW = 1, the pulse generator input is
reduced by a factor of 64. These two parameters control the
pulse gain factor X (see table below). Allowed values are either
1 or 0. Default is 0 for both (X = 6).
PULSE_FAST PULSE_SLOW
X
0
0
1.5 * 22 = 6
6
1
0
1.5 * 2 = 96
-4
0
1
1.5 * 2 = 0.09375
1
1
Do not use
The FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]) selects the phase that is utilized to generate a sag
interrupt. Thus, a SAG_INT event occurs when the selected phase has satisfied the sag event criteria as
set by the SAG_THR (CE RAM 0x24) register and the SAG_CNT field in CECONFIG (CE RAM 0x20[19:8]).
When the SAG_INT bit (CE RAM 0x20[20]) is set to 1, a sag event generates a transition on the YPULSE
output. In a two-phase system (71M6542F/G), and after a sag interrupt, the MPU should change the
FREQSEL[1:0] setting to select the other phase, if it is powered. Even though a sag interrupt is only
generated on the selected phase, both phases are simultaneously checked for sag. The presence of
power on a given phase can be sensed by directly checking the SAG_A and SAG_B bits in CESTATUS (CE
RAM 0x80[0:1]).
The EXT_TEMP bit enables temperature compensation by the MPU, when set to 1. When 0, internal (CE)
temperature compensation is enabled.
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by
the MPU if the EXT_PULSE bit = 1 (CE RAM 0x20[5]). In this case, the MPU controls the pulse rate (external
pulse generation) by placing values into APULSEW and APULSER (CE RAM 0x45 and 0x49). By setting
EXT_PULSE = 0, the CE controls the pulse rate based on WSUM_X (CE RAM 0x84) and VARSUM_X (CE
RAM 0x88).
The 71M6541D/F/G and 71M6542F/G Demo Code creep function halts both internal and external
pulse generation.
Table 84: Sag Threshold and Gain Adjust Control
CE
Address
Name
Default
7
0x24
SAG_THR
2.39*10
0x40
GAIN_ADJ0
16384
0x41
GAIN_ADJ1
16384
0x42
GAIN_ADJ2
16384
5.3.8
Rev 2
Description
The voltage threshold for sag warnings. The default value is
equivalent to 113Vpk or 80 Vrms if VMAX = 600 Vrms.
 ∙ √2
_ =
 ∙ 7.8798 ∙ 10−9
This register scales the voltage measurement channels VA and
VB*. The default value of 16384 is equivalent to unity gain (1.000).
*71M6542F/G only
This register scales the IA current channel for Phase A. The
default value of 16384 is equivalent to unity gain (1.000).
This register scales the IB current channel for Phase B. The
default value of 16384 is equivalent to unity gain (1.000).
CE Transfer Variables
129
71M6541D/F/G and 71M6542F/G Data Sheet
When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer
variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY
interrupt. They remain constant throughout each accumulation interval. In this data sheet, the names of
CE transfer variables always end with “_X”. The transfer variables can be categorized as:
•
•
•
Fundamental energy measurement variables
Instantaneous (RMS) values
Other measurement parameters
5.3.8.1 Fundamental Energy Measurement Variables
Table 85 and Table 86 describe each transfer variable for fundamental energy measurement. All
variables are signed 32-bit integers. Accumulated variables such as WSUM are internally scaled so they
have at least 2x margin before overflow when the integration time is one second. Additionally, the hardware
does not permit output values to fold back upon overflow.
Table 85: CE Transfer Variables (with Local Sensors)
CE
Address
Name
0x84†
WSUM_X
0x85
0x86
W0SUM_X
W1SUM_X
0x88†
VARSUM_X
0x89
0x8A
VAR0SUM_X
VAR1SUM_X
Description
Configuration
The signed sum: W0SUM_X+W1SUM_X. Not used
for EQU[2:0] = 0 (I/O RAM 0x2106[7:5]) and
EQU[2:0] = 1.
The sum of Wh samples from each wattmeter
element.
LSBW = 9.4045*10-13 * VMAX * IMAX Wh.
The signed sum: VAR0SUM_X+VAR1SUM_X. Not
used for EQU[2:0] = 0 and EQU[2:0] = 1.
The sum of VARh samples from each wattmeter
element.
-13
LSBW = 9.4045*10 * VMAX * IMAX VARh.
Figure 35 (page 93)
Figure 37 (page 95)
Note:
†
71M6542 only.
Table 86: CE Transfer Variables (with Remote Sensor)
CE
Address
Name
0x84†
WSUM_X
0x85
0x86
W0SUM_X
W1SUM_X
0x88†
VARSUM_X
0x89
0x8A
VAR0SUM_X
VAR1SUM_X
Description
Configuration
The signed sum: W0SUM_X+W1SUM_X. Not used
for EQU[2:0] = 0 (I/O RAM 0x2106[7:5]) and
EQU[2:0] = 1.
The sum of Wh samples from each wattmeter
element.
LSB = 1.55124*10-12 * VMAX* IMAX Wh.
The signed sum: VAR0SUM_X+VAR1SUM_X. Not
used for EQU[2:0] = 0 and EQU[2:0] = 1.
The sum of VARh samples from each wattmeter
element.
-12
LSB = 1.55124*10 *VMAX* IMAX VARh.
Figure 36 (page 94)
Figure 38 (page 96)
Note:
†
71M6542 only.
WSUM_X (CE RAM 0x84) and VARSUM_X (CE RAM 0x88) are the signed sum of Phase-A and Phase-B Wh
or VARh values according to the metering equation specified in the I/O RAM control field EQU[2:0] (I/O
RAM 0x2106[7:5]). WxSUM_X (x = 0 or 1, CE RAM 0x85 and 0x86) is the Wh value accumulated for phase x
in the last accumulation interval and can be computed based on the specified LSB value.
130
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5.3.8.2 Instantaneous Energy Measurement Variables
IxSQSUM_X and VxSQSUM (see Table 87) are the sum of the squared current and voltage samples
acquired during the last accumulation interval.
Table 87: CE Energy Measurement Variables (with Local Sensors)
CE
Address
Name
0x8C
I0SQSUM_X
0x8D
I1SQSUM_X
†
0x90
V0SQSUM_X
0x91†
V1SQSUM_X
Configuration
Description
The sum of squared current samples from each
element.
-13
2 2
LSBI = 9.4045*10 IMAX A h
When EQU = 1, I0SQSUM_X is based on IA and
IB.
The sum of squared voltage samples from each
element.
-13
2 2
LSBV= 9.4045*10 VMAX V h
Figure 35 (page 93)
Figure 37 (page 95)
71M6542 only.
Table 88: CE Energy Measurement Variables (with Remote Sensor)
CE
Address
0x8C
I0SQSUM_X
0x8D
I1SQSUM_X
†
Name
0x90
V0SQSUM_X
0x91†
V1SQSUM_X
Description
Configuration
The sum of squared current samples from each
element.
-12
2 2
LSBI = 2.55872*10 * IMAX A h
When EQU = 1, I0SQSUM_X is based on IA and
IB.
The sum of squared voltage samples from each
element.
LSBV= 9.40448*10-13 * VMAX2 V2h
Figure 36 (page 94)
Figure 38 (page 96)
71M6542 only.
The RMS values can be computed by the MPU from the squared current and voltage samples as follows:
Ix RMS =
IxSQSUM ⋅ LSBI ⋅ 3600 ⋅ FS
N ACC
VxRMS =
VxSQSUM ⋅ LSBV ⋅ 3600 ⋅ FS
N ACC
Note: NACC = SUM_SAMPS[12:0] (CE RAM 0x23).
Other Transfer variables include those available for frequency and phase measurement, and those
reflecting the count of the zero-crossings of the mains voltage and the battery voltage. These transfer
variables are listed in Table 89.
MAINEDGE_X (CE RAM 0x83) reflects the number of half-cycles accounted for in the last accumulated
interval for the AC signal of the phase specified in the FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]).
MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal.
Rev 2
131
71M6541D/F/G and 71M6542F/G Data Sheet
Table 89: Other Transfer Variables
CE
Address
Name
Description
2520.6 Hz
≈ 0.509 ⋅ 10− 6 Hz(for Local)
32
2
2520.6 Hz
LSB ≡
≈ 0.587 ⋅ 10− 6 Hz(for Remote)
232
The number of edge crossings of the selected voltage in the previous
accumulation interval. Edge crossings are either direction and are
de-bounced.
Fundamental frequency: LSB ≡
0x82
FREQ_X
0x83
MAINEDGE_X
5.3.9
Pulse Generation
Table 90 describes the CE pulse generation parameters.
The combination of the CECONFIG PULSE_SLOW and PULSE_FAST bits (CE RAM 0x20[0:1]) controls the
speed of the pulse rate. The default values of 0 and 0 maintain the original pulse rate given by the Kh
equation.
WRATE (CE RAM 0x21) controls the number of pulses that are generated per measured Wh and VARh
quantities. The lower WRATE is, the slower the pulse rate for the measured energy quantity. The metering
constant Kh is derived from WRATE as the amount of energy measured for each pulse. That is, if Kh =
1Wh/pulse, a power applied to the meter of 120 V and 30 A results in one pulse per second. If the load
is 240 V at 150 A, ten pulses per second are generated.
Control is transferred to the MPU for pulse generation if EXT_PULSE = 1 (CE RAM 0x20[5]). In this case,
the pulse rate is determined by APULSEW and APULSER (CE RAM 0x45 and 0x49). The MPU has to
load the source for pulse generation in APULSEW and APULSER to generate pulses. Irrespective of the
EXT_PULSE status, the output pulse rate controlled by APULSEW and APULSER is implemented by the CE
only. By setting EXT_PULSE = 1, the MPU is providing the source for pulse generation. If EXT_PULSE is
0, W0SUM_X (CE RAM 0x85) and VAR0SUM_X (CE RAM 0x89) are the default pulse generation sources. In
this case, creep cannot be controlled since it is an MPU function.
The maximum pulse rate is 3*FS = 7.56 kHz.
See 2.3.6.2 VPULSE and WPULSE for details on how to adjust the timing of the output pulses.
The maximum time jitter is 1/6 of the multiplexer cycle period (nominally 67 µs) and is independent of the
number of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is
67 ppm. After 10 seconds, the peak jitter is 6.7 ppm. The average jitter is always zero. If it is attempted
to drive either pulse generator faster than its maximum rate, it simply outputs at its maximum rate without
exhibiting any rollover characteristics. The actual pulse rate, using WSUM as an example, is:
RATE =
WRATE ⋅ WSUM ⋅ FS ⋅ X
Hz ,
2 46
where FS = sampling frequency (2520.6 Hz), X = Pulse speed factor derived from the CE variables
PULSE_SLOW (CE RAM 0x20[0]) and PULSE_FAST (CE RAM 0x20[1]).
132
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Table 90: CE Pulse Generation Parameters
CE
Address
Name
Default
Description
Kh =
0x21
WRATE
547
0x22
0x23
KVAR
SUM_SAMPS
6444
2520
0x45
APULSEW
0
0x46
WPULSE_CTR
0
0x47
WPULSE_FRAC
0
0x48
0x49
0x4A
WSUM_ACCUM
APULSER
VPULSE_CTR
0
0
0
0x4B
VPULSE_FRAC
0
0x4C
VSUM_ACCUM
0
Rev 2
VMAX ⋅ IMAX ⋅ K
⋅ Wh / pulse
WRATE ⋅ N ACC ⋅ X
where:
K = 66.1782 (Local Sensors)
K = 109.1587 (Remote Sensor)
NACC = SUM_SAMPS[12:0] (CE RAM 0x23)
See Table 83 for the definition of X.
The default value yields 1.0 Wh/pulse for VMAX = 600 V and
IMAX = 208 A. The maximum value for WRATE is 32,768 (215).
Scale factor for VAR measurement.
SUM_SAMPS (NACC).
Wh pulse (WPULSE) generator input to be updated by the MPU
when using external pulse generation. The output pulse rate is:
APULSEW * FS * 2-32 * WRATE * X * 2-14.
This input is buffered and can be updated by the MPU during a
conversion interval. The change takes effect at the beginning of
the next interval.
WPULSE counter.
Unsigned numerator, containing a fraction of a pulse. The value
in this register always counts up towards the next pulse.
Roll-over accumulator for WPULSE.
VARh (VPULSE) pulse generator input.
VPULSE counter.
Unsigned numerator, containing a fraction of a pulse. The value
in this register always counts up towards the next pulse.
Roll-over accumulator for VPULSE.
133
71M6541D/F/G and 71M6542F/G Data Sheet
5.3.10 Other CE Parameters
Table 91 shows the CE parameters used for suppression of noise due to scaling and truncation effects.
Table 91: CE Parameters for Noise Suppression and Code Version
CE
Address
Name
Default
Description
QUANT_VA
0x25
0
QUANT_IA
0x26
0
Compensation factors for truncation and noise in voltage, current,
real energy and reactive energy for phase A.
QUANT_A
0x27
0
QUANT_VARA
0x28
0
QUANT_VB
0x29 †
0
Compensation factors for truncation and noise in voltage, current,
QUANT_IB
0x2A
0
real energy and reactive energy for phase B.
QUANT_B
0x2B
0
†
71M6542 only.
QUANT_VARB
0x2C
0
0x38
0x43453431
CE file name identifier in ASCII format (CE41a01f). These values
0x39
0x6130316B
are overwritten as soon as the CE starts
0x3A
0x00000000
LSB weights for use with Local Sensors:
QUANT _ Ix _ LSB = 5.08656 ⋅ 10 −13 ⋅ IMAX 2 ( Amps 2 )
QUANT _ Wx _ LSB = 1.04173 ⋅ 10 −9 ⋅ VMAX ⋅ IMAX (Watts)
QUANT _ VARx _ LSB = 1.04173 ⋅ 10 −9 ⋅ VMAX ⋅ IMAX (Vars)
LSB weights for use with the 71M6x01 isolated sensors:
QUANT _ Ix _ LSB = 1.38392 ⋅ 10−12 ⋅ IMAX 2 ( Amps 2 )
QUANT _ Wx _ LSB = 1.71829 ⋅ 10−9 ⋅ VMAX ⋅ IMAX (Watts)
QUANT _ VARx _ LSB = 1.71829 ⋅ 10−9 ⋅ VMAX ⋅ IMAX (Vars)
134
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
5.3.11 CE Calibration Parameters
Table 92 lists the parameters that are typically entered to effect calibration of meter accuracy.
Table 92: CE Calibration Parameters
CE
Address
Name
Default
0x10
0x11
0x13
†
0x14
CAL_IA
CAL_VA
CAL_IB
CAL_VB
16384
16384
16384
16384
0x12
PHADJ_A
0
Description
These constants control the gain of their respective channels. The
nominal value for each parameter is 214 = 16384. The gain of each
channel is directly proportional to its CAL parameter. Thus, if the
gain of a channel is 1% slow, CAL should be increased by 1%.
Refer to the 71M6541 Demo Board User’s Manual for the equations
to calculate these calibration parameters.
†
71M6542 only.
These constants control the CT phase compensation. Compensation
does not occur when PHADJ_X = 0. As PHADJ_X is increased,
more compensation (lag) is introduced. The range is ± 215 – 1. If
it is desired to delay the current by the angle Φ, the equations are:
PHADJ _ X = 2 20
0x15
PHADJ_B
0
0.02229 ⋅ TANΦ
at 60Hz
0.1487 − 0.0131 ⋅ TANΦ
0.0155 ⋅ TANΦ
at 50Hz
0.1241 − 0.009695 ⋅ TANΦ
The shunt delay compensation is obtained using the equation
provided below:
 2πf 
 2πf
 + 2ab cos
a 2 cos 2 
2π
 fs 
 fs
DLYADJ _ X = ∆ deg rees (1 + 0.1∆ deg rees )214
360
 2πf 

c sin 
 fs 
PHADJ _ X = 2 20
0x12
DLYADJ_A
0

 + b

where:
a = 2A
b = A2 + 1
0x15
DLYADJ_B
0
 = 22 + 4 �
2
�+2

Where, f is the mains frequency and fs is the sampling frequency.
The table below provides the value of A for each current channel:
Value of A
(decimal)
Channel
Eq. 0 or 2
Eq. 1
DLYADJ_A
15811 / 214
6811 / 214
DLYADJ_B
-1384 / 214
-1384 / 214
Rev 2
135
71M6541D/F/G and 71M6542F/G Data Sheet
5.3.12 CE Flow Diagrams
Figure 44 through Figure 46 show the data flow through the CE in simplified form. Functions not shown
include delay compensation, sag detection, scaling and the processing of meter equations.
Figure 44: CE Data Flow: Multiplexer and ADC
Figure 45: CE Data Flow: Scaling, Gain Control, Intermediate Variables
136
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
SUM
Σ
W0
W1
Σ
VAR0
Σ
VAR1
Σ
W0SUM_X
MPU
W1SUM_X
VAR0SUM_X
VAR1SUM_X
SUM_SAMPS=2520
SQUARE
I0
SUM
I0SQ
I2
V0SQ
V0
V2
I1
I2
I1SQ
Σ
I0SQSUM_X
Σ
V0SQSUM_X
Σ
I1SQSUM_X
F0
Figure 46: CE Data Flow: Squaring and Summation Stages
Rev 2
137
71M6541D/F/G and 71M6542F/G Data Sheet
6
Electrical Specifications
This section provides the electrical specifications for the 71M654x. Please refer to the 71M6xxx Data
Sheet for the 71M6x01 electrical specifications, pin-out, and package mechanical data.
The devices are 100% production tested at room temperature, and performance over the full temperature
range is guaranteed by design.
6.1
Absolute Maximum Ratings
Table 93 shows the absolute maximum ratings for the device. Stresses beyond Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings only and functional operation at
these or any other conditions beyond those indicated under recommended operating conditions (see 6.3
Recommended Operating Conditions) is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability. All voltages are with respect to GNDA.
Table 93: Absolute Maximum Ratings
Voltage and Current
Supplies and Ground Pins
V3P3SYS, V3P3A
VBAT, VBAT_RTC
GNDD
Analog Output Pins
VREF
VDD
V3P3D
VLCD
Analog Input Pins
IAP-IAN, VA, IBP-IBN, VB† († 71M6542F/G
only)
XIN, XOUT
−0.5 V to 4.6 V
-0.5 V to 4.6 V
-0.1 V to +0.1 V
-10 mA to +10 mA,
-0.5 V to V3P3A+0.5 V
-10 mA to 10 mA,
-0.5 to 3.0 V
-10 mA to 10 mA,
-0.5 V to 4.6 V
-10 mA to 10 mA,
-0.5 V to 6 V
-10 mA to +10 mA
-0.5 V to V3P3A+0.5 V
-10 mA to +10 mA
-0.5 V to 3.0 V
SEG and SEGDIO Pins
Configured as SEG or COM drivers
Configured as Digital Inputs
Configured as Digital Outputs
-1 mA to 1 mA,
-0.5 V to VLCD+0.5 V
-10 mA to 10 mA,
-0.5 V to 6 V
-10 mA to 10 mA,
-0.5 V to V3P3D+0.5 V
Digital Pins
Inputs (PB, RESET, RX, ICE_E, TEST)
Outputs (TX)
Temperature and ESD Stress
Operating junction temperature (peak, 100ms)
Operating junction temperature (continuous)
Storage temperature
138
-10 mA to 10 mA,
-0.5 to 6 V
-10 mA to 10 mA,
-0.5 V to V3P3D+0.5 V
140 °C
125 °C
−45 °C to +165 °C
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Solder temperature – 10 second duration
ESD stress on all pins
6.2
+250 °C
±4 kV
Recommended External Components
Table 94: Recommended External Components
Name
C1
C2
CSYS
CVDD
From
V3P3A
V3P3D
V3P3SYS
VDD
To
GNDA
GNDD
GNDD
GNDD
CVLCD
VLCD
GNDD
XTAL
XIN
XOUT
CXS
XIN
GNDA
CXL
XOUT
GNDA
6.3
Function
Bypass capacitor for 3.3 V supply
Bypass capacitor for 3.3 V output
Bypass capacitor for V3P3SYS
Bypass capacitor for VDD
Bypass capacitor for VLCD pin (when
charge pump is used)
32.768 kHz crystal – electrically similar to
ECS .327-12.5-17X, Vishay XT26T or
Suntsu SCP6–32.768kHz TR (load
capacitance 12.5 pF).
Load capacitor values for crystal depend on
crystal specifications and board parasitics.
Nominal values are based on 4 pF board
capacitance and include an allowance for
chip capacitance.
Value
Unit
≥0.1 ±20%
0.1 ±20%
≥1.0 ±30%
0.1 ±20%
µF
µF
µF
µF
≥0.1 ±20%
µF
32.768
kHz
15 ±10%
pF
10 ±10%
pF
Recommended Operating Conditions
Unless otherwise specified, all parameters listed in 6.4 Performance Specifications and 6.5 Timing
Specifications are valid over the Recommended Operating Conditions provided in Table 95 below.
Table 95: Recommended Operating Conditions
Parameter
Condition
V3P3SYS and V3P3A Supply Voltage for
VBAT=0 V to 3.8 V
precision metering operation (MSN mode).
VBAT_RTC =0 V to
Voltages at VBAT and VBAT_RTC need
3.8 V
not be present.
VBAT Voltage (BRN mode). V3P3SYS is V3P3SYS < 2.8 V
below the 2.8 V comparator threshold.
and
Either V3P3SYS or VBAT_RTC must be
Max (VBAT_RTC,
high enough to power the RTC module.
V3P3SYS) > 2.0 V
VBAT_RTC Voltage. VBAT_RTC is not
needed to support the RTC and nonV3P3SYS<2.0 V
volatile memory unless V3P3SYS < 2.0 V
Operating Temperature
Notes:
1. GNDA and GNDD must be connected together.
2. V3P3SYS and V3P3A must be connected together.
Rev 2
Min
Typ
Max
Unit
3.0
3.6
V
2.5
3.8
V
2.0
3.8
V
-40
+85
ºC
139
71M6541D/F/G and 71M6542F/G Data Sheet
6.4
Performance Specifications
6.4.1
Input Logic Levels
Table 96: Input Logic Levels
Parameter
Condition
Min
Typ
Max
Unit
1
Digital high-level input voltage , VIH
2
1
Digital low-level input voltage , VIL
0.8
Input pullup current, IIL
E_RXTX, E_RST, E_TCLK
VIN=0 V,
10
100
OPT_RX, OPT_TX
ICE_E=3.3 V
10
100
SPI_CSZ (SEGDIO36)
10
10
Other digital inputs
-1
0
1
Input pull down current, IIH
VIN=V3P3D
ICE_E, RESET, TEST
10
100
Other digital inputs
-1
0
1
Note:
1. In battery powered modes, digital inputs should be below 0.1 V or above VBAT – 0.1 V to
minimize battery current.
6.4.2
V
V
µA
µA
µΩ
µA
µA
µA
Output Logic Levels
Table 97: Output Logic Levels
Parameter
Digital high-level output voltage
VOH
Digital low-level output voltage
VOL
Condition
ILOAD = 1 mA
ILOAD = 15 mA
(see notes 1, 2)
ILOAD = 1 mA
ILOAD = 15 mA
(see note 1)
Min
V3P3D–0.4
V3P3D-0.6
0
0
Typ
Max
Unit
V
V
0.4
0.8
V
V
Note:
1. Guaranteed by design, not production tested.
2. Caution: The sum of all pull up currents must be compatible with the on-resistance of the
internal V3P3D switch. See 6.4.6 V3P3D Switch on page 143.
140
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.3
Battery Monitor
Table 98: Battery Monitor Performance Specifications (TEMP_BAT= 1)
Parameter
BV: Battery Voltage
(definition)
Measurement Error
 BV

100 ⋅ 
− 1
 VBAT 
Input impedance in
continuous measurement,
MSN mode.
V(VBAT_RTC)/I(VBAT_RTC)
Load applied with BCURR
IBAT(BCURR=1) - IBAT(BCURR=0)
6.4.4
Condition
Min
Typ
Max
Unit
 = 3.3 + ( − 142) ∙ 0.0246 +  ∙ 297
MSN mode, TEMP_PWR = 1
V
 = 3.291 + ( − 142) ∙ 0.0255 +  ∙ 328
BRN mode,
TEMP_PWR=TEMP_BSEL
VBAT =
2.0 V
2.5 V
3.0 V
4.0 V
-7.5
-5
-3
-3
V3P3 = 3.3 V,
TEMP_BSEL = 0,
TEMP_PER = 111,
VBAT_RTC = 3.6 V,
7.5
5
3
5
1
MΩ
50
V3P3 = 3.3 V
%
100
140
µA
Temperature Monitor
Table 99. Temperature Monitor
Parameter
Condition
Min
Typ
Max
Unit
In MSN, TEMP_PWR=1:
Temperature Measurement
Equation
Temperature Error
VBAT_RTC charge per
measurement
 = 0.325 ∙  + 22
 = 0.325 ∙  + 0.00218 ∙  2 − 0.609 ∙  + 64.4
TA=+22°C
TEMP_BSEL = 0,
TEMP_PWR=0,
SLP Mode,
VBAT_RTC = 3.6 V
TEMP_PWR = 0,
Duration of temperature
TEMP_PER = 7,
measurement after setting
SLP Mode,
TEMP_START
VBAT_RTC = 3.6 V
Force V3P3D = 1.0 V
(see note 1)
Notes:
1. Guaranteed by design; not production tested.
Rev 2
°C
In BRN, TEMP_PWR = TEMP_BSEL:
-2
+2
16
15
°C
µC
60
ms
141
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.5
Supply Current
The supply currents provided in Table 100 below include only the current consumed by the 71M654x.
Refer to the 71M6xxx Data Sheet for additional current required when using a 71M6x01 remote sensor.
Table 100: Supply Current Performance Specifications
Parameter
Condition
I1:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
Single-phase: 2 Currents, 1 Voltage
V3P3A = V3P3SYS = 3.3 V,
MPU_DIV [2:0]= 3 (614 kHz MPU clock),
No Flash memory write,
RTM_E=0, PRE_E=0, CE_E=1, ADC_E=1,
ADC_DIV=1, MUX_DIV[3:0]=3,
FIR_LEN[1:0]=1, PLL_FAST=1
I1a:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
I1b:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
I1c:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
I2:
V3P3A + V3P3SYS dynamic
current
Min
Typ
Max
Unit
5.5
6.7
mA
2.6
3.5
mA
Same as I1, except PRE_E = 1
5.7
6.9
mA
Same as I1, except PLL_FAST = 0 and
PRE_E = 1
2.6
3.6
mA
0.4
0.6
mA/
MHz
0
2.4
0.4
24
3.0
1.1
0
300
3.2
108
36
11
3.4
+300
nA
mA
nA
µA
µA
µA
nA
0
240
1.8
0.7
1.5
300
320
4.1
1.7
3.2
nA
nA
µA
µA
µA
7.1
8.7
mA
Same as I1, except PLL_FAST=0
Same as I1, except with variation of
MPU_DIV[2:0].
I MPU_DIV = 0 - I MPU_DIV = 3
4.3
VBAT current
I3: MSN Mode
I4: BRN Mode
I5: LCD Mode (ext. VLCD)
Note 1
I6: LCD Mode (boost, DAC)
Note 1
I7: LCD Mode (DAC)
I8: LCD Mode (VBAT)Note 1
I9: SLP Mode
-300
CE_E=0
LCD_VMODE[1:0]=3, also see note 2
LCD_VMODE[1:0]=2, also see note 3
LCD_VMODE[1:0]=1, also see note 3
LCD_VMODE[1:0]=0, also see note 3
SLP Mode
-300
VBAT_RTC current
I10: MSN
I11: BRN
I12: LCD Mode
I13: SLP Mode
I14: SLP Mode (see note 1)
I15:
V3P3A + V3P3SYS current,
Write Flash with ICE
-300
LCD_VMODE[1:0]=2, also see note 2
TA ≤ 25 °C
TA = 85 °C
Same as I1, except write Flash at maximum rate,
CE_E=0, ADC_E=0.
Notes:
1.
2.
3.
142
Guaranteed by design; not production tested.
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 1, LCD_BLANK=0,
LCD_ON=1.
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 0.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.6
V3P3D Switch
Table 101: V3P3D Switch Performance Specifications
Parameter
On resistance – V3P3SYS to V3P3D
On resistance – VBAT to V3P3D
V3P3D IOH, MSN
V3P3D IOH, BRN
6.4.7
Condition
| IV3P3D | ≤ 1 mA
| IV3P3D | ≤ 1 mA,
VBAT>2.5V
V3P3SYS = 3V
V3P3D = 2.9V
VBAT = 2.6V
V3P3D = 2.5V
Min
Typ
Max
10
Unit
Ω
10
Ω
10
mA
10
mA
Internal Power Fault Comparators
Table 102. Internal Power Fault Comparator Specifications
Parameter
Condition
Overall response time
100mV overdrive, falling
100mV overdrive, rising
Falling Threshold
3.0 V Comparator
2.8 V Comparator
Difference 3.0V and 2.8V Comparators
Falling Threshold
2.25 V Comparator
2.0 V Comparator
VDD (@VBAT=3.0V) – 2.25V Comparator
Difference 2.25V and 2.0V Comparators
Hysteresis,
(Rising Threshold - Falling Threshold)
3.0 V Comparator
2.8 V Comparator
2.25 V Comparator
2.0 V Comparator
6.4.8
Min
Typ
20
Max
Unit
200
200
µs
µs
V3P3 falling
2.83
2.75
50
2.93
2.81
136
3.03
2.87
220
V
V
mV
2.2
1.90
0.25
0.15
2.25
2.00
0.35
0.25
2.5
2.20
0.45
0.35
V
V
V
V
22
25
10
10
45
42
33
28
65
60
60
60
mV
mV
mV
mV
VDD falling
TA = 22 °C
2.5 V Voltage Regulator – System Power
Table 103: 2.5 V Voltage Regulator Performance Specifications
Parameter
V2P5
V2P5 load regulation
Voltage overhead V3P3SYS-V2P5
Rev 2
Condition
V3P3 = 3.0 V - 3.8 V
ILOAD = 0 mA
VBAT = 3.3 V , V3P3 = 0 V
ILOAD = 0 mA to 1 mA
ILOAD = 5 mA,
Reduce V3P3D until V2P5
drops 200 mV
Min
Typ
Max
Unit
2.55
2.65
2.75
V
40
mV
440
mV
143
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.9
2.5 V Voltage Regulator – Battery Power
Unless otherwise specified, V3P3SYS = V3P3A = 0, PB=GND (BRN).
Table 104: Low-Power Voltage Regulator Performance Specifications
Parameter
Condition
VBAT = 3.0 V - 3.8 V,
V3P3 = 0 V, ILOAD = 0 mA
VBAT = 3.3 V, V3P3 = 0 V,
ILOAD = 0 mA to 1 mA
ILOAD = 0ma, VBAT = 2.0 V,
V3P3 = 0 V.
V2P5
V2P5 load regulation
Voltage Overhead 2V − VBAT-VDD
Min
Typ
Max
Unit
2.55
2.65
2.75
V
40
mV
200
mV
6.4.10 Crystal Oscillator
Measurement conditions: Crystal disconnected, test load of 200 pF/100 kΩ between XOUT and GNDD.
Table 105: Crystal Oscillator Performance Specifications
Parameter
Condition
Maximum Output Power to Crystal
XIN to XOUT Capacitance
(see note 1)
Crystal connected, see note 1
Capacitance change on XOUT
Min
RTC_ADJ = 7F to 0,
Bias voltage = unbiased
Vpp = 0.1 V
Typ
Max
Unit
1
μW
3
pF
15
pF
Notes:
1. Guaranteed by design; not production tested.
6.4.11 Phase-Locked Loop (PLL)
Table 106: PLL Performance Specifications
Parameter
PLL Power up Settling Time
(see note 1)
PLL_FAST settling time
PLL_FAST rise (see note 1)
PLL_FAST fall (see note 1)
PLL SLP to MSN Settling Time
(see note 2)
PLL power up overshoot
(see note 1)
Condition
PLL_FAST = 0, V3P3 = 0 V to 3.3 V
step, measured from first edge of
MCK
V3P3 = 0 V, VBAT = 3.8 V to 2.0 V
Min
Typ
Max
Unit
5
ms
5
5
ms
ms
PLL_FAST = 0
5
ms
PLL_FAST = 0
2.5
MHz
Notes:
1. Guaranteed by design; not production tested.
144
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.12 LCD Drivers
Table 107: LCD Driver Performance Specifications
PARAMETER
VLCD Current
(see Notes 1 to 4)
Notes:
1.
2.
3.
4.
Rev 2
CONDITION
MIN
TYP
VLCD=3.3, all LCD map bits=0
VLCD=5.0, all LCD map bits=0
MAX
2
3
UNIT
uA
uA
These specifications apply to all COM and SEG pins.
VLCD = 2.5 V to 5 V.
LCD_VMODE=3, LCD_ON=1, LCD_BLANK=0, LCD_MODE=6, LCD_CLK=2.
Output load is 74 pF per SEG and COM pin.
145
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.13 VLCD Generator
1
Table 108: LCD Driver Performance Specifications
Parameter
VSYS to VLCD switch impedance
VBAT to VLCD switch impedance
LCD Boost Frequency
VLCD IOH current
(VLCD(0)-VLCD(IOH)<0.25)
Condition
V3P3 = 3.3 V,
RVLCD=removed, LCD_BAT=0,
LCD_VMODE[1:0]=0,
∆ILCD=10 µA
V3P3 = 0 V, VBAT = 2.5 V,
RVLCD =removed, LCD_BAT =1,
LCD_VMODE[1:0]=0,
∆ILCD=10 µA
LCD_VMODE[1:0] = 2,
RVLCD = removed,
CVLCD = removed
PLL_FAST=1
PLL_FAST=0
LCD_VMODE[1:0] = 2,
LCD_CLK[1:0] = 2,
RVLCD = removed,
V3P3 = 3.3V,
LCD_DAC[4:0] = 1F
Min
Typ
Max
Unit
750
Ω
700
Ω
820
786
kHz
kHz
10
µA
From LCDADJ0 and LCDADJ12 fuses:
12 − 0
(_) = 5 �0 +
_�
12
_
 (_) = 2.65 + 2.65
+ (_)
31
The above equations describe the nominal value of VLCD for a specific LCD_DAC value. The
specifications below list the maximum deviation between actual VLCD and VLCDnom. Note that when
VCC and boost are insufficient, the LCD DAC will not reach its target value and a large negative error
will occur.
LCD_DAC Error. VLCD-VLCDnom
(see note 2)
Full Scale, with Boost
V3P3 =3.6 V
V3P3 =3.0 V
VBAT=4.0 V, V3P3=0, BRN Mode
VBAT=2.5 V, V3P3=0, BRN Mode
LCD_DAC Error. VLCD-VLCDnom
DAC=12, with Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 2.5 V, V3P3 = 0 V, BRN Mode
LCD_DAC Error. VLCD-VLCDnom
Zero Scale, with Boost
V3P3 = 3.6 V
V3P3 = 3.0 V
VBAT = 4.0 V, V3P3 = 0 V, BRN Mode
(see note 2)
VBAT = 2.5 V, V3P3 = 0 V, BRN Mode
LCD_DAC Error. VLCD-VLCDnom
Full Scale, no Boost
V3P3 = 3.6 V (see note 2)
V3P3 = 3.0 V (see note 2)
VBAT = 4.0 V, V3P3 = 0 V, BRN Mode
VBAT = 2.5 V, V3P3 = 0 V, BRN Mode
146
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] = C,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] =0,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
LCD_VMODE[1:0] = 1,
LCD_DAC[4:0] = 1F,
LCD_CLK[1:0]=2,
LCD_MODE[2:0]=6
-0.15
-0.4
-0.15
-1.3
0.15
0.15
0.15
V
V
V
V
-0.15
-0.15
-0.15
0.15
0.15
0.15
V
V
V
-0.15
-0.15
-0.15
0.15
0.15
0.15
V
V
V
-0.15
0.15
V
-2.1
-2.8
-1.8
-3.2
V
V
V
V
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Parameter
Condition
Min
Typ
Max
Unit
LCD_DAC Error. VLCD-VLCDnom
LCD_VMODE[1:0] = 1,
LCD_DAC[4:0] = C,
DAC=12, no Boost
-0.5
V
LCD_CLK[1:0]=2,
V3P3 = 3.6 V
-1.1
LCD_MODE[2:0]=6
V
V3P3 = 3.0 V
2
2
-0.15
0.15
V
VBAT = 4.0 V, V3P3 = 0 V, BRN Mode
2
-1.5
V
VBAT = 2.5 V, V3P3 = 0 V, BRN Mode
LCD_DAC Error. VLCD-VLCDnom
LCD_VMODE[1:0] = 1,
LCD_DAC[4:0] = 0,
Zero Scale, no Boost
LCD_CLK[1:0]=2,
-0.15
0.15
V
V3P3 = 3.6 V
LCD_MODE[2:0]=6
-0.15
0.15
V
V3P3 = 3.0 V
-0.15
0.15
V
VBAT = 4.0 V, V3P3 = 0 V, BRN Mode
-0.45
0.15
V
VBAT = 2.5 V, V3P3 = 0 V, BRN Mode
LCD_DAC Error. VLCD-VLCDnom
LCD_VMODE[1:0] = 2,
LCD_DAC[4:0] = 1F,
Full Scale, with Boost, LCD mode
-0.15
0.15
V
LCD_CLK[1:0]=2,
VBAT = 4.0 V, V3P3 = 0 V
-1.3
LCD_MODE[2:0]=6
V
VBAT = 2.5 V, V3P3 = 0 V
Notes:
1. The following test conditions also apply to all parameters provided in this table: bypass capacitor CVLCD ≥
0.1 µF, test load RVLCD = 500 kΩ, no display, all SEGDIO pins configured as DIO.
2. Guaranteed by design; not production tested.
Rev 2
147
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.14 VREF
Table 109 shows the performance specifications for the ADC reference voltage (VREF).
Table 109: VREF Performance Specifications
Parameter
VREF output voltage,
VREF(22)
VREF output voltage,
VREF(22)
Condition
TA = 22 ºC
VREF power supply sensitivity
ΔVREF / ΔV3P3A
V3P3A = 3.0 to 3.6 V
VNOM definition (see note 2)
VNOM temperature
coefficients:
TC1 =
TC2 =
Max
Unit
1.193
1.195
1.197
V
1.195
VREF_CAL = 1,
ILOAD = 10 µA, -10 µA
VREF chop step, trimmed
Typ
PLL_FAST=0
VREF output impedance
VREF input impedance
Min
VREF_DIS = 1,
VREF = 1.3 V to 1.7 V
VREF(CHOP=01) −
VREF(CHOP=10)
-1.5
V
3.2
kΩ
1.5
mV/V
kΩ
100
-10
0
10
VNOM (T ) = VREF (22) + (T − 22)TC1 + (T − 22) 2 TC 2
275 − 4.95 ⋅ TRIMT
mV
V
µV/°C
µV/°C2
−0.557 + 0.00028 ⋅ TRIMT
VREF(T) deviation from
VNOM(T) (see note 1):
VREF (T ) − VNOM (T ) 106
VNOM (T )
62
VREF aging
-40
+40
±25
ppm/°C
ppm/
year
Notes:
1.
2.
3.
148
Guaranteed by design; not production tested.
This relationship describes the nominal behavior of VREF at different temperatures, as governed by a
st
nd
second order polynomial of 1 and 2 order coefficients TC1 and TC2.
For the parameters in this table, unless otherwise specified, VREF_DIS = 0, PLL_FAST=1.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.4.15 ADC Converter
Table 110. ADC Converter Performance Specifications
Parameter
Condition
Recommended Input Range
(Vin - V3P3A)
Voltage to Current Crosstalk
6
10 *Vcrosstalk
cos(∠Vin − ∠Vcrosstalk )
Vin
(see note 1)
Input Impedance, no pre-amp
ADC Gain Error vs %Power Supply
Variation
10 6 ∆Nout PK 357 nV / VIN
100 ∆V 3P3 A / 3.3
Input Offset
IADC0=IADC1=V3P3A
IADC0=V3P3A
THD @ 250mVpk
Name
FIR_LEN
A
B
C
D
E
F
G
H
J
ADC_DIV
0
1
0
1
2
0
0
1
2
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
FIR_LEN
A
B
C
D
E
F
G
H
J
ADC_DIV
0
1
0
1
2
0
0
1
2
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
Typ
Max
Unit
-250
250
mV
peak
-10
10
μV/V
40
90
kΩ
50
ppm / %
10
10
mV
mV
Vin=200 mV pk, 65 Hz
V3P3A=3.0 V, 3.6 V
DIFF0_E=1, PRE_E=0
DIFF0_E=0, PRE_E=0
THD @ 20mVpk
Name
Vin = 200 mV peak,
65 Hz, on VADC10 (VA)
or VADC9 (VB)†
†71M6542F/G only.
Vcrosstalk = largest
measurement on IAP-IAN
or IBP-IBN
Vin=65 Hz
Min
VIN = 65Hz, 250mVpk,
64kpts FFT, Blackman Harris
Window.
VIN = 65Hz, 20mVpk,
64kpts FFT, Blackman Harris
Window.
-10
-10
A
B
C
D
E
F
G
H
J
-82
-84
-83
-86
A
B
C
D
E
F
G
H
J
-75
-75
-75
-75
-75
-75
-75
-75
-75
dB
A
B
C
D
E
F
G
H
J
-85
-91
-85
-91
-93
-85
-85
-91
-93
dB
A
B
C
D
E
F
G
H
J
3470
406
3040
357
151
3470
3040
357
151
nV
LSB Size:
Name
A
B
C
D
E
F
G
H
J
FIR_LEN
ADC_DIV
0
1
0
1
2
0
0
1
2
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
Digital Full-Scale:
Name
A
B
C
D
E
F
G
H
J
Rev 2
FIR_LEN
0
1
0
1
2
0
0
1
2
ADC_DIV
0
0
0
0
0
1
1
1
1
PLL_FAST
0
0
1
1
1
0
1
1
1
MUX_DIV
3
2
11
6
4
2
6
3
2
Vin=65Hz, 20mVpk,
64kpts FFT, BlackmanHarris window
A: ±91125
B: ±778688
C: ±103823
D: ±884736
E: ±2097152
F: ±91125
G: ±103823
H: ±884736
J: ±2097152
LSB
149
71M6541D/F/G and 71M6542F/G Data Sheet
Notes:
1. Guaranteed by design; not production tested.
2. Unless stated otherwise, the following test conditions apply to all the parameters provided in
this table: FIR_LEN[1:0]=1, VREF_DIS=0, PLL_FAST=1, ADC_DIV=0, MUX_DIV=6, LSB values
do not include the 9-bit left shift at CE input.
6.4.16 Pre-Amplifier for IAP-IAN
Table 111: Pre-Amplifier Performance Specifications
PARAMETER
Differential Gain
Vin=30mV differential
Vin=15mV differential (see note 1)
Gain Variation vs V3P3
Vin=30mV differential (see note 1)
Gain Variation vs Temp
Vin=30mV differential (see note 1)
Phase Shift,
Vin=30mV differential (see note 1)
Preamp input current
IADC0
IADC1
Preamp+ADC THD
Vin=30mV differential
Vin=15mV differential
CONDITION
TA= +25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz sample rate
V3P3 =
2.97 V, 3.63 V
TA = -40⁰C, 85⁰C
TA=25⁰C,
V3P3=3.3 V
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1
2520Hz sample rate,
IADC0=IADC1=V3P3
TA=25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz sample rate.
TA=25⁰C,
V3P3=3.3 V,
PRE_E=1,
FIR_LEN=2,
DIFF0_E=1,
2520Hz sample rate
Preamp Offset
IADC0=IADC1=V3P3+30mV
IADC0=IADC1= V3P3+15mV
IADC0=IADC1= V3P3
IADC0=IADC1= V3P3-15mV
IADC0=IADC1= V3P3-30mV
Notes:
1. Guaranteed by design; not production tested.
150
MIN
TYP
MAX
UNIT
7.8
7.8
7.92
7.92
8.0
8.0
V/V
V/V
100
ppm/%
-80
ppm/C
6
mº
16
16
uA
uA
-100
10
-25
-6
4
4
9
9
-82
-86
dB
dB
-0.63
-0.57
-0.56
-0.56
-0.55
mV
mV
mV
mV
mV
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.5
Timing Specifications
6.5.1
Flash Memory
Table 112: Flash Memory Timing Specifications
Parameter
Condition
Flash write cycles
Flash data retention
-40 °C to +85 °C
25 °C
85 °C
Min
Typ
Max
20,000
100
10
Cycles
Years
Flash byte writes between page or
mass erase operations
Write Time per Byte
Page Erase (1024 bytes)
Mass Erase
6.5.2
Unit
2
Cycles
21
21
21
µs
ms
Ms
SPI Slave
Table 113. SPI Slave Timing Specifications
Parameter
SPI Setup Time
SPI Hold Time
SPI Output Delay
SPI Recovery Time
SPI Removal Time
SPI Clock High
SPI Clock Low
SPI Clock Freq
SPI Transaction Space
6.5.3
Condition
SPI_DI to SPI_CK rise
SPI_CK rise to SPI_DI
SPI_CK fall to SPI_D0
SPI_CSZ fall to SPI_CK
SPI_CK to SPI_CSZ rise
SPI Freq/MPU Freq
SPI_CSZ rise to SPI_CSZ fall
Min
10
10
Typ
Max
40
10
15
40
40
2.0
4.5
Unit
ns
ns
ns
ns
ns
ns
ns
MHz/MHz
MPU Cycles
EEPROM Interface
Table 114: EEPROM Interface Timing
Parameter
Condition
2
Write Clock frequency (I C)
Write Clock frequency (3-wire)
Rev 2
CKMPU = 4.9 MHz,
Using interrupts
CKMPU = 4.9 MHz,
bit-banging DIO2/3
PLL_FAST = 0
CKMPU = 4.9 MHz
PLL_FAST = 0
PLL_FAST = 1
Min
Typ
Max
Unit
310
kHz
100
kHz
160
500
kHz
151
71M6541D/F/G and 71M6542F/G Data Sheet
6.5.4
RESET Pin
Table 115: RESET Pin Timing
Parameter
Condition
Reset pulse width
Reset pulse fall time (see note 1)
Notes:
1. Guaranteed by design; not production tested.
6.5.5
Min
Typ
Max
Unit
1
µs
µs
5
RTC
Table 116: RTC Range for Date
Parameter
Range for date
152
Condition
Min
Typ
Max
Unit
2000
-
2255
Year
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.6
Package Outline Drawings
6.6.1
64-Pin LQFP Outline Package Drawing
11.7
12.3
11.7
+
12.3
PIN No. 1 Indicator
9.8
10.2
0.50 Typ.
0.60 Typ.
0.00
0.20
0.14
0.28
1.40
1.60
Figure 47: 64-pin LQFP Package Outline
Rev 2
153
71M6541D/F/G and 71M6542F/G Data Sheet
6.6.2
100-Pin LQFP Package Outline Drawing
Controlling dimensions are in mm.
15.7(0.618)
16.3(0.641)
1
15.7(0.618)
16.3(0.641)
Top View
14.000 +/- 0.200
MAX. 1.600
1.50 +/- 0.10
0.225 +/- 0.045
0.50 TYP.
0.10 +/- 0.10
0.60 TYP>
Side View
Figure 48: 100-pin LQFP Package Outline
154
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Package Markings
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
71M6541DIGT.428AB
104224TH
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
71M6542G-IGT
110124TK
445AP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
6.7
Figure 49. Package Markings (Examples)
Figure 49 provides an example of the package markings for the 64-pin and 100-pin packages. Package
markings comprise three lines of text and are as described in Table 117 and Table 118 below.
Line No.
Table 117. 71M6541 Package Markings
Markings
Description
1
71M6541D-
2
IGT.428AB
3
104224TH
Part number (‘IGT’ wraps to the next line)
Refer to Table 122.
The five characters to the right of the dot
(i.e., 428AB) are the lot code.
The first four digits to the left are the year
and week of manufacture as YYWW. In
this example, the date code is 1042 which
represents year 2010, week 42.
The last four characters (i.e., 24TH) are
reserved for Maxim internal use only.
Line No.
1
2
Table 118. 71M6542 Package Markings
Markings
Description
71M6542G-IGT
110124TK
Part number. Refer to Table 122.
The first four digits to the left are the year
and week of manufacture as YYWW. In
this example, the date code is 1101 which
represents year 2011, week 1.
The last four characters (i.e., 24TK) are
reserved for Maxim internal use only.
3
Rev 2
445AP
A five character lot code.
155
71M6541D/F/G and 71M6542F/G Data Sheet
Pinout Diagrams
6.8.1
71M6541D/F/G LQFP-64 Package Pinout
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SPI_CKI/SEGDIO39
SEGDIO44
SEGDIO45
TMUX2OUT/SEG46
TMUXOUT/SEG47
RESET
PB
VLCD
VREF
IAP
IAN
V3P3A
VA
TEST
GNDA
XOUT
6.8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Teridian
71M6541D
71M6541F
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
XIN
VBAT_RTC
VBAT
V3P3SYS
IBP
IBN
GNDD
V3P3D
VDD
ICE_E
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
RX
TX
OPT_TX/SEGDIO51
SEGDIO14
SEGDIO13
SEGDIO12
SEGDIO11
SEGDIO10
SEGDIO9
SEGDIO8/DI
SEGDIO7/YPULSE
SEGDIO6/XPULSE
SEGDIO5
SEGDIO4
SEGDIO3/SDATA
SEGDIO2/SDCK
SEGDIO1/VPULSE
SEGDIO0/WPULSE
OPT_RX/SEGDIO55
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SPI_DI/SEGDIO38
SPI_DO/SEGDIO37
SPI_CSZ/SEGDIO36
COM0
COM1
COM2
COM3
SEGDIO27/COM4
SEGDIO26/COM5
SEGDIO25
SEGDIO24
SEGDIO23
SEGDIO22
SEGDIO21
SEGDIO20
SEGDIO19
Figure 50: Pinout for the 71M6541D/F/G (LQFP-64 Package)
156
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
71M6542F/G LQFP-100 Package Pinout
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SPI_CKI/SEGDIO39
SEGDIO40
SEGDIO41
SEGDIO42
SEGDIO43
SEGDIO44
SEGDIO45
TMUX2OUT/SEG46
TMUXOUT/SEG47
RESET
PB
VLCD
VREF
IAP
IAN
V3P3A
NC
VB
VA
TEST
GNDA
NC
NC
NC
XOUT
6.8.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Teridian
71M6542F
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
XIN
NC
NC
GNDA
VBAT_RTC
VBAT
V3P3SYS
IBP
IBN
NC
NC
NC
NC
GNDD
V3P3D
VDD
ICE_E
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
RX
TX
OPT_TX/SEGDIO51
SEGDIO52
SEGDIO53
NC
SEGDIO17
SEGDIO16
SEGDIO15
SEGDIO14
SEGDIO13
SEGDIO12
SEGDIO11
SEGDIO10
SEGDIO9
SEGDIO8/DI
SEGDIO7/YPULSE
SEGDIO6/XPULSE
SEGDIO5
NC
SEGDIO4
SEGDIO3/SDATA
SEGDIO2/SDCK
SEGDIO1/VPULSE
SEGDIO0/WPULSE
OPT_RX/SEGDIO55
SEGDIO54
NC
NC
NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SPI_DI/SEGDIO38
SPI_DO/SEGDIO37
SPI_CSZ/SEGDIO36
SEGDIO35
SEGDIO34
SEGDIO33
SEGDIO32
SEGDIO31
SEGDIO30
SEGDIO29
SEGDIO28
COM0
COM1
COM2
COM3
SEGDIO27/COM4
SEGDIO26/COM5
SEGDIO25
SEGDIO24
SEGDIO23
SEGDIO22
SEGDIO21
SEGDIO20
SEGDIO19
SEGDIO18
Figure 51: Pinout for the 71M6542F/G (LQFP-100 Package)
Rev 2
157
71M6541D/F/G and 71M6542F/G Data Sheet
6.9
Pin Descriptions
6.9.1
Power and Ground Pins
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output.
The circuit number denotes the equivalent circuit, as specified under 6.9.4 I/O Equivalent Circuits.
.
Table 119: Power and Ground Pins
Pin
Pin
(64 pin)
(100-pin)
50
Name
Type
Circuit
72, 80
GNDA
P
–
42
62
GNDD
P
–
53
85
V3P3A
P
–
45
69
V3P3SYS
P
–
41
61
V3P3D
O
13
40
60
VDD
O
–
57
89
VLCD
O
–
46
70
VBAT
P
12
47
71
VBAT_RTC
P
12
158
Description
Analog ground: This pin should be connected directly to
the ground plane.
Digital ground: This pin should be connected directly to
the ground plane.
Analog power supply: A 3.3 V power supply should be
connected to this pin. V3P3A must be the same
voltage as V3P3SYS.
System 3.3 V supply. This pin should be connected to a
3.3 V power supply.
Auxiliary voltage output of the chip. In mission mode,
this pin is connected to V3P3SYS by the internal
selection switch. In BRN mode, it is internally
connected to VBAT. V3P3D is floating in LCD and
sleep mode. A 0.1 µF bypass capacitor to ground
must be connected to this pin.
The output of the 2.5V regulator. This pin is powered
in MSN and BRN modes. A 0.1 µF bypass capacitor to
ground should be connected to this pin.
The output of the LCD DAC. A 0.1 µF bypass
capacitor to ground should be connected to this pin.
Battery backup pin to support the battery modes (BRN,
LCD). A battery or super-capacitor is to be connected
between VBAT and GNDD. If no battery is used,
connect VBAT to V3P3SYS.
RTC and oscillator power supply. A battery or supercapacitor is to be connected between VBAT and
GNDD. If no battery is used, connect VBAT_RTC to
V3P3SYS.
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
6.9.2
Analog Pins
Table 120: Analog Pins
†
Pin
Pin
(64 pin)
(100-pin)
Name
55
54
87
86
IAPIAN
44
43
68
67
IBPIBN
52
--
82
83
56
48
49
Type
Circuit
I
6
VA
†
VB
I
6
88
VREF
O
9
75
76
XIN
XOUT
I
O
8
Description
Differential or single-ended Line Current Sense Inputs:
These pins are voltage inputs to the internal A/D
converter. Typically, they are connected to the outputs
of current sensors. Unused pins must be tied to
V3P3A.
Pins IBP-IBN may be configured for communication with
the remote sensor interface (71M6x01). When RMT_E =
1 (I/O RAM 0x2709[3]), the IBP-IBN pins become
balanced differential pair. If unused, RMT_E must be
zero and IBP-IBN must tied to V3P3A.
Line Voltage Sense Inputs: These pins are voltage
inputs to the internal A/D converter. Typically, they are
connected to the outputs of resistor dividers. Unused
pins must be tied to V3P3A.
Voltage Reference for the ADC. This pin should be left
unconnected (floating).
Crystal Inputs: A 32 kHz crystal should be connected
across these pins. Typically, a 15 pF capacitor is also
connected from XIN to GNDA and a
10 pF capacitor is connected from XOUT to GNDA. It
is important to minimize the capacitance between these
pins. See the crystal manufacturer datasheet for details.
If an external clock is used, a 150 mV (p-p) clock signal
should be applied to XIN, and XOUT should be left
unconnected.
Pin VB only available on 71M6542F/G.
Rev 2
159
71M6541D/F/G and 71M6542F/G Data Sheet
6.9.3
Digital Pins
Table 121 lists the digital pins. Pin types: P = Power, O = Output, I = Input, I/O = Input/Output, N/C = no
connect. The circuit number denotes the equivalent circuit, as specified in 6.9.4 I/O Equivalent Circuits.
Table 121: Digital Pins
Pin
(64-pin)
Pin
(100-pin)
Name
Type
Circuit
4-7
12–15
COM0–COM3
O
5
31
45
SEGDIO0/WPULSE
30
44
SEGDIO1/VPULSE
29
43
SEGDIO2/SDCK
28
42
SEGDIO3/SDATA
27
41
SEGDIO4
26
39
SEGDIO5
25
38
SEGDIO6/XPULSE
24
37
SEGDIO7/YPULSE
23
36
SEGDIO8/DI
22-17
35–30
SEGDIO[9:14]
--
29-27
SEGDIO[15:17]
--
25
SEGDIO[18]
16-10
24–18
SEGDIO[19:25]
--
11–4
SEGDIO[28:35]
63-62
95-94
SEGDIO[44:45]
--
99–96
SEGDIO[40:43]
--
52
SEGDIO52
--
51
SEGDIO53
--
47
SEGDIO54
9
17
SEGDIO26/COM5
8
16
SEGDIO27/COM4
3
3
SPI_CSZ/SEGDIO36
2
2
SPI_DO/SEGDIO37
1
1
SPI_DI/SEGDIO38
64
100
SPI_CKI/SEGDIO39
33
53
OPT_TX/SEGDIO51
32
46
38
36
37
58
56
57
OPT_RX/SEGDIO55
E_RXTX/SEG48
E_RST/SEG50
E_TCLK/SEG49
160
I/O
3, 4, 5
Function
LCD Common Outputs. These four pins provide the select
signals for the LCD display.
Multiple-Use Pins. Configurable as either LCD segment
driver or DIO. Alternative functions with proper selection of
associated I/O RAM registers are:
SEGDIO0 = WPULSE
SEGDIO1 = VPULSE
SEGDIO2 = SDCK
SEGDIO3 = SDATA
SEGDIO6 = XPULSE
SEGDIO7 = YPULSE
SEGDIO8 = DI
Unused pins must be configured as outputs or
terminated to V3P3/GNDD.
I/O
3, 4, 5
Multiple-Use Pins. Configurable as either LCD segment
driver or DIO with alternative function (LCD common
drivers).
I/O
3, 4, 5
Multiple-Use Pins. Configurable as either LCD segment
driver or DIO with alternative function (SPI interface).
I/O
3, 4, 5
Multiple-Use Pins, configurable as either LCD segment
driver or DIO with alternative function (optical port/UART1)
I/O
1, 4, 5
O
4, 5
Multiuse Pins. Configurable as either emulator port pins
(when ICE_E pulled high) or LCD segment drivers (when
ICE_E tied to GND).
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Pin
(64-pin)
Pin
(100-pin)
Name
39
59
ICE_E
60
92
TMUXOUT/SEG47
61
93
TMUX2OUT/SEG46
Type
Circuit
I
2
ICE Enable. When zero, E_RST, E_TCLK, and E_RXTX
become SEG50, SEG49, and SEG48 respectively. For
production units, this pin should be pulled to GND to disable
the emulator port.
O
4, 5
Multiple-Use Pins. Configurable as either multiplexer/clock
output or LCD segment driver using the I/O RAM registers.
59
91
RESET
I
2
35
55
RX
I
3
34
54
TX
O
4
51
81
TEST
I
7
58
90
PB
I
3
--
26, 40,
48, 49,
50, 63,
64, 65,
66, 73,
74, 77,
78, 79,
84
NC
N/C
—
Rev 2
Function
Chip Reset. This input pin is used to reset the chip into a
known state. For normal operation, this pin is pulled low. To
reset the chip, this pin should be pulled high. This pin has
an internal 30 μA (nominal) current source pulldown. No
external reset circuitry is necessary.
UART0 Input. If this pin is unused it must be terminated
to V3P3D or GNDD.
UART0 Output
Enables Production Test. This pin must be grounded in
normal operation.
Pushbutton Input. This pin must be at GNDD when not active
or unused. A rising edge sets the WF_PB flag. It also
causes the part to wake up if it is in SLP or LCD mode. PB
does not have an internal pullup or pulldown resistor.
No Connection. Do not connect this pin.
161
71M6541D/F/G and 71M6542F/G Data Sheet
6.9.4
I/O Equivalent Circuits
V3P3D
V3P3A
V3P3D
110K
Digital
Input
Pin
CMOS
Input
from
internal
reference
LCD SEG
Output
Pin
LCD
Driver
VREF
Pin
GNDD
GNDA
GNDD
LCD Output Equivalent Circuit
Type 5:
LCD SEG or
pin configured as LCD SEG
Digital Input Equivalent Circuit
Type 1:
Standard Digital Input or
pin configured as DIO Input
with Internal Pull-Up
VREF Equivalent Circuit
Type 9:
VREF
V3P3A
V3P3D
V3P3D
Digital
Input
Pin
CMOS
Input
Analog
Input
Pin
GNDD
GNDD
Analog Input Equivalent Circuit
Type 6:
ADC Input
Digital Input
Type 2:
Pin configured as DIO Input
with Internal Pull-Down
V2P5 Equivalent Circuit
Type 10:
V2P5
V3P3A
V3P3D
Comparator
Input
Pin
To
Comparator
VLCD
Pin
LCD
Drivers
GNDA
Digital
Input
Pin
V2P5
Pin
GNDA
110K
GNDD
from
internal
reference
To
MUX
CMOS
Input
GNDD
Comparator Input Equivalent
Circuit Type 7:
Comparator Input
VLCD Equivalent Circuit
Type 11:
VLCD Power
GNDD
Oscillator
Pin
Digital Input Type 3:
Standard Digital Input or
pin configured as DIO Input
To
Oscillator
Power
Down
Circuits
VBAT
Pin
GNDD
GNDD
V3P3D
Oscillator Equivalent Circuit
Type 8:
Oscillator I/O
V3P3D
10
Digital
Output
Pin
CMOS
Output
from
V3P3SYS
V3P3D
Pin
GNDD
GNDD
Digital Output Equivalent Circuit
Type 4:
Standard Digital Output or
pin configured as DIO Output
VBAT Equivalent Circuit
Type 12:
VBAT Power
40
from
VBAT
V3P3D Equivalent Circuit
Type 13:
V3P3D
Figure 52: I/O Equivalent Circuits
162
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
7
Ordering Information
7.1
71M6541D/F/G and 71M6542F/G
Table 122. Ordering Information
Part
Part Description
(Package, Accuracy)
71M6541D
64-pin LQFP Lead-Free, 0.5%
71M6541D
64-pin LQFP Lead-Free, 0.5%
71M6541F
64-pin LQFP Lead-Free, 0.5%
71M6541F
64-pin LQFP Lead-Free, 0.5%
71M6541G* 64-pin LQFP Lead-Free, 0.5%
71M6541G* 64-pin LQFP Lead-Free, 0.5%
71M6542F
100-pin LQFP Lead-Free, 0.5%
71M6542F
100-pin LQFP Lead-Free, 0.5%
71M6542G
100-pin LQFP Lead-Free, 0.5%
71M6542G
100-pin LQFP Lead-Free, 0.5%
Flash
Size
Packaging
32 KB bulk
tape and
32 KB
reel
64 KB bulk
tape and
64 KB
reel
128 KB bulk
tape and
128 KB
reel
64 KB bulk
tape and
64 KB
reel
128 KB bulk
tape and
128 KB
reel
Order Number
Package
Marking
71M6541D-IGT/F
71M6541D-IGT
71M6541D-IGTR/F 71M6541D-IGT
71M6541F-IGT/F
71M6541F-IGT
71M6541F-IGTR/F 71M6541F-IGT
71M6541G-IGT/F
71M6541G-IGT
71M6541G-IGTR/F 71M6541G-IGT
71M6542F-IGT/F
71M6542F-IGT
71M6542F-IGTR/F 71M6542F-IGT
71M6542G-IGT/F
71M6542G-IGT
71M6542G-IGTR/F 71M6542G-IGT
*Future product—contact factory for availability.
8
Related Information
Users need these additional documents related to the 71M6541D/F/G and 71M6542F/G:
•
•
•
•
71M6541D/F/G and 71M6542F/G Data Sheet (this document)
71M6xxx Data Sheet
71M6541 Demo Board User’s Manual
71M654x Software User’s Guide
9
Contact Information
For more information about Maxim products or to check the availability of the 71M6541D/F/G and
71M6542F/G, contact technical support at www.maxim-ic.com/support.
Rev 2
163
71M6541D/F/G and 71M6542F/G Data Sheet
Appendix A: Acronyms
AFE
AMR
ANSI
CE
DIO
DSP
FIR
I2C
ICE
IEC
MPU
PLL
RMS
SFR
SOC
SPI
TOU
UART
164
Analog Front End
Automatic Meter Reading
American National Standards Institute
Compute Engine
Digital I /O
Digital Signal Processor
Finite Impulse Response
Inter-IC Bus
In-Circuit Emulator
International Electrotechnical Commission
Microprocessor Unit (CPU)
Phase-locked loop
Root Mean Square
Special Function Register
System on Chip
Serial Peripheral Interface
Time of Use
Universal Asynchronous Receiver/Transmitter
Rev 2
71M6541D/F/G and 71M6542F/G Data Sheet
Appendix B: Revision History
REVISION
NUMBER
1.0
REVISION
DATE
3/11
1.1
4/11
2
Rev 2
11/11
DESCRIPTION
Initial release
Removed the information about 18mW typ consumption at 3.3V
in sleep mode from the Features section
Updated the Temperature Measurement Equation and
Temperature Error parameters in Table 99
Promoted 71M6542G to production level (Table 122)
Added references to 71M6541G/2G throughout the document,
as appropriate.
Added missing data sheet title header to odd and even pages.
Corrected errata detected since the previous v1.1 (see
indicated pages changed).
Added section 6.7 on page 155.
PAGES
CHANGED
—
1
141
1, 9, 10, 27,
49, 54, 56,
62, 97, 120
165
71M6541D/F/G and 71M6542F/G Data Sheet
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit
patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0
 2011 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products.
19-5828; Rev 0; 4/11
ERRATA SHEET
71M6541G/71M6542G
Revision A01 Errata
The errata listed below describe situations where 71M6541G/71M6542G revision A01 components perform
differently than expected or differently than described in the data sheet. Maxim Integrated Products, Inc.,
intends to correct these errata when the opportunity to redesign the product presents itself.
This errata sheet only applies to 71M6541G/71M6542G revision A01 components. Revision A01
components are branded on the topside of the package with a six-digit code in the form yywwA01, where yy
and ww are two-digit numbers representing the year and work week of manufacture, respectively. To obtain
an errata sheet on another 71M6541G/71M6542G die revision, visit our website at
www.maxim-ic.com/errata.
1) RTC_Q[1:0] VALUE OF 1 BEHAVES ERRONEOUSLY THE SAME AS A VALUE OF 3
Description:
The RTC_Q[1:0] (I/O RAM 0x289D[1:0]) is one of two locations used for digitally adjusting the real-time
clock (RTC). The RTC_Q[1:0] field comprises 2 bits and can be set to 0, 1, 2, or 3. Due to a design error,
an RTC_Q[1:0] value of 1 behaves erroneously the same as a value of 3.
Workaround:
The workaround for this issue is to never program RTC_Q[1:0] to a value of 1, as follows:
a)When using the automatic RTC compensation (i.e., OSC_COMP = 1), and when loading the 128byte NV RAM with RTC compensation values, entries that would have normally been
RTC_Q[1:0] = 1 should be modified to have RTC_Q[1:0] = 0 or 2. In other words, instead of two
decision points that would indicate when RTC_Q[1:0] should shift from 0 to 1 and from 1 to 2,
there should be one decision point that causes RTC_Q[1:0] to shift between 0 and 2.
b)When automatic compensation is not used (i.e., OSC_COMP = 0) and the MPU is calculating the
RTC_P[16:0] and RTC_Q[1:0] correction, it should similarly replace the two decision points that
would have bracketed RTC_Q[1:0] = 1 with a single decision point that causes a transition
between 0 and 2.
Although this workaround causes a larger correction step, noise in the temperature sensor and variations in
actual temperature should allow the average value of the compensation to remain unchanged.
__________________________________Maxim Integrated Products
1
19-5827; Rev 0; 4/11
ERRATA SHEET
71M6541D/71M6541F/71M6542F
Revision B02 Errata
The errata listed below describe situations where 71M6541D/71M6541F/71M6542F revision B02
components perform differently than expected or differently than described in the data sheet. Maxim
Integrated Products, Inc., intends to correct these errata when the opportunity to redesign the product
presents itself.
This errata sheet only applies to 71M6541D/71M6541F/71M6542F revision B02 components. Revision B02
components are branded on the topside of the package with a six-digit code in the form yywwB02, where yy
and ww are two-digit numbers representing the year and work week of manufacture, respectively. To obtain
an errata sheet on another 71M6541D/71M6541F/71M6542F die revision, visit our website at
www.maxim-ic.com/errata.
1) RTC_Q[1:0] VALUE OF 1 BEHAVES ERRONEOUSLY THE SAME AS A VALUE OF 3
Description:
The RTC_Q[1:0] (I/O RAM 0x289D[1:0]) is one of two locations used for digitally adjusting the real-time
clock (RTC). The RTC_Q[1:0] field comprises 2 bits and can be set to 0, 1, 2, or 3. Due to a design error,
an RTC_Q[1:0] value of 1 behaves erroneously the same as a value of 3.
Workaround:
The workaround for this issue is to never program RTC_Q[1:0] to a value of 1, as follows:
a)When using the automatic RTC compensation (i.e., OSC_COMP = 1), and when loading the 128byte NV RAM with RTC compensation values, entries that would have normally been
RTC_Q[1:0] = 1 should be modified to have RTC_Q[1:0] = 0 or 2. In other words, instead of two
decision points that would indicate when RTC_Q[1:0] should shift from 0 to 1 and from 1 to 2,
there should be one decision point that causes RTC_Q[1:0] to shift between 0 and 2.
b)When automatic compensation is not used (i.e., OSC_COMP = 0) and the MPU is calculating the
RTC_P[16:0] and RTC_Q[1:0] correction, it should similarly replace the two decision points that
would have bracketed RTC_Q[1:0] = 1 with a single decision point that causes a transition
between 0 and 2.
Although this workaround causes a larger correction step, noise in the temperature sensor and variations in
actual temperature should allow the average value of the compensation to remain unchanged.
__________________________________Maxim Integrated Products
1