SPICE Device Model Si5517DU Vishay Siliconix N- and P-Channel 20-V (D-S) MOSFET CHARACTERISTICS • N- and P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n- and p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74130 S-52018⎯Rev. A, 03-Oct-05 www.vishay.com 1 SPICE Device Model Si5517DU Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Simulated Data Test Condition Measured Data Unit Static Gate Threshold Voltage On-State Drain Currenta Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltagea VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = 250 μA N-Ch 0.50 VDS = VGS, ID = −250 μA P-Ch 0.80 VDS < 5 V, VGS = 4.5 V N-Ch 117 VDS < −5 V, VGS = −4.5 V P-Ch 60 A VGS = 4.5 V, ID = 4.4 A N-Ch 0.032 0.032 VGS = −4.5 V, ID = −3.3 A P-Ch 0.063 0.060 VGS = 2.5 V, ID = 4.1 A N-Ch 0.038 0.037 VGS = −2.5 V, ID = −2.8 A P-Ch 0.082 0.083 VGS = 1.8 V, ID = 1.8 A N-Ch 0.046 0.046 VGS = −1.8 V, ID = −0.76 A P-Ch 0.107 0.108 VDS = 10 V, ID = 4.4 A N-Ch 23 22 VDS = −10 V, ID = −3.3 A P-Ch 11 9 IS = 1.2 A N-Ch 0.72 0.80 IS = −1A P-Ch 0.78 - 080 Ω S V Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Source Charge Ciss Coss N-Channel VDS = 10 V, VGS = 0 V, f = 1 MHz P-Channel VDS = −10 V, VGS = 0 V, f = 1 MHz Crss Qg Qgs Qgs N-Ch 605 520 P-Ch 589 455 N-Ch 96 100 P-Ch 103 105 N-Ch 62 60 P-Ch 57 65 VDS = 10 V, VGS = 8 V, ID = 4.4 A N-Ch 8.1 10.5 VDS = − 10 V, VGS = −8 V, ID = −4.6 A P-Ch 8.4 9.1 N-Ch 5 6 P-Ch 5 5.5 N-Ch 0.91 0.91 N-Channel VDS = 10 V, VGS = 4.5 V, ID = 4.4 A P-Channel VDS = −10 V, VGS = −4.5 V, ID = −1.8 A P-Ch 0.75 0.75 N-Ch 0.70 0.70 P-Ch 1.5 1.5 pF nC Notes a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 74130 S-52018⎯Rev. A, 03-Oct-05 SPICE Device Model Si5517DU Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) N-Channel MOSFET Document Number: 74130 S-52018⎯Rev. A, 03-Oct-05 www.vishay.com 3 SPICE Device Model Si5517DU Vishay Siliconix P-Channel MOSFET www.vishay.com 4 Document Number: 74130 S-52018⎯Rev. A, 03-Oct-05