1024-/256-Position, 1% Resistor Tolerance Error, I2C Interface and 50-TP Memory Digital Rheostat AD5272/AD5274 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD POWER-ON RESET RDAC REGISTER SCL SDA I2C SERIAL INTERFACE A 10/8 W 50-TP MEMORY BLOCK ADDR RESET VSS APPLICATIONS AD5272/AD5274 EXT_CAP GND 08076-001 Single-channel, 1024-/256-position resolution 20 kΩ, 50 kΩ, 100 kΩ nominal resistance Maximum ±1% nominal resistor tolerance error 50-times programmable (50-TP) wiper memory Rheostat mode temperature coefficient: 5 ppm/°C 2.7 V to 5.5 V single-supply operation ±2.5 V to ±2.75 V dual-supply operation for ac or bipolar operations I2C-compatible interface Wiper setting readback Power on refreshed from 50-TP memory Thin LFCSP 10-lead, 3 mm × 3 mm × 0.8 mm package Compact MSOP, 10-lead 3 mm × 4.9 mm × 1.1 mm package Figure 1. Mechanical rheostat replacements Op-amp: variable gain control Instrumentation: gain, offset adjustment Programmable voltage to current conversions Programmable filters, delays, time constants Programmable power supply Sensor calibration GENERAL DESCRIPTION The AD5272/AD52741 are single-channel, 1024-/256-position digital rheostats that combine industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. The AD5272/AD5274 ensure less than 1% end-to-end resistor tolerance error and offer 50-times programmable (50-TP) memory. The guaranteed industry leading low resistor tolerance error feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. 1 The AD5272/AD5274 device wiper settings are controllable through the I2C-compatible digital interface. Unlimited adjustments are allowed before programming the resistance value into the 50-TP memory. The AD5272/AD5274 do not require any external voltage supply to facilitate fuse blow and there are 50 opportunities for permanent programming. During 50-TP activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer). The AD5272/AD5274 are available in a 3 mm × 3 mm 10-lead LFCSP package and in a 10-lead MSOP package. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Protected by U.S. Patent Number 7688240. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com AD5272/AD5274 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Shift Register ............................................................................... 18 Applications ....................................................................................... 1 Write Operation.......................................................................... 19 Functional Block Diagram .............................................................. 1 Read Operation........................................................................... 20 General Description ......................................................................... 1 RDAC Register............................................................................ 21 Revision History ............................................................................... 2 50-TP Memory Block ................................................................ 21 Specifications..................................................................................... 3 Write Protection ......................................................................... 21 Electrical Characteristics—AD5272 .......................................... 3 50-TP Memory Write-Acknowledge Polling .......................... 23 Electrical Characteristics—AD5274 .......................................... 5 Reset ............................................................................................. 23 Interface Timing Specifications .................................................. 7 Resistor Performance Mode...................................................... 23 Absolute Maximum Ratings ............................................................ 9 Shutdown Mode ......................................................................... 23 Thermal Resistance ...................................................................... 9 RDAC Architecture .................................................................... 23 ESD Caution .................................................................................. 9 Programming the Variable Resistor ......................................... 23 Pin Configuration and Function Descriptions ........................... 10 EXT_CAP Capacitor .................................................................. 24 Typical Performance Characteristics ........................................... 11 Terminal Voltage Operating Range ......................................... 24 Test Circuits ..................................................................................... 17 Power-Up Sequence ................................................................... 24 Theory of Operation ...................................................................... 18 Outline Dimensions ....................................................................... 25 Serial Data Interface ................................................................... 18 Ordering Guide .......................................................................... 25 REVISION HISTORY 3/13—Rev. C to Rev. D Changed Resistor Noise Density, RAW = 20 kΩ from 50 nV/√Hz to 13 nV/√Hz; Table 1 ...................................................................... 4 Changed Resistor Noise Density, RAW = 20 kΩ from 50 nV/√Hz to 13 nV/√Hz; Table 4 ...................................................................... 6 Updated Outline Dimensions ....................................................... 25 3/10—Rev. 0 to Rev. A Changes to Product Title and General Description Section .......1 Changes to Theory of Operation Section.................................... 15 10/09—Revision 0: Initial Version 11/10—Rev. B to Rev. C Changes to Figure 24 ...................................................................... 14 5/10—Rev. A to Rev. B Added LFCSP Package .................................................. Throughout Changed OTP to 50-TP ................................................ Throughout Changes to Features Section and Applications Section ............... 1 Added Endnote 1 .............................................................................. 1 Changes to Table 1 ............................................................................ 3 Added Table 3.................................................................................... 4 Changes to Table 4 ............................................................................ 5 Added Table 6.................................................................................... 6 Changes to Table 8 and Table 9 ....................................................... 9 Added Figure 5................................................................................ 10 Added Exposed Pad Note to Table 10 .......................................... 10 Changes to Typical Performance Characteristics ....................... 11 Changes to Resistor Performance Mode Section ....................... 23 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 26 Rev. D | Page 2 of 28 Data Sheet AD5272/AD5274 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5272 VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity 2, 3 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance R-Perf Mode 4 Normal Mode Resistance Temperature Coefficient 5, 6 Wiper Resistance RESISTOR TERMINALS Terminal Voltage Range5, 7 Capacitance5 A Capacitance5 W Common-Mode Leakage Current5 DIGITAL INPUTS Input Logic5 High Low Input Current Input Capacitance5 DIGITAL OUTPUT Output Voltage5 High Low Tristate Leakage Current Output Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Supply Current Positive Negative 50-TP Store Current5, 8 Positive Negative 50-TP Read Current5, 9 Positive Negative Power Dissipation 10 Symbol Test Conditions/Comments Min R-INL RAW= 20 kΩ, |VDD − VSS| = 3.0 V to 5.5 V RAW= 20 kΩ, |VDD − VSS| = 2.7 V to 3.0 V RAW= 50 kΩ, 100 kΩ 10 −1 −1 −1 −1 See Table 2 and Table 3 −1 R-DNL Code = full scale Code = zero scale Typ 1 ±0.5 ±15 5 35 VSS f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VW VINH VINL IIN CIN VOH VOL Max Unit +1 +1.5 +1 +1 Bits LSB LSB LSB LSB +1 70 VDD 90 40 50 2.0 0.8 ±1 5 RPULL_UP = 2.2 kΩ to VDD RPULL_UP = 2.2 kΩ to VDD VDD = 2.7 V to 5.5 V, VSS = 0 V VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V VDD − 0.1 2.7 ±2.5 V V µA pF 5.5 ±2.75 V V 1 µA µA −1 IDD_OTP_STORE ISS_OTP_STORE 4 −4 IDD_OTP_READ ISS_OTP_READ mA mA 500 −500 VIH = VDD or VIL = GND Rev. D | Page 3 of 28 V V µA pF 0.4 0.6 +1 5 IDD ISS V pF pF nA V −1 VSS = 0 V % % ppm/°C Ω 5.5 µA µA µW AD5272/AD5274 Parameter Power Supply Rejection Ratio5 DYNAMIC CHARACTERISTICS5, 11 Bandwidth Total Harmonic Distortion Resistor Noise Density Data Sheet Symbol PSRR Test Conditions/Comments ΔVDD/ΔVSS = ±5 V ± 10% RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Min −3 dB, RAW = 10 kΩ, Terminal W, see Figure 41 RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ VA = 1 V rms, f = 1 kHz, code = half scale RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Typ 1 Max −66 −75 −78 −55 −67 −70 Unit dB kHz 300 120 60 dB −90 −88 −85 nV/√Hz 13 25 32 Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. 3 The maximum current in each code is defined by IAW = (VDD − 1)/RAW. 4 The terms, resistor performance mode and R-Perf mode, are used interchangeably. See the Resistor Performance Mode section. 5 Guaranteed by design and not subject to production test. 6 See Figure 24 for more details. 7 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 8 Different from operating current, the supply current for the fuse program lasts approximately 55 ms. 9 Different from operating current, the supply current for the fuse read lasts approximately 500 ns. 10 PDISS is calculated from (IDD × VDD) + (ISS × VSS). 11 All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V. 1 2 Table 2. AD5272 Resistor Performance Mode Code Range Resistor Tolerance Per Code R-TOLERANCE 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance |VDD − VSS| = 4.5 V to 5.5 V |VDD − VSS| = 2.7 V to 4.5 V From 0x078 to 0x3FF From 0x037 to 0x3FF From 0x028 to 0x3FF From 0x0BE to 0x3FF From 0x055 to 0x3FF From 0x037 to 0x3FF Table 3. AD5272 50 kΩ and 100 kΩ Resistor Performance Mode Code Range Resistor Tolerance Per Code R-TOLERANCE 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance RAW = 50 kΩ RAW = 100 kΩ From 0x078 to 0x3FF From 0x055 to 0x3FF From 0x032 to 0x3FF From 0x04B to 0x3FF From 0x032 to 0x3FF From 0x019 to 0x3FF Rev. D | Page 4 of 28 Data Sheet AD5272/AD5274 ELECTRICAL CHARACTERISTICS—AD5274 VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted. Table 4. Parameter DC CHARACTERISTICS— RHEOSTAT MODE Resolution Resistor Integral Nonlinearity 2, 3 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance R-Perf Mode 4 Normal Mode Resistance Temperature Coefficient 5, 6 Wiper Resistance RESISTOR TERMINALS Terminal Voltage Range5, 7 Capacitance5 A Capacitance5 W Common-Mode Leakage Current5 DIGITAL INPUTS Input Logic5 High Low Input Current Input Capacitance5 DIGITAL OUTPUT Output Voltage5 High Low Tristate Leakage Current Output Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Supply Current Positive Negative OTP Store Current5, 8 Positive Negative OTP Read Current5, 9 Positive Negative Power Dissipation 10 Power Supply Rejection Ratio5 Symbol Test Conditions/Comments Min Typ 1 8 −1 −1 R-INL R-DNL See Table 5 and Table 6 −1 Unit +1 +1 Bits LSB LSB +1 Code = full scale ±0.5 ±15 5 % % ppm/°C Code = zero scale 35 70 Ω VDD V pF pF nA VSS f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VW VINH VINL IIN CIN VOH VOL Max 90 40 50 2.0 0.8 ±1 5 RPULL_UP = 2.2 kΩ to VDD RPULL_UP = 2.2 kΩ to VDD VDD = 2.7 V to 5.5 V, VSS = 0 V VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V VDD − 0.1 V −1 0.4 0.6 +1 V V µA pF 5.5 ±2.75 V V 1 µA µA 5 VSS = 0 V 2.7 ±2.5 IDD ISS −1 IDD_OTP_STORE ISS_OTP_STORE 4 −4 IDD_OTP_READ ISS_OTP_READ PSRR mA mA 500 −500 VIH = VDD or VIL = GND ΔVDD/ΔVSS = ±5 V ± 10% RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Rev. D | Page 5 of 28 V V µA pF 5.5 −66 −75 −78 −55 −67 −70 µA µA µW dB AD5272/AD5274 Parameter DYNAMIC CHARACTERISTICS5, 11 Bandwidth Total Harmonic Distortion Resistor Noise Density Data Sheet Symbol Test Conditions/Comments Min −3 dB, RAW = 10 kΩ, Terminal W, see Figure 41 RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ VA = 1 V rms, f = 1 kHz, code = half scale RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Typ 1 Max Unit kHz 300 120 60 dB −90 −88 −85 nV/√Hz 13 25 32 Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. 3 The maximum current in each code is defined by IAW = (VDD − 1)/RAW. 4 The terms, resistor performance mode and R-Perf mode, are used interchangeably. See the Resistor Performance Mode section. 5 Guaranteed by design and not subject to production test. 6 See Figure 24 for more details. 7 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 8 Different from operating current, the supply current for the fuse program lasts approximately 55 ms. 9 Different from operating current, the supply current for the fuse read lasts approximately 500 ns. 10 PDISS is calculated from (IDD × VDD) + (ISS × VSS). 11 All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V. 1 2 Table 5. AD5274 Resistor Performance Mode Code Range Resistor Tolerance per Code R-TOLERANCE 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance |VDD − VSS| = 4.5 V to 5.5 V |VDD − VSS| = 2.7 V to 4.5 V From 0x1E to 0xFF From 0x0F to 0xFF From 0x06 to 0xFF From 0x32 to 0xFF From 0x19 to 0xFF From 0x0E to 0xFF Table 6. AD5274 50 kΩ and 100 kΩ Resistor Performance Mode Code Range Resistor Tolerance per Code R-TOLERANCE 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance RAW = 50 kΩ RAW = 100 kΩ From 0x1E to 0xFF From 0x14 to 0xFF From 0x0A to 0xFF From 0x14 to 0xFF From 0x0F to 0xFF From 0x0A to 0xFF Rev. D | Page 6 of 28 Data Sheet AD5272/AD5274 INTERFACE TIMING SPECIFICATIONS VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7. Parameter fSCL 2 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t11A t12 t13 tSP 3 tEXEC 4, 5 tRDAC_R-PERF tRDAC_NORMAL tMEMORY_READ tMEMORY_PROGRAM tRESET tPOWER-UP 6 Conditions 1 Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode High speed mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Limit at TMIN, TMAX Min Max 100 400 4 0.6 4.7 1.3 250 100 0 3.45 0 0.9 4.7 0.6 4 0.6 160 4.7 1.3 4 0.6 1000 300 300 300 1000 300 1000 Unit kHz kHz µs µs µs µs ns ns µs µs µs µs µs µs ns µs µs µs µs ns ns ns ns ns ns ns Fast mode 300 ns Standard mode Fast mode RESET pulse time Fast mode 300 300 ns ns ns ns ns µs ns µs ms µs ms 20 0 500 50 2 600 6 350 600 2 Description Serial clock frequency Serial clock frequency tHIGH, SCL high time tHIGH, SCL high time tLOW, SCL low time tLOW, SCL low time tSU;DAT, data setup time tSU;DAT, data setup time tHD;DAT, data hold time tHD;DAT, data hold time tSU;STA, set-up time for a repeated start condition tSU;STA, set-up time for a repeated start condition tHD;STA, hold time (repeated) start condition tHD;STA, hold time (repeated) start condition tHD;STA, hold time (repeated) start condition tBUF, bus free time between a stop and a start condition tBUF, bus free time between a stop and a start condition tSU;STO, setup time for a stop condition tSU;STO, setup time for a stop condition tRDA, rise time of SDA signal tRDA, rise time of SDA signal tFDA, fall time of SDA signal tFDA, fall time of SDA signal tRCL, rise time of SCL signal tRCL, rise time of SCL signal tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit tFCL, fall time of SCL signal tFCL, fall time of SCL signal Minimum RESET low time Pulse width of spike suppressed Command execute time RDAC register write command execute time (R-Perf mode) RDAC register write command execute time (normal mode) Memory readback execute time Memory program time Reset 50-TP restore time Power-on 50-TP restore time Maximum bus capacitance is limited to 400 pF. The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode. 4 Refer to tRDAC_R-PERF and tRDAC_NORMAL for RDAC register write operations. 5 Refer to tMEMORY_READ and tMEMORY_PROGRAM for memory commands operations. 6 Maximum time after VDD − VSS is equal to 2.5 V. 1 2 Rev. D | Page 7 of 28 AD5272/AD5274 Data Sheet Shift Register and Timing Diagrams DB9 (MSB) C3 0 C1 C2 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 08076-003 0 DB0 (LSB) DATA BITS CONTROL BITS Figure 2. Shift Register Content t11 t12 t6 t8 t2 SCL t5 t1 t6 t4 t10 t3 t9 SDA t7 P S S P 08076-002 RESET t13 Figure 3. 2-Wire Serial Interface Timing Diagram Rev. D | Page 8 of 28 Data Sheet AD5272/AD5274 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 8. Parameter VDD to GND VSS to GND VDD to VSS VA, VW to GND Digital Input and Output Voltage to GND EXT_CAP to VSS IA, IW Continuous RAW = 20 kΩ RAW = 50 kΩ, 100 kΩ Pulsed 1 Frequency > 10 kHz Frequency ≤ 10 kHz Operating Temperature Range 4 Maximum Junction Temperature (TJ Maximum) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Rating –0.3 V to +7.0 V +0.3 V to −7.0 V 7V VSS − 0.3 V, VDD + 0.3 V −0.3 V to VDD + 0.3 V 7V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is defined by JEDEC specification JESD-51 and the value is dependent on the test board and test environment. Table 9. Thermal Resistance ±3 mA ±2 mA Package Type 10-Lead LFCSP 10-Lead MSOP ±MCC 2/d 3 ±MCC2/√d3 −40°C to +125°C 150°C 1 JEDEC 2S2P test board, still air (0 m/s air flow). ESD CAUTION −65°C to +150°C θJA1 50 135 260°C 20 sec to 40 sec (TJ max − TA)/θJA Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A and W terminals at a given resistance. 2 Maximum continuous current 3 Pulse duty factor. 4 Includes programming of 50-TP memory. 1 Rev. D | Page 9 of 28 θJC 3 N/A Unit °C/W °C/W AD5272/AD5274 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 10 ADDR AD5272/ AD5274 9 SCL W 3 VSS 4 (EXPOSED PAD) 7 RESET A 2 A 2 W 3 VSS 4 10 ADDR AD5272/ AD5274 9 SCL 8 SDA TOP VIEW (Not to Scale) 7 RESET 6 GND EXT_CAP 5 EXT_CAP 5 6 GND NOTES 1. THE EXPOSED PAD IS LEFT FLOATING OR IS TIED TO VSS. 08076-004 VDD 1 8 SDA Figure 4. MSOP Pin Configuration 08076-040 VDD 1 Figure 5. LFCSP Pin Configuration Table 10. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic VDD A W VSS 5 EXT_CAP 6 7 GND RESET 8 SDA 9 10 EPAD SCL ADDR Exposed Pad (LFCSP Only) Description Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. Terminal A of RDAC. VSS ≤ VA ≤ VDD. Wiper terminal of RDAC. VSS ≤ VW ≤ VDD. Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. External Capacitor. Connect a 1 μF capacitor between EXT_CAP and VSS. This capacitor must have a voltage rating of ≥7 V. Ground Pin, Logic Ground Reference. Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET to VDD if not used. Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input registers. Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 11). Leave floating or tie to VSS. Rev. D | Page 10 of 28 Data Sheet AD5272/AD5274 TYPICAL PERFORMANCE CHARACTERISTICS 0.8 0.8 +125°C +25°C –40°C 0.6 RAW = 20kΩ TA = 25°C 0.4 0.2 0.2 0 0 –0.2 –0.2 0 128 256 384 512 640 768 896 –0.4 08076-010 –0.4 1023 CODE (Decimal) 0 256 512 CODE (Decimal) 768 1023 08076-111 INL (LSB) 0.4 INL (LSB) 20kΩ 50kΩ 100kΩ 0.6 Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5272) Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5272) 0.6 0.2 TA = 25°C RAW = 20kΩ 0.1 0.4 0 0.2 DNL (LSB) DNL (LSB) –0.1 –0.2 0 –0.3 –0.2 –0.4 –0.4 +25°C 0 128 256 384 512 768 896 1023 CODE (Decimal) Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5272) –0.6 0 50kΩ 256 100kΩ 512 CODE (Decimal) 768 0.6 +125°C +25°C –40°C 1023 Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5272) 0.5 0.4 20kΩ +125°C 640 08076-011 –40°C –0.6 08076-120 –0.5 20kΩ 50kΩ 100kΩ TA = 25°C RAW = 20kΩ 0.4 INL (LSB) 0.2 0.2 0 0.1 –0.1 0 128 256 384 512 640 768 896 1023 CODE (Decimal) Figure 8. R-INL in Normal Mode vs. Code vs. Temperature (AD5272) –0.4 0 256 512 CODE (Decimal) 768 1023 08076-121 –0.2 0 08076-014 INL (LSB) 0.3 Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5272) Rev. D | Page 11 of 28 AD5272/AD5274 Data Sheet 0.15 0.15 +125°C +25°C –40°C 0.10 RAW = 20kΩ 20kΩ 50kΩ 100kΩ TA = 25°C 0.10 0.05 DNL (LSB) DNL (LSB) 0.05 0 0 –0.05 –0.05 –0.10 –0.10 0 128 256 384 512 640 768 896 1023 CODE (Decimal) –0.20 08076-015 –0.15 Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature (AD5272) 0 256 512 CODE (Decimal) 768 Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5272) 0.15 0.20 +125°C +25°C –40°C 0.15 1023 08076-122 –0.15 20kΩ 100kΩ TA = 25°C RAW = 20kΩ 0.10 INL (LSB) INL (LSB) 0.10 0.05 0.05 0 0 0 64 128 CODE (Decimal) 192 255 08076-013 –0.10 –0.10 0 128 CODE (Decimal) 192 255 Figure 16. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5274) Figure 13. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5274) 0.15 0.06 RAW = 20kΩ +125°C +25°C –40°C 0.04 TA = 25°C 0.10 0.02 0 0.05 –0.02 DNL (LSB) –0.04 –0.06 0 –0.05 –0.08 –0.10 –0.10 –0.12 20kΩ 0 64 128 CODE (Decimal) 192 255 Figure 14. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5274) 100kΩ –0.15 08076-012 –0.14 0 64 128 CODE (Decimal) 192 255 08076-125 DNL (LSB) 64 08076-123 –0.05 –0.05 Figure 17. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5274) Rev. D | Page 12 of 28 Data Sheet AD5272/AD5274 0.15 0.10 +125°C +25°C –40°C 0.08 RAW = 20kΩ 20kΩ 100kΩ TA = 25°C 0.10 0.05 INL (LSB) INL (LSB) 0.06 0.04 0 0.02 –0.05 0 64 128 CODE (Decimal) 192 255 –0.10 0 128 CODE (Decimal) 192 255 Figure 21. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5274) Figure 18. R-INL in Normal Mode vs. Code vs. Temperature (AD5274) 0.010 0.03 +125°C +25°C –40°C RAW = 20kΩ 0.02 TA = 25°C 100kΩ 20kΩ 0.008 0.01 DNL (LSB) 0.006 0.004 –0.01 0.002 –0.02 0 –0.03 0 64 128 CODE (Decimal) 192 255 –0.002 Figure 19. R-DNL in Normal Mode vs. Code vs. Temperature (AD5274) 0 128 CODE (Decimal) 64 192 255 Figure 22. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5274) 0.7 500 400 0.6 IDD = 5V 300 0.5 0.4 IDD (mA) IDD = 3V ISS = 3V 0 –100 0.3 0.2 –200 0.1 ISS = 5V –300 –500 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 TEMPERATURE (°C) –0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VLOGIC (V) 4.0 4.5 5.0 Figure 23. Supply Current (IDD) vs. Digital Input Voltage Figure 20. Supply Current (IDD, ISS) vs. Temperature Rev. D | Page 13 of 28 5.5 08076-110 0 –400 08076-018 CURRENT (nA) 200 100 008076-027 0 08076-017 DNL (LSB) 64 08076-126 0 08076-016 –0.02 AD5272/AD5274 Data Sheet 50 45 VDD/VSS = 5V/0V 20kΩ 50kΩ 100kΩ 20kΩ 50kΩ 100kΩ 6 THEORETICAL IWA_MAX (mA) 40 35 30 25 20 15 10 5 4 3 2 1 5 256 64 512 128 CODE (Decimal) 768 192 1023 AD5272 255 AD5274 0 0 08076-019 0 0 256 64 Figure 24. Tempco ΔRWA/ΔT vs. Code 768 192 1023 AD5272 255 AD5274 Figure 27. Theoretical Maximum Current vs. Code 0 0 AD5272 (AD5274) 0x200 (0x80) –10 512 128 CODE (Decimal) AD5272 (AD5274) 0x200 (0x80) 0x100 (0x40) –10 0x100 (0x40) 0x080 (0x20) 0x080 (0x20) 0x020 (0x08) 0x010 (0x04) –40 0x020 (0x08) –30 0x010 (0x04) 0x008 (0x02) –40 0x008 (0x02) 0x004 (0x01) 0x004 (0x01) 0x002 –50 0x001 –60 0x001 –50 10k 100k 1M 10M FREQUENCY (Hz) –70 1k 08076-031 –60 1k 0x002 0 AD5272 (AD5274) –10 –20 0x020 (0x08) 0x010 (0x04) –40 50kΩ 100kΩ 20kΩ –30 0x040 (0x10) PSRR (dB) –30 10M VDD/VSS = 5V/0V CODE = HALF SCALE 0x100 (0x40) 0x080 (0x20) –20 1M Figure 28. 100 kΩ Gain vs. Code vs. Frequency 0 –10 100k FREQUENCY (Hz) Figure 25. 20 kΩ Gain vs. Code vs. Frequency 0x200 (0x80) 10k 08076-041 –30 0x040 (0x10) 0x040 (0x10) GAIN (dB) 0x008 (0x02) –40 –50 –60 0x004 (0x01) –50 –70 0x002 0x001 10k 100k 1M FREQUENCY (Hz) 10M 08076-032 –60 1k –80 Figure 26. 50 kΩ Gain vs. Code vs. Frequency –90 100 1k 10k FREQUENCY (Hz) Figure 29. PSRR vs. Frequency Rev. D | Page 14 of 28 100k 08076-024 GAIN (dB) –20 –20 08076-028 0 0 GAIN (dB) RHEOSTAT MODE TEMPCO (ppm/°C) 7 VDD/VSS= 5V/0V Data Sheet AD5272/AD5274 0 0 20kΩ 50kΩ 100kΩ VDD/VSS = 5V/0V CODE = HALF SCALE fIN = 1kHz NOISE BW = 22kHz –10 –20 –40 20kΩ 50kΩ 100kΩ –30 THD + N (dB) THD + N (dB) VDD/VSS = 5V/0V CODE = HALF SCALE NOISE BW = 22kHz –20 VIN = 1V rms –40 –50 –60 –60 –70 –80 –80 10k 08076-025 1k –100 0.001 100k FREQUENCY (Hz) Figure 30. THD + N vs. Frequency 0.01 0.1 VOLTAGE (VRMS) 08076-026 –90 –100 100 1 Figure 33. THD + N vs. Amplitude 0.03 0.0010 VDD/VSS = 5V/0V IAW = 200µA CODE = HALF SCALE 20kΩ 50kΩ 100kΩ 0.02 0.0005 VOLTAGE (V) VOLTAGE (V) 0.01 0 –0.01 0 –0.0005 –0.02 –0.0010 14 19 –0.0015 –10 0 10.00 6.25 20 5.00 15 3.75 10 2.50 5 1.25 0 4.2 VDD (V) 4.7 5.2 NUMBER OF CODES (AD5272) 25 3.7 15.5 20kΩ 50kΩ 100kΩ 60 NUMBER OF CODES (AD5274) 8.75 7.50 3.2 60 50 VDD/VSS = 5V/0V 30 0 2.7 40 70 11.25 08076-021 NUMBER OF CODES (AD5272) 35 30 Figure 34. Digital Feedthrough TA = 25°C 20kΩ 50kΩ 100kΩ 40 20 TIME (µs) Figure 31. Maximum Glitch Energy 45 10 15.0 50 12.5 40 10.0 30 7.5 20 5.0 10 2.5 0 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 Figure 35. Maximum Code Loss vs. Power Supply Range Figure 32. Maximum Code Loss vs. Temperature Rev. D | Page 15 of 28 0 NUMBER OF CODES (AD5274) 9 TIME (µs) 08076-020 4 08076-043 –0.04 –1 08076-046 –0.03 AD5272/AD5274 Data Sheet 0.006 8 VDD/VSS = 5V/0V IAW = 10µA CODE = HALF SCALE 0.005 ΔRAW RESISTANCE (%) 6 5 0.004 0.003 0.002 0.001 0 4 0.07 0.09 0.11 0.13 0.15 TIME (Seconds) 0.17 –0.002 Figure 36. VEXT_CAP Waveform While Writing Fuse 0 100 200 300 400 500 600 700 800 900 1000 OPERATION AT 150°C (Hours) Figure 37. Long-Term Drift Accelerated Average by Burn-In Rev. D | Page 16 of 28 08076-038 –0.001 08076-029 VOLTAGE (V) 7 Data Sheet AD5272/AD5274 TEST CIRCUITS Figure 38 to Figure 42 define the test conditions used in the Specifications section. DUT DUT IW VMS 08076-033 VMS Figure 41. Gain vs. Frequency Figure 38. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) RWA = CODE = 0x00 IW V 08076-036 A A DUT 1GΩ W W DUT VMS IW GND ICM W RWA RW = 2 +2.75V –2.75V A W GND VMS NC = NO CONNECT +2.75V Figure 39. Wiper Resistance V+ = VDD ±10% IW W V+ PSS (%/%) = –2.75V Figure 42. Common Leakage Current PSRR (dB) = 20 log VDD GND NC ΔVMS% ΔVDD% VMS VDD VMS 08076-035 A Figure 40. Power Supply Sensitivity (PSS, PSRR) Rev. D | Page 17 of 28 08076-037 08076-034 A AD5272/AD5274 Data Sheet THEORY OF OPERATION The AD5272 and AD5274 digital rheostats are designed to operate as true variable resistors for analog signals within the terminal voltage range of VSS < VTERM < VDD. The RDAC register contents determine the resistor wiper position. The RDAC register acts as a scratchpad register, which allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting using the I2C interface. When a desirable wiper position is found, this value can be stored in a 50-TP memory register. Thereafter, the wiper position is always restored to that position for subsequent power-up. The storing of 50-TP data takes approximately 350 ms; during this time, the AD5272/AD5274 is locked and does not acknowledge any new command thereby preventing any changes from taking place. The acknowledge bit can be polled to verify that the fuse program command is complete. The AD5272/AD5274 also feature a patented 1% end-to-end resistor tolerance. This simplifies precision, rheostat mode, and open-loop applications where knowledge of absolute resistance is critical. SERIAL DATA INTERFACE The AD5272/AD5274 have 2-wire I2C-compatible serial interfaces. Each of these devices can be connected to an I2C bus as a slave device under the control of a master device; see Figure 3 for a timing diagram of a typical write sequence. The AD5272/AD5274 support standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. The AD5272/AD5274 each has a 7-bit slave address. The five MSBs are 01011 and the two LSBs are determined by the state of the ADDR pin. The facility to make hardwired changes to ADDR allows the user to incorporate up to three of these devices on one bus as outlined in Table 11. The 2-wire serial bus protocol operates as follows: The master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The next byte is the address byte, which consists of the 7-bit slave address and a R/W bit. The slave device corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition. SHIFT REGISTER For the AD5272/AD5274, the shift register is 16 bits wide, as shown in Figure 2. The 16-bit word consists of two unused bits, which should be set to zero, followed by four control bits and 10 RDAC data bits (note that for the AD5274 only, the lower two RDAC data bits are don’t care if the RDAC register is read from or written to), and data is loaded MSB first (Bit 15). The four control bits determine the function of the software command (Table 12). Figure 43 shows a timing diagram of a typical AD5272/AD5274 write sequence. The command bits (Cx) control the operation of the digital potentiometer and the internal 50-TP memory. The data bits (Dx) are the values that are loaded into the decoded register. Table 11. Device Address Selection ADDR GND VDD NC (No Connection) 1 1 A1 1 0 1 A0 1 0 0 Not available in bipolar mode. VSS < 0 V. Rev. D | Page 18 of 28 7-Bit I2C Device Address 0101111 0101100 0101110 Data Sheet AD5272/AD5274 Two bytes of data are then written to the RDAC, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the AD5272/AD5274. A stop condition follows. The write operations for the AD5272/ AD5274 are shown in Figure 43. WRITE OPERATION It is possible to write data for the RDAC register or the control register. When writing to the AD5272/AD5274, the user must begin with a start command followed by an address byte (R/W = 0), after which the AD5272/AD5274 acknowledges that it is prepared to receive data by pulling SDA low. A repeated write function gives the user flexibility to update the device a number of times after addressing the part only once, as shown in Figure 44. 1 9 1 9 SCL 1 0 SDA 0 1 1 A1 A0 R/W 0 0 C3 C2 C1 C0 D9 D8 ACK. BY AD5272/AD5274 ACK. BY AD5272/AD5274 START BY MASTER FRAME 2 MOST SIGNIFICANT DATA BYTE FRAME 1 SERIAL BUS ADDRESS BYTE 1 9 9 SCL (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY STOP BY AD5272/AD5274 MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE 08076-005 SDA (CONTINUED) Figure 43. Write Command 1 9 1 9 SCL 0 1 0 1 1 A1 START BY MASTER A0 R/W 0 0 C3 C2 C1 C0 D9 D8 ACK. BY AD5272 2/AD5274 ACK. BY AD5272 2/AD5274 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 MOST SIGNIFICANT DATA BYTE 9 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD5272 2/AD5274 FRAME 3 LEAST SIGNIFICANT DATA BYTE 9 1 9 SCL (CONTINUED) 0 SDA (CONTINUED) 0 C3 C2 C1 C0 D9 D8 ACK. BY AD5272 2/AD5274 FRAME 4 MOST SIGNIFICANT DATA BYTE 9 9 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 STOP BY ACK. BY AD5272 2/AD5274 MASTER FRAME 5 LEAST SIGNIFICANT DATA BYTE Figure 44. Multiple Write Rev. D | Page 19 of 28 08076-006 SDA AD5272/AD5274 Data Sheet A stop condition follows. These bytes contain the read instruction, which enables readback of the RDAC register, 50-TP memory, or the control register. The user can then read back the data beginning with a start command followed by an address byte (R/W = 1), after which the device acknowledges that it is prepared to transmit data by pulling SDA low. Two bytes of data are then read from the device, as shown in Figure 45. A stop condition follows. If the master does not acknowledge the first byte, the second byte is not transmitted by the AD5272/AD5274. READ OPERATION When reading data back from the AD5272/AD5274, the user must first issue a readback command to the device, this begins with a start command followed by an address byte (R/W = 0), after which the AD5272/AD5274 acknowledges that it is prepared to receive data by pulling SDA low. Two bytes of data are then written to the AD5272/AD5274, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the AD5272/AD5274. 1 9 1 9 SCL SDA 0 1 0 1 1 A1 A0 R/W 0 0 C3 C2 C1 C0 D9 D8 ACK. BY AD5272/AD5274 START BY MASTER ACK. BY AD5272/AD5274 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 MOST SIGNIFICANT DATA BYTE 9 9 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY STOP BY AD5272/AD5274 MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE 1 9 1 9 SCL 0 1 0 1 1 A1 A0 R/W 0 0 X X X X D9 D8 ACK. BY AD5272/AD5274 START BY MASTER ACK. BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 MOST SIGNIFICANT DATA BYTE 9 9 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 NO ACK. BY STOP BY MASTER MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE Figure 45. Read Command Rev. D | Page 20 of 28 08076-007 SDA Data Sheet AD5272/AD5274 RDAC REGISTER Prior to 50-TP activation, the AD5272/AD5274 is preset to midscale on power-up. It is possible to read back the contents of any of the 50-TP memory registers through the I2C interface by using Command 5 in Table 12. The lower six LSB bits, D0 to D5 of the data byte, select which memory location is to be read back. A binary encoded version address of the most recently programmed wiper memory location can be read back using Command 6 in Table 12. This can be used to monitor the spare memory status of the 50-TP memory block. The RDAC register directly controls the position of the digital rheostat wiper. For example, when the RDAC register is loaded with all zeros, the wiper is connected to Terminal A of the variable resistor. It is possible to both write to and read from the RDAC register using the I2C interface. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. 50-TP MEMORY BLOCK WRITE PROTECTION The AD5272/AD5274 contain an array of 50-TP programmable memory registers, which allow the wiper position to be programmed up to 50 times. Table 16 shows the memory map. Command 3 in Table 12 programs the contents of the RDAC register to memory. The first address to be programmed is Location 0x01, see Table 16, and the AD5272/AD5274 increments the 50-TP memory address for each subsequent program until the memory is full. Programming data to 50-TP consumes approximately 4 mA for 55 ms, and takes approximately 350 ms to complete, during which time the shift register is locked preventing any changes from taking place. Bit C3 of the control register in Table 15 can be polled to verify that the fuse program command was successful. No change in supply voltage is required to program the 50-TP memory; however, a 1 µF capacitor on the EXT_CAP pin is required as shown in Figure 47. On power-up, serial data input register write commands for both the RDAC register and the 50-TP memory registers are disabled. The RDAC write protect bit (Bit C1) of the control register (see Table 14 and Table 15) is set to 0 by default. This disables any change of the RDAC register content regardless of the software commands, except that the RDAC register can be refreshed from the 50-TP memory using the software reset, Command 4, or through hardware by the RESET pin. To enable programming of the variable resistor wiper position (programming the RDAC register), the write protect bit (Bit C1) of the control register must first be programmed. This is accomplished by loading the serial data input register with Command 7 (see Table 12). To enable programming of the 50-TP memory block, Bit C0 of the control register, which is set to 0 by default, must first be set to 1. Table 12. Command Operation Truth Table Command Number 0 1 Command[DB13:DB10] C3 C2 C1 C0 0 0 0 0 0 0 0 1 D7 X D7 Data[DB9:B0] 1 D6 D5 D4 D3 X X X X D6 D5 D4 D3 D9 X D9 D8 X D8 D2 X D2 D1 X D1 2 D0 X D02 2 0 0 1 0 X X X X X X X X X X 3 0 0 1 1 X X X X X X X X X X 4 0 1 0 0 X X X X X X X X X X 53 0 1 0 1 X X X X D5 D4 D3 D2 D1 D0 6 0 1 1 0 X X X X X X X X X X 74 0 1 1 1 X X X X X X X D2 D1 D0 8 1 0 0 0 X X X X X X X X X X 9 1 0 0 1 X X X X X X X X X D0 X = don’t care. AD5274 = don’t care. 3 See Table 16 for the 50-TP memory map. 4 See Table 15 for bit details. 1 2 Rev. D | Page 21 of 28 Operation NOP: do nothing. Write contents of serial register data to RDAC. Read contents of RDAC wiper register. Store wiper setting: store RDAC setting to 50-TP. Software reset: refresh RDAC with the last 50-TP memory stored value. Read contents of 50-TP from the SDO output in the next frame. Read address of the last 50-TP programmed memory location. Write contents of the serial register data to the control register. Read contents of the control register. Software shutdown. D0 = 0; normal mode. D0 = 1; shutdown mode. AD5272/AD5274 Data Sheet Table 13. Write and Read to RDAC and 50-TP memory DIN 0x1C03 0x0500 0x0800 0x0C00 SDO1 0xXXXX 0x1C03 0x0500 0x100 0x1800 0x0000 0x0C00 0xXX19 0x1419 0x2000 0x0000 0x0100 0x0000 0xXXXX 1 Action Enable update of wiper position and 50-TP memory contents through digital interface. Write 0x100 to the RDAC register, wiper moves to ¼ full-scale position. Prepare data read from RDAC register. Stores RDAC register content into 50-TP memory. 16-bit word appears out of SDO, where last 10-bits contain the contents of the RDAC Register 0x100. Prepare data read of last programmed 50-TP memory monitor location. NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs last 6-bits contain the binary address of the last programmed 50-TP memory location, for example, 0x19 (see Table 16). Prepares data read from Memory Location 0x19. Prepare data read from the control register. Sends a 16-bit word out of SDO, where the last 10-bits contain the contents of Memory Location 0x19. NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register. If Bit C3 = 1, fuse program command successful. X is don’t care. Table 14. Control Register Bit Map DB9 0 DB8 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 C3 DB2 C2 DB1 C1 DB0 C0 Table 15. Control Register Description Bit Name C0 C1 C2 C3 1 Description 50-TP program enable 0 = 50-TP program disabled (default) 1 = enable device for 50-TP program RDAC register write protect 0 = wiper position frozen to value in 50-TP memory (default)1 1 = allow update of wiper position through a digital interface Resistor performance enable 0 = RDAC resistor tolerance calibration enabled (default) 1 = RDAC resistor tolerance calibration disabled 50-TP memory program success bit 0 = fuse program command unsuccessful (default) 1 = fuse program command successful Wiper position is frozen to the last value programmed in the 50-TP memory. Wiper freezes to midscale if 50-TP memory has not been previously programmed. Table 16. Memory Map Command Number 5 1 D9 X X X X X … X X X X X D8 X X X X X … X X X X X D7 X X X X X … X X X X X Data Byte [DB9:DB8]1 D6 D5 D4 D3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 … … … … 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 D2 0 0 0 0 1 … 0 1 1 0 0 X is don’t care. Rev. D | Page 22 of 28 D1 0 0 1 1 0 … 1 0 1 0 1 D0 0 1 0 1 0 … 0 0 0 0 0 Register Contents Reserved 1st programmed wiper location (0x01) 2nd programmed wiper location (0x02) 3rd programmed wiper location (0x03) 4th programmed wiper location (0x04) … 10th programmed wiper location (0xA) 20th programmed wiper location (0x14) 30th programmed wiper location (0x1E) 40th programmed wiper location (0x28) 50th programmed wiper location (0x32) Data Sheet AD5272/AD5274 50-TP MEMORY WRITE-ACKNOWLEDGE POLLING A After each write operation to the 50-TP registers, an internal write cycle begins. The I2C interface of the device is disabled. To determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C interface polling can be conducted by sending a start condition, followed by the slave address and the write bit. If the I2C interface responds with an acknowledge (ACK), the write cycle is complete and the interface is ready to proceed with further operations. Otherwise, I2C interface polling can be repeated until it completes. RL RL RM RM 10-/8-BIT ADDRESS DECODER SW RW W RW The AD5272/AD5274 can be reset through software by executing Command 4 (see Table 12) or through hardware on the low pulse of the RESET pin. The reset command loads the RDAC register with the contents of the most recently programmed 50-TP memory location. The RDAC register loads with midscale if no 50-TP memory location has been previously programmed. Tie RESET to VDD if the RESET pin is not used. RESISTOR PERFORMANCE MODE This mode activates a new, patented 1% end-to-end resistor tolerance that ensures a ±1% resistor tolerance on each code, that is, code = half scale and RWA = 10 kΩ ± 100 Ω. See Table 2, Table 3, Table 5, and Table 6 to check which codes achieve ±1% resistor tolerance. The resistor performance mode is activated by programming Bit C2 of the control register (see Table 14 and Table 15). SHUTDOWN MODE The AD5272/AD5274 can be shut down by executing the software shutdown command, Command 9 (see Table 12), and setting the LSB to 1. This feature places the RDAC in a zero-powerconsumption state where Terminal Ax is disconnected from the wiper terminal. It is possible to execute any command from Table 12 while the AD5272 or AD5274 is in shutdown mode. The part can be taken out of shutdown mode by executing Command 9 and setting the LSB to 0, or by issuing a software or hardware reset. RDAC ARCHITECTURE To achieve optimum performance, Analog Devices has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5272/AD5274 employ a three-stage segmentation approach, as shown in Figure 46. The AD5272/ AD5274 wiper switch is designed with the transmission gate CMOS topology. 08076-008 RESET Figure 46. Simplified RDAC Circuit PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation—1% Resistor Tolerance The nominal resistance between Terminal W and Terminal A, RWA, is available in 20 kΩ, 50 kΩ, and 100 kΩ, and 1024-/256-tap points accessed by the wiper terminal. The 10-/8-bit data in the RDAC latch is decoded to select one of the 1024 or 256 possible wiper settings. The AD5272/ AD5274 contain an internal ±1% resistor tolerance calibration feature which can be disabled or enabled, enabled by default, or by programming Bit C2 of the control register (see Table 15). The digitally programmed output resistance between the W terminal and the A terminal, RWA, is calibrated to give a maximum of ±1% absolute resistance error over both the full supply and temperature ranges. As a result, the general equations for determining the digitally programmed output resistance between the W terminal and A terminal are as follows: For the AD5272 D (1) RWA (D) = × RWA 1024 For the AD5274 RWA (D) = D × RWA 256 (2) where: D is the decimal equivalent of the binary code loaded in the 10-/8-bit RDAC register. RWA is the end-to-end resistance. In the zero-scale condition, a finite total wiper resistance of 120 Ω is present. Regardless of which setting the part is operating in, take care to limit the current between the A terminal to B terminal, W terminal to A terminal, and W terminal to B terminal, to the maximum continuous current of ±3 mA, or the pulse current specified in Table 8. Otherwise, degradation or possible destruction of the internal switch contact can occur. Rev. D | Page 23 of 28 AD5272/AD5274 Data Sheet EXT_CAP CAPACITOR A 1 μF capacitor to VSS must be connected to the EXT_CAP pin (see Figure 47) on power-up and throughout the operation of the AD5272/AD5274. AD5272/ AD5274 EXT_CAP C1 1µF 50_OTP MEMORY BLOCK POWER-UP SEQUENCE 08076-009 VSS VSS The ground pins of the AD5272/AD5274 devices are primarily used as digital ground references. To minimize the digital ground bounce, join the AD5272/AD5274 ground terminal remotely to the common ground. The digital input control signals to the AD5272/AD5274 must be referenced to the device ground pin (GND) and satisfy the logic level defined in the Specifications section. An internal level shift circuit ensures that the common-mode voltage range of the three terminals extends from VSS to VDD, regardless of the digital input level. Figure 47. EXT_CAP Hardware Setup TERMINAL VOLTAGE OPERATING RANGE The positive VDD and negative VSS power supplies of the AD5272/AD5274 define the boundary conditions for proper 2-terminal digital resistor operation. Supply signals present on Terminal A and Terminal W that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 48). VDD Because there are diodes to limit the voltage compliance at Terminal A and Terminal W (see Figure 48), it is important to power VDD/VSS first before applying any voltage to Terminal A and Terminal W; otherwise, the diode is forward-biased such that VDD/VSS are powered unintentionally. The ideal power-up sequence is VSS, GND, VDD, digital inputs, VA, and VW. The order of powering VA, VW, and digital inputs is not important as long as they are powered after VDD/VSS. As soon as VDD is powered, the power-on preset activates, which first sets the RDAC to midscale and then restores the last programmed 50-TP value to the RDAC register. A VSS 08076-109 W Figure 48. Maximum Terminal Voltages Set by VDD and VSS Rev. D | Page 24 of 28 Data Sheet AD5272/AD5274 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 49. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 BOTTOM VIEW TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.30 0.25 0.20 0.05 MAX 0.02 NOM COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF Figure 50. 10-Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3mm Body, Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Rev. D | Page 25 of 28 0.20 MIN PIN 1 INDICATOR (R 0.15) 02-05-2013-C PIN 1 INDEX AREA AD5272/AD5274 Data Sheet ORDERING GUIDE Model1 AD5272BRMZ-20 AD5272BRMZ-20-RL7 AD5272BRMZ-50 AD5272BRMZ-50-RL7 AD5272BRMZ-100 AD5272BRMZ-100-RL7 AD5272BCPZ-20-RL7 AD5272BCPZ-100-RL7 AD5274BRMZ-20 AD5274BRMZ-20-RL7 AD5274BRMZ-100 AD5274BRMZ-100-RL7 AD5274BCPZ-20-RL7 AD5274BCPZ-100-RL7 EVAL-AD5272SDZ 1 RAW (kΩ) 20 20 50 50 100 100 20 100 20 20 100 100 20 100 Resolution 1,024 1,024 1,024 1,024 1,024 1,024 1,024 1,024 256 256 256 256 256 256 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Evaluation Board Z = RoHS Compliant Part. Rev. D | Page 26 of 28 Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 CP-10-9 CP-10-9 Branding DE6 DE6 DE7 DE7 DE5 DE5 DE4 DE3 DEE DEE DED DED DE9 DE8 Data Sheet AD5272/AD5274 NOTES Rev. D | Page 27 of 28 AD5272/AD5274 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08076-0-3/13(D) Rev. D | Page 28 of 28