CXA2056Q Digital CCD Camera Head Amplifier Description The CXA2056Q is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the following functions: correlated double sampling, AGC for the CCD signal, GCA for the lowband chroma signal, AMP for high-band chroma and line signals, A/D sample and hold, blanking, A/D reference voltage, and an output driver. 32 pin QFP (Plastic) Features • High sensitivity made possible by a high-gain AGC amplifier • Blanking function provided for the purpose of calibrating the CCD output signal black level • Regulator output pin provided for A/D converter reference voltage • Built-in GCA and AMP for amplifying video signals (chroma and line signals) from external sources • Built-in sample-and-hold circuits for camera signals required by external A/D converters Absolute Maximum Ratings • Supply voltage VCC • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation PD Operating Conditions Supply voltage VCC1, 2, 3 11 –20 to +75 –65 to +150 1160 3 to 3.3 V °C °C mW V Applications Digital CCD cameras Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96119A8X-PS CXA2056Q CLPDM GND1 SHD SHP VCC1 CCDLEVEL AGCCONT N.C Block Diagram and Pin Configuration 24 23 22 21 20 19 18 17 BUF SH1 SH2 PIN 25 DC SHIFT AGC 16 AGCCLP 15 CLPOB 14 XRS 13 PBLK 12 OFFSET 11 VRT 10 VRB 9 VCC3 SH3 OBSW DMSW1 DIN 26 CAM SH CDS CLP1 VCC2 27 CDS CLP2 AGC CLP DMSW2 BLK SW VREF ICONT 28 LIN CLP LISW OFFSET VB LIN/CH 29 GND2 30 CH SW LIN CH AMP 2 VISW 1 3 CVSW CAM DRV VRT VIDC SHIFT VIDEO DRV VSI VRT DRV VCENT VRB DRV VB 5 6 7 8 DRVOUT VS2 VCENT LOUTCLP CL GCA PBRFC 32 VRB LOUT CLP GND3 LOSW N.C RFCONT 31 VCENT VB 1 2 3 4 MODE1 MODE2 MODE3 PS MODE CONTROL & POWER SAVE CONTROL –2– CXA2056Q Pin Description Pin No. 1 Symbol (VCC1, 2, 3 = 3V) Pin voltage Equivalent circuit Description MODE1 50k 75k 2 Camera and video signal selector. Composite video signal and high-band chroma/low-band chroma signal selector of the video signal. For details on the selection conditions for each mode, refer to the diagram of the Electrical Characteristics Measurement Circuit. MODE2 1 VTH = 1.5V 145 1.5V 2 3 4 10µA 50k 3 MODE3 4 PS Power saving mode. 5 17 N.C No connection; normally ground. 6 23 30 GND3 GND1 GND2 Ground. GND 38k 1k 100µA 7 LOUTCLP Approx. 1.1V 12k 1.1V 2µA 22k 100µA 7 145 90k –3– Capacitor connection for LOUTCLP which clamps the output minimum level in modes which pass the composite video signal. (Recommended value: 0.1µF) CXA2056Q Pin No. Symbol Pin voltage Equivalent circuit IOFFSET 8 • Camera mode (CAM) VRB to VRB + 100mV • Composite video mode (LIN) VRB + 50mV = approx. DRVOUT 1.4V • Chroma mode (CH, CL) Center voltage = (VRT – VRB)/2 = approx. 1.85V 25µA 200µA 25µA 0 to 50µA SW1 2k VCC3 VCC1 VCC2 Driver output for A/D converter capable of DC coupling. SW1 50µA Dynamic range = 1Vp-p 50µA Mode SW1 SW2 SW3 VRT = 2.35V 5090 1.85V 4072 30k ICONT 3.2 to 6.4mA 2.4mA 145 30k 1.4 509 SW3 VRB = 1.35V SW2 SW1 VIDEO signal 8 10p VCC 0 LIN 0 1 1 CH, CL 0 1 0 0: Open 1: Closed 1.35V regulator output. Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF) 145 1.35V 0 Power supply. 200 VRB 1 48 16.5k 10 CAM CAM signal 100µA 9 20 27 Description 1.35V 10 13.5k 110µA 30k 2.35V regulator output. 30k 6.5k 145 2.35V 11 VRT 11 2.35V 23.5k 55µ 200 55µ –4– 220µ Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF) CXA2056Q Pin No. Symbol Pin voltage Equivalent circuit 50k Description 50k 2k 30k 12 OFFSET 1.5 to 3V & 0V 1.85V 1.5k 3k 25k VRB 30k 50µA 145 50µA 12 50µA 30k Active when Low only during camera mode. Calibrates the black level of the AGC output waveform. When PBLK is Low, the DRVOUT potential is forced to VRB. 145 1.85V PBLK 13 30k 50µA Active: Low 40µA VTH = 0.68V 770µA 24k 145 14 When 3V: VRB When 1.5V: VRB + 100mV When 0V (preset mode): VRB + 35mV Camera signal preblanking pulse input. 30k VTH = 1.85V 13 Controls the output offset during camera mode. 14 XRS 0.68V Camera signal sample-and-hold pulse input. 7k Sampling 97µ 30k VTH = 1.5V 30k 145 15 1.5V CLPOB 15 30k 50µA Active: Low –5– Clamp pulse used to clamp the optical black portion of the camera signal after it passes through the AGC amplifier. CXA2056Q Pin No. Symbol Pin voltage Equivalent circuit 5k Description 3k 5k 145 16 AGCCLP AGC clamp capacitor. (Recommended value: 0.1µF) 16 Approx. 1.3V 145 50k 3k 3.3k 3.3k AGC gain control. 145 18 18 AGCCONT 1.5 to 3.0V 3.4k 3.4k 2.14V ICONT 300µA 100µA 300µA 100µA 3.4k 3.4k 200µA 2.29V When 1.5V: –1dB (Minimum gain) When 3.0V: +31.5dB (Maximum gain) 200µA 100µA 19 DIN input CCD signal CCDLEVEL black level: approx. 2.2V Enables monitoring of the SH3 output camera signal. 19 500 340 21 20µA SHP VTH = 0.65V Preset level sampleand-hold pulse input. 365µA 36k 145 21 22 0.65V 22 SHD Sampling Data level sampleand-hold pulse input. 10k –6– CXA2056Q Pin No. Symbol Pin voltage Equivalent circuit 30k VTH = 1.5V 24 Description Clamp pulse used to clamp the dummy pixel portion of the input CCD signal. 145 1.5V CLPDM 24 30k 50µA Active: Low 15µA 15µA 145 2k 25 25 26 PIN DIN Black level: approx. 2.1V 26 145 23k 14k 200µA 7k CCD signal input. 2k 50µA DRVOUT output waveform rise time control. 15k 145 2.25V 28 ICONT 28 1.5 to 3V When 1.5V: Maximum rise time 6k 6k 45k When 3V: Minimum rise time 100µA 25µA 145 29 29 LIN/CH Clamp potential during LIN mode: approx. 1.46V During CH mode: approx. 1.85V 50µA 10k Common input for the composite video signal (LIN) and highband chroma signal (CH). 54k 11.5k 1.85V 30k 18.5k CH mode LIN mode 200µA 2µA 100µA VRB + 50mV –7– CXA2056Q Pin No. Symbol Pin voltage Equivalent circuit 27k Description Gain control for the low-band chroma signal (CL). 42k 145 54k 31 31 RFCONT 0.3 to 2.7V When 0.3V: –4dB (Minimum gain) When 2.7V: +12.5dB (Maximum gain) 27k 2k 2.9V 145 32 7.8k 58k 10k 32 PBRFC Approx. 1.9V 200µA 22k 10k 1.9V 100µA 38k 25µA –8– 200µA Low-band chroma signal (CL) input. CXA2056Q Electrical Characteristics Item Camera mode (Ta=25°C, VCC1, 2, 3 = 3V) Symbol IDC LINE mode IDL Max. Unit Conditions Min. Typ. AGCCONT = 1.5V, open between VRT and VRB MODE1 = 3V, MODE2 = 0V MODE3 = 0V, PS = 3V, ICONT = 3V 30 41.0 53 Open between VRT and VRB MODE1 = 0V, MODE2 = 0V, MODE3 = 0V, PS = 3V 10 13.9 19 Current consumption CH mode IDCH Open between VRT and VRB MODE1 = 0V, MODE2 = 3V, MODE3 = 3V, PS = 3V 9 12.2 17 CL mode IPCL RFCONT = 0.3V, open between VRT and VRB MODE1 = 0V, MODE2 = 3V, MODE3 = 0V, PS = 3V 9 12.2 17 PS mode IDP PS = 0V 2 3.4 6 Maximum gain A CONT max. DIN = 1µs, 20mVp-p pulse AGCCONT = 3V, ICONT = 3V 28.5 31.3 — Minimum gain A CONT min. DIN = 1µs, 500mVp-p pulse AGCCONT = 1.5V, ICONT = 3V — –0.8 1.4 27.1 32.1 — 800 895 — AGC DRV REF BLK AMP GCA SH3 Range of gain AGC G variance A CON max. – A CON min. mA Dynamic range maximum AGCmax. AGCCONT = 3V DRVOUT output signal at saturation level D Dynamic range typical AGCTYP. D AGCCONT = 2V DRVOUT output signal at saturation level 900 955 — Offset high CAOF high Camera mode OFFSET = 1.5V 80 98 — Offset low CAOF low Camera mode OFFSET = 3.0V — 2 5 Offset preset CAOF pre Camera mode OFFSET = 0V 25 34 40 VRT DC level VRTO With a 400Ω load 2300 2342 2400 VRB DC level VRBO With a 400Ω load 1300 1359 1400 VRT – VRB ∆VR With a 400Ω load 950 983 1050 Offset BLKOF BLKOF (PBLK = 3V) – BLKOF (PBLK = 0V) —10 9 23 LIN mode gain LIN G LIN/CH = 15kHz, 500mVp-p, Sine wave + offset voltage 2.5 3.43 4.5 CH mode gain CH G LIN/CH = 3MHz, 500mVp-p, sine wave 2.5 3.18 4.5 mV 9.5 12.7 — RFCONT = 0.3V CL mode RF minimum gain CONmin. 15kHz 500mVp-p sine wave — –4.0 –2.5 600 815 — SH3 D DIN = 1µs, 1Vp-p pulse –9– mV mV mV dB RFCONT = 2.7V CL mode RF maximum gain CONmax. 15kHz 80mVp-p sine wave Dynamic range dB mV CXA2056Q Electrical Characteristics Measurement Circuit 28 13 OFF ON LIN/ CH C1 0.1µF GND2 GND RFCONT PBRFC 12 29 CLPOB PL4 XRS PL5 PBLK PL6 OFFSET V6 0 to 3V VRT 11 R3 400 VRB 10 30 31 32 9 VCC3 C9 4.7µF SW6 VCC3 3V OFF ON C8 4.7µF C2 0.047µF L GND GND GND SW4 SW3 HL V3 3V C5 0.1µ H V4 3V GND R2 22 GND GND DRVOUT SW2 HL V2 3V 8 7 LOUTCLP SW1 HL V1 3V 6 5 4 3 GND3 2 N.C 1 R1 10k C6 70pF V5 1.85V GND GND SW1 SW2 SW3 SW5 SW4 L L H H L L H L H L L L H H L L H L L H H OFF ON MODE CAM H LIN CL OFF CH L – 10 – GND 14 C7 0.1µF GND 27 AGCCLP GND SHP 15 ICONT SW5 V12 0.3 to 2.7V AC V13 26 PS V10 0 to 3V 16 MODE3 AC V11 25 GND V9 1.5 to 3V 17 GND VCC2 18 GND VCC2 3V 19 GND DIN 20 V7 1.5 to 3V GND C3 1µF GND VCC1 3V PL3 21 22 MODE2 GND GND GND GND AC V8 GND GND PIN MODE1 GND C4 1µF SHD 23 24 GND N.C PL2 GND1 CLPDM PL1 GND AGCCONT GND CCDLEVEL GND VCC1 GND POWER SAVE CXA2056Q Measurement Timing Chart 1H 2µs 2.5V PL4 (CLPOB) GND 1H 2µs 2.5V PL1 (CLPDM) GND 2.5V PL6 (PBLK) GND 1H V8 (DIN) Different for each test Equivalent to CCD signal black level V11 (CH) V13 (PBRFC) V10 + V11 (LIN) Different for each test 2.5V PL2 (SHD) PL3 (SHP) PL5 (XRS) GND – 11 – CXA2056Q Application Circuit VAGCCONT 1.5 to 3V SHP DIN VCC2 GND VCC 1.5 to 3V N.C AGCCONT 18 17 25 16 26 15 27 14 28 13 29 12 30 11 31 10 ICONT 0.1µF AGCCLP CLPOB XRS PBLK VICONT LIN/CH LIN/CH VOFFSET 0 to 3V OFFSET 4.7µF VRT VRB GND 0.3 to 2.7V VRFCONT RFCONT 4.7µF PBRFC PBRFC 32 9 VCC3 VCC 0.047µF 22 0.1µF GND 3V 3V 3V GND GND GND DRVOUT 8 7 LOUTCLP 6 GND3 MODE3 MODE2 5 4 3 N.C 2 PS 1 MODE1 GND GND 0.1µF GND2 GND SHP VCC1 CCDLEVEL 19 VRB VRT A/D A/D IN 3V GND GND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 12 – GND 1µF 20 GND CCD PIN 21 22 GND 23 24 1µF SHD GND1 CLPDM VCC GND SHD GND GND CLPDM GND CLPOB GND XRS GND PBLK GND CXA2056Q Description of Operation Refer to the Block Diagram. 1. Camera signal processing system Process the video signal processing pins as follows only in camera mode. <7> LOUTCLP ... Connect to GND. <29> LIN/CH ... Connect to GND. <31> RFCONT ... Connect to GND via the capacitor (approx. 0.01µF). <32> PBRFC ... Connect to GND. Operating conditions The camera signal processing system operates when PS is High, MODE1 is Low, MODE2 is Low and MODE3 is High, or when PS is High, MODE1 is High, MODE2 is Low and MODE3 is Low. Camera signal processing system timing chart (when VCC = 3V) Sig interval Idle transfer interval OPB interval Precharge level Sig interval CCD output Signal level SHP SHD SH1 output 2.1V [∗1] [∗2] SH2 output SH3 output 2.1V CLPDM (2µ dummy bit portion during the idle transfer interval) AGC output SH3 output – SH2 output × (– N) 2µs Basic black level 0.65V Black level [∗3] XRS CLPOB (2µ during the OPB interval) 2µs CAMSH output 0.65V PBLK (10µ during the idle transfer interval) 10µs BLK SW output 1.35V [∗4] CAM DRVOUT output [∗5] Approx. VRB + 35mV when OFFSET = 0V Approx. VRB + 100mV when OFFSET = 1.5V Approx. VRB when OFFSET = 3V – 13 – CXA2056Q CDS (SH1, SH2, SH3): The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS) is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output by the SH2 output, and the signal level is sampled, held and output by the SH3 output. SH1 and SH2 are the sample-and-hold circuits for the pre-charge level; SH3 is the sample-and-hold circuit for the signal level. CDSCLP 1, 2: CDSCLP1 and 2 stabilize the input signal DC level, clamp (CLPDM) the input signal during the idle transfer interval for the purpose of eliminating the AGC input offset, and adjust the DC level ([∗1], [∗2]) of SH2 and SH3 in line with VREF. CDSCLP1 is the clamp circuit for the precharge level, and CDSCLP2 is the clamp circuit for the signal level. AGC: AGC is the gain control amplifier for the camera signal. The gain can be varied from –1 to +31dB by adjusting the AGCCONT voltage control VAGCCONT from 1.5 to 3.0V. CAM SH: CAM SH is the sample-and-hold circuit for the camera signal processing system; it synchronizes the data readin timing for the external A/D. Sampling is possible according to the approximately 10ns sampling pulse width input to XRS. AGCCLP: The basic black level is set ([*3]) by clamping the AGC output waveform with the CLPOB clock during the OPB interval. When PBLK is High and CLPOB is Low, the clamping circuit operates, adjusting the AGCCLP current so that the DRVOUT potential equals the OFFSET potential (which is determined by the voltage applied to the OFFSET pin), thus setting the AGCCLP potential. The AGCCLP capacitance is connected to the AGCCLP pin. DC SHIFT: This circuit functions when AGCCLP operates, following the AGCCLP potential and forcing a DC shift of the AGC output waveform OPB interval to the basic black level. When AGCCLP is not operating, the basic black level is maintained at its previous setting. BLK SW: The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not fall below the basic black level and replacing the DC potential with VRB. ([∗4]) The signal is blanked when PBLK is low. CVSW: When the MODE1, 2, 3 and PS pin voltages are set so that the camera signal processing system operates, CVSW conducts the CAMDRV output (camera signal) into the DRVOUT. In addition, when these voltages are set so that the video signal processing system operates, CVSW conducts the VIDEODRV output (video signal) into the DRVOUT. – 14 – CXA2056Q OFFSET: OFFSET controls the CAMDRV output waveform black level offset. In the camera signal processing system camera mode, the OFFSET pin is enabled, permitting adjustment of the offset for the [OFFSET] and DRVOUT camera signals. ([∗5]) The voltage controlled by OFFSET is output as the CAMDRV output DC offset via AGCLP, DCSHIFT, CAMSH, and BLKSW. When the OFFSET voltage is 1.5 to 3.0V, DRVOUT DC can vary in a linear fashion from VRB + 100mV to VRB. In addition, when the OFFSET voltage is 0V, DRVOUT DC is preset to VRB + 35mV. CAMDRV: CAMDRV operates in the camera signal processing system mode, driving the external A/D. The current that flows to the last-stage amplifier in CAMDRV is controlled by applying voltage to the ICONT pin, making it possible to adjust the rise time of the output waveform, which affects the external A/D load capacitance. The variable range is 1.5 to 3V, with 1.5V yielding the maximum and 3V yielding the minimum. The optimum rise time for the external A/D input capacitance can be selected. VRT DRV, VRB DRV: These are the external A/D reference voltage drivers. These circuits are connected to A/D VRT and VRB, supplying 2.35V and 1.35V, respectively, when VCC is 3V. The IC's internal primary voltage is also generated on the basis of the VRT and VRB voltages. (VRB, VB, and VCENT) MODE CONTROL & POWER SAVE CONTROL: This block selects the mode governing the operation of the camera signal system and the video signal system through the selection of High and Low potential for the MODE1, 2, 3, and PS pins. The PS pin is the POWER SAVE pin; the power saving function operates when this pin is Low. 2. Video signal processing system Operating conditions The video signal processing system has three modes: LIN signal mode, CH signal mode and CL signal mode. The video signal processing system operates in LIN signal mode when PS is High, MODE1 is High, MODE2 is Low and MODE3 is High, or when PS is High, MODE1 is Low, MODE 2 is Low and MODE3 is Low. The video signal processing system operates in CH signal mode when PS is High, MODE1 is Low, MODE2 is High and MODE3 is High. The video signal processing system operates in CL signal mode when PS is High, MODE1 is Low, MODE2 is High and MODE3 is Low, or when PS is High, MODE1 is Low, MODE2 is High and MODE3 is High. Video signal processing system timing chart (when VCC = 3V) LIN mode LIN/CH input 1.46V • LIN CHAMP output (3.5dB) • DRVOUT output 1.4V – 15 – CXA2056Q LIN signal mode In LIN signal mode, LINSW and LOSW close, VISW is set to “1” and the video signal passes through CVSW. In addition, LINCHAMP, LINCLP, LOUTCLP, VIDC SHIFT, and VIDEO DRV all operate. LINCLP: LINCLP is an input clamp circuit that clamps the video composite signal sync level. The video composite signal is input to LIN/CH pin. LINCLP expands the input dynamic range, and sync tip clamps the input signal at VB (= 1.4V) to allow full input. The input level and frequency are respectively 571mVp-p (Max.) and DC is up to 7MHz. LINCHAMP: LINCHAMP amplifies the LIN signal and the CH (high-band chroma) signal; the gain is fixed at 3.5dB. VISW: VISW switches the LIN signal, the CH (high-band chroma) signal, and the CL (low-band chroma) signal. The signals are switched according to the mode selection. LOUTCLP: LOUTCLP is an output clamp circuit that clamps the sync level of the video composite signal that is output from VIDEO DRV. Because the VIDEO DRV output signal is fully input to the external A/D, the clamp level is set to VB (= 1.4V). If the sync level of the signal output from VIDEO DRV drops below VB, LOUTCLP operates: the LOUTCLP current flows so that the sync level equals VB, and the LOUTCLP potential is set. A clamping capacitor is connected to the LOUTCLP pin. VIDC SHIFT: VIDC SHIFT functions when LOUTCLP operates, following the LOUTCLP potential and forcing a DC shift of the VIDEO output signal sync level to VB. VIDEO DRV: VIDEO DRV outputs the video signal (LIN, CH, CL) to the external A/D in video signal processing mode. – 16 – CXA2056Q CH (high-band chroma) signal mode In CH mode, CHSW closes, VISW is set to “2” and the video signal passes through CVSW. In addition, LINCHAMP and VIDEO DRV operate. VS1: The video high-band chroma signal is input to the LIN/CH pin. VS1 expands the input dynamic range and sets a center DC bias so that the center potential of the SIN signal is 1.85V to allow full input. The input level and frequency of the CH signal are respectively 470mVp-p (Max.) and from 1 to 7MHz. VCENT: VCENT is a DC bias circuit that operates when the CH signal is output to VIDEO DRV. The DC bias potential is generated from VRT and VRB, and is set to 1.85V. CH mode LIN/CH input 1.85V • LINCH AMP output (3.5dB) • DRVOUT output 1.85V – 17 – CXA2056Q CL (low-band chroma) signal mode In CL mode, VISW is set to “3” and the video signal passes through CVSW. In addition, CLGCA and VIDEO DRV operate. VS2: The video low-band chroma signal is input to the PBRFC pin. VS2 expands the input dynamic range and sets a center DC bias so that the center potential of the SIN signal is 1.9V to allow full input. The input level and frequency of the CH signal are respectively 1490mVp-p (Max.) and DC is up to 1.5MHz. CLGCA: The CLGCA amplifier controls the gain of the CL signal input to the PBRFC pin. The gain can be varied from –4 to +12.5dB by adjusting the RFCONT voltage from 0.3 to 2.7V. The phase of the CLGCA output waveform is reversed in DRVOUT. VCENT: VCENT is a DC bias circuit that operates when the CL signal is output to VIDEO DRV. The DC bias potential is generated from VRT and VRB, and is set to 1.85V. CL mode PBRFC input 1.9V • CLGCA output (–4 to +12.5dB) • DRVOUT output 1.85V – 18 – CXA2056Q Example of Representative Characteristics CAM mode AGCCONT control supply voltage characteristics VAGCCONT vs. Gain Tc = 27°C VCC = 3V VCC = 3.15V VCC = 3.3V 35 Gain [dB] 30 20 10 0 –4 1.5 2.0 2.5 3.0 3.3 VAGCCONT [V] CAM mode OFFSET control supply voltage characteristics VOFFSET vs. OFFSET 115 Tc = 27°C 100 OFFSET [mV] 80 60 40 20 VCC = 3.3V VCC = 3V (VRB =) 0 0 1.0 2.0 3.0 3.3 VOFFSET [V] CL mode RFGCA gain control supply voltage characteristics VRFCONT vs. Gain Tc = 27°C VCC = 3V VCC = 3.15V VCC = 3.3V Gain [dB] 25 20 10 0 –5 0 1.0 2.0 VRFCONT [V] – 19 – 3.0 3.3 CXA2056Q CAM mode AGCCONT control temperature characteristics AGCCONT vs. Gain VCC = 3.0V Tc = –20°C Tc = +27°C Tc = +75°C 35 Gain [dB] 30 20 10 0 –4 1.5 2.0 2.5 3.0 AGCCONT [V] CAM mode OFFSET control temperature characteristics VOFFSET vs. OFFSET VCC = 3.0V Tc = –20°C Tc = +27°C Tc = +75°C OFFSET [mV] 150 100 50 (VRB =) 0 0 1.0 2.0 3.0 VOFFSET [V] CL mode RFGCA gain control temperature characteristics VRFCONT vs. Gain VCC = 3V Tc = –20°C Tc = +27°C Tc = +75°C Gain [dB] 25 20 10 0 –5 0 0.3 1.0 2.0 VRFCONT [V] – 20 – 2.7 3.0 CXA2056Q CAM mode maximum signal amplitude temperature characteristics (Max. gain) Tc vs. Vout CAM mode maximum signal amplitude temperature characteristics (Min. gain) Tc vs. Vout VCC = 3.0V, AGCCONT = 3.0V Input amplitude DIN = 28mVp-p Input amplitude DIN = 24mVp-p Input amplitude DIN = 21mVp-p VCC = 3.0V, AGCCONT = 1.5V Input amplitude DIN = 870mVp-p Input amplitude DIN = 800mVp-p Input amplitude DIN = 750mVp-p Input amplitude DIN = 700mVp-p Input amplitude DIN = 600mVp-p 0.9 Gain temperature characteristics from –20 to +100°C DIN = 28mVp-p 0.8 1.0 30.99dB 30.99dB DIN = 24mVp-p 30.76dB +0 31.41 –0.38 dB 0.9 DIN = 870mVp-p Vout [Vp-p] Vout [Vp-p] +0 30.99 –0.23 dB DIN = 800mVp-p 0.7 DIN = 750mVp-p 31.41dB 31.41dB DIN = 21mVp-p DIN = 700mVp-p 31.03dB +0 31.45 –0.33 dB 0.8 31.45dB 31.45dB 0.75 –20 0 0.6 31.12dB 50 DIN = 600mVp-p 0.53 –20 100 50 100 Tc [°C] LIN, CH mode LINCHAMP gain temperature characteristics Tc vs. Gain LIN, CH mode LINCHAMP gain supply voltage characteristics VCC vs. Gain VCC = 3.0V LIN mode CH mode Tc = 27°C CH mode LIN mode 4 3.5 3 –20 Gain [dB] Gain [dB] 0 Tc [°C] 0 4 75 Tc [°C] 3.5 3 3 3.15 VCC [V] – 21 – 3.3 CXA2056Q CH, LIN, CL mode input pin DC voltage temperature characteristics Tc vs. DCIN 1.9 CL mode 1.85 CH mode 1.8 DCIN 1.75 1.7 VCC = 3.0V 1.65 1.6 1.55 1.5 1.45 LIN mode 1.4 –20 0 20 40 60 80 Tc [°C] 1.9 CH, LIN, CL mode DRVOUT output DC voltage temperature characteristics Tc vs. DCOUT CL mode 1.85 CH mode 1.8 DCOUT 1.75 1.7 VCC = 3.0V 1.65 1.6 1.55 1.5 1.45 LIN mode 1.4 –20 0 20 40 60 80 Tc [°C] VRT, VRB, VRT – VRB temperature characteristics Tc vs. VRT, VRB, VRT – VRB 2.4 VRT VRT, VRB, VRT – VRB [V] 2.2 2.0 VCC = 3.0V 1.8 1.6 VRB 1.4 1.2 VRT – VRB 1.0 0.8 –20 0 20 40 Tc [°C] – 22 – 60 80 CXA2056Q –35 CH mode 2nd/3rd harmonic distortion temperature characteristics Tc vs. 2nd/3rd harmonic distortion –30 VCC = 3.0V f = 5MHz 2nd/3rd Harmonic Distortion [dB] 2nd/3rd Harmonic Distortion [dB] –30 LIN mode 2nd/3rd harmonic distortion temperature characteristics Tc vs. 2nd/3rd harmonic distortion –40 2nd: out = 0.9Vp-p –45 3rd: out = 0.9Vp-p –50 –55 –60 3rd: out = 0.75Vp-p 2nd: out = 0.75Vp-p –65 –70 –75 –80 –20 0 20 40 60 –35 VCC = 3.0V f = 5MHz 2nd: out = 0.9Vp-p –45 –50 –55 –60 3rd: out = 0.75Vp-p –70 –75 0 20 Tc [°C] –40 3rd: out = 0.75Vp-p –50 –55 2nd: out = 0.3Vp-p –60 3rd: out = 0.3Vp-p –65 –70 –75 –80 –20 0 20 80 –30 VCC = 3.0V, RFCONT = 0.3V f = 700kHz 2nd: out = 0.75Vp-p –45 60 CL mode 2nd/3rd harmonic distortion temperature characteristics (Max. gain) Tc vs. 2nd/3rd harmonic distortion 2nd/3rd Harmonic Distortion [dB] 2nd/3rd Harmonic Distortion [dB] –35 40 Tc [°C] CL mode 2nd/3rd harmonic distortion temperature characteristics (Min. gain) Tc vs. 2nd/3rd harmonic distortion –30 2nd: out = 0.75Vp-p –65 –80 –20 80 3rd: out = 0.9Vp-p –40 40 60 –35 VCC = 3.0V, RFCONT = 2.7V f = 700kHz –40 –45 3rd: out = 0.75Vp-p –55 –60 –65 3rd: out = 0.3Vp-p Tc [°C] 2nd: out = 0.3Vp-p –70 –75 –80 –20 80 2nd: out = 0.75Vp-p –50 0 20 40 Tc [°C] – 23 – 60 80 CXA2056Q Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 + 0.15 0.3 – 0.1 0.24 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-32P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE QFP032-P-0707 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.2g JEDEC CODE – 24 – 0.50 8