HY5117404C,HY5116404C 4Mx4, Extended Data Out mode DESCRIPTION This family is a 16M bit dynamic RAM organized 4,194,304 x 4-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(50, 60 or 70ns) and refresh cycle(2K ref. or 4K ref.) and power consumption (Normal or Low power with self refresh). Hyundai’s advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. FEATURES Ÿ Extended data out operation Ÿ Read-modify-write Capability Ÿ TTL compatible inputs and outputs Ÿ /CAS-before-/RAS, /RAS-only, Hidden and Self refresh capability Ÿ JEDEC standard pinout Ÿ 24/26-pin Plastic SOJ (300mil) 24/26-pin Plastic TSOP-II (300mil) Ÿ Single power supply of 5V ± 10% Ÿ Early write or output enable controlled write Ÿ Max. Active power dissipation Ÿ Fast access time and cycle time Speed 2K refresh 4K refresh Speed tRAC tCAC tHPC 50 798mW 605mW 50 50ns 13ns 20ns 60 660mW 495mW 60 60ns 15ns 25ns 70 550mW 440mW 70 70ns 18ns 30ns Ÿ Refresh cycle Part number Refresh Normal HY5117404C 2K 32ms HY5116404C 4K 64ms SL-part 256ms ORDERING INFORMATION Part Name Refresh HY5117404CJ 2K HY5117404CSLJ 2K HY5117404CT 2K HY5117404CSLT 2K HY5116404CJ 4K HY5116404CSLJ 4K HY5116404CT 4K HY5116404CSLT 4K Power Package 24/26Pin SOJ SL-part 24/26Pin SOJ 24/26Pin TSOP-II SL-part 24/26Pin TSOP-II 24/26Pin SOJ SL-part 24/26Pin SOJ 24/26Pin TSOP-II SL-part 24/26Pin TSOP-II *SL : Low power with self refresh This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Hyundai Semiconductor Rev.00 / Sep.97 1 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY5117404C,HY5116404C FUNCTIONAL BLOCK DIAGRAM DQ0 DQ1 DQ2 DQ3 4 4 Data Input Buffer Data Output Buffer DQ0~3 DQ0~3 WE CAS 4 OE 4 CAS Clock Generator RAS Address Buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 *(A11) (11/10)* Cloumn Predecoder (11/10)* Column Decoder Sense Amp I/O Gate Refresh Controller Refresh Counter Row Decoder Row Predecoder (11/12)* Memory Array 4,194,304 x 4 (11/12)* RAS Clock Generator Substrate Bias Generator X16 Parallel Test *(A11) for 4K refresh part (2K Refresh / 4K Refresh)* 4Mx4,EDO DRAM Rev.00 / Sep.97 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 VCC VSS HY5117404C,HY5116404C PIN CONFIGURATION (Marking Side) VCC DQ0 DQ1 WE RAS *(N.C) A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 • 8 9 10 11 12 13 26 25 24 23 22 21 VSS DQ3 DQ2 CAS OE A9 VCC DQ0 DQ1 WE RAS *(N.C) A11 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS A10 A0 A1 A2 A3 VCC 24/26Pin Plastic SOJ (300mil) PIN DESCRIPTION Parameter /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable /OE Output Enable A0~A11 Address Input (4K Refresh Product) A0~A10 Address Input (2K Refresh Product) DQ0~DQ3 Data In/Out Vcc Power (5V) Vss Ground NC No Connection • 8 9 10 11 12 13 26 25 24 23 22 21 VSS DQ3 DQ2 CAS OE A9 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS 24/26Pin Plastic TSOP-II (300mil) (N.C)* : For 2K refresh product Pin Name 1 2 3 4 5 6 4Mx4,EDO DRAM Rev.00 / Sep.97 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY5117404C,HY5116404C ABSOLUTE MAXIMUM RATING Symbol Parameter Rating Unit TA Ambient Temperature 0 to 70 °C TSTG Storage Temperature -55 to 150 °C VIN, VOUT Voltage on Any Pin relative to VSS -1.0 to 7.0 V VCC Voltage on VCC relative to VSS -1.0 to 7.0 V IOS Short Circuit Output Current 50 mA PD Power Dissipation 1 W TSOLDER Soldering Temperature Ÿ Time 260 Ÿ 10 °C Ÿ sec Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to 70°C ) Symbol Parameter Min Typ Max UNIT VCC Power Supply Voltage 4.5 5.0 5.5 V VIH Input High Voltage 2.4 - VCC+1.0 V VIL Input Low Voltage -1.0 - 0.8 V Note : All voltages are referenced to VSS. DC OPERATING CHARACTERISTIC Symbol Parameter Test condition Min Max Unit ILI Input Leakage Current (Any input) VSS ≤ VIN ≤ VCC + 1.0 All other pins not under test = VSS -10 10 µA ILO Output Leakage Current (Any input) VSS ≤ VOUT ≤ VCC /RAS & /CAS at VIH -10 10 µA VOL Output Low Voltage IOL = 4.2mA - 0.4 V VOH Output High Voltage IOH = -5.0mA 2.4 - V 4Mx4,EDO DRAM Rev.00 / Sep.97 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY5117404C,HY5116404C DC CHARACTERISTICS (TA = 0°C to 70°C , VCC = 5V ± 10%, VSS = 0V, unless otherwise noted.) Symbol Parameter Test condition Speed Max. Current Unit 2K Ref 4K Ref 50 60 70 145 120 100 110 90 80 mA SL-part 2 1 2 1 mA ICC1 Operating Current /RAS, /CAS Cycling tRC = tRC(min.) ICC2 TTL Standby Current /RAS, /CAS ≥ VIH Other inputs ≥ VSS ICC3 /RAS-only Refresh Current /RAS Cycling,/CAS = VIH tRC = tRC(min.) 50 60 70 145 120 100 110 90 80 mA ICC4 EDO mode Current /CAS Cycling, /RAS = VIL tHPC = tHPC(min.) 50 60 70 120 100 80 90 80 70 mA ICC5 CMOS Standby Current /RAS = /CAS ≥ VCC - 0.2V SL-part 1 300 1 300 mA µA ICC6 /CAS-before-/RAS Refresh Current /RAS & /CAS = 0.2V tRC = tRC(min.) 50 60 70 145 120 100 110 90 80 mA ICC7 Battery Back-up Current (SL-part) tRC=125µs (2K Ref), 62.5µs (4K Ref) /CAS = CBR cycling or 0.2V /OE & /WE = VCC - 0.2V Address = Vcc-0.2V or 0.2V DQ0~DQ3 = Vcc-0.2, 0.2V or Open tRAS ≤ 300ns 300 300 ICC8 Self Refresh Current (SL-part) tRAS ≤ 1µs /RAS & /CAS = 0.2V Other pins are same as ICC7 µA 500 500 300 300 µA Note 1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tHPC). 2. Specified values are obtained with output unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one EDO mode cycle time tHPC. 4. Only /RAS(max.) = 1µs is applied to refresh of battery backup but tRAS(max.) = 10µs is to applied to normal functional operation. 5. Icc5(max.) = 300µA, Icc7 and Icc8 are applied to SL-part only. 4Mx4,EDO DRAM Rev.00 / Sep.97 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY5117404C,HY5116404C AC CHARACTERISTICS (TA = 0 °C to 70 °C, VCC = 5V ± 10% , VSS = 0V, unless otherwise noted.) 50ns Symbol 60ns 70ns Unit Parameter Min Max Min Max Min Max Note tRC Random read or write cycle time 84 - 104 - 124 - ns tRWC Read-modify-write cycle time 113 - 137 - 160 - ns tHPC EDO mode cycle time 20 - 25 - 30 - ns 2 tHPRWC EDO mode read-modify-write cycle time 61 - 70 - 78 - ns 2 tRAC Access time from /RAS - 50 - 60 - 70 ns 5,6,7 tCAC Access time from /CAS - 13 - 15 - 18 ns 5,6 tAA Access time from column address - 25 - 30 - 35 ns 5 tCPA Access time from column precharge - 30 - 35 - 40 ns 5 tCLZ /CAS to output low impedance 3 - 3 - 3 - ns 5 tCEZ Output buffer turn-off delay from /CAS 3 13 3 15 3 18 ns 8 tT Transition time(rise and fall) 2 50 2 50 2 50 ns 3 tRP /RAS precharge time 30 - 40 - 50 - ns tRAS /RAS pulse width 50 10K 60 10K 70 10K ns tRASP /RAS pulse width(EDO mode) 50 200K 60 200K 70 200K ns tRSH /RAS hold time 13 - 15 - 18 - ns tCSH /CAS hold time 40 - 45 - 50 - ns tCAS /CAS pulse width 8 10K 11 10K 14 10K ns tRCD /RAS to /CAS delay time 18 37 20 45 20 52 ns 6 tRAD /RAS to column address delay time 10 25 15 30 15 35 ns 7 tCRP /CAS to /RAS precharge time 5 - 5 - 5 - ns 11 tCP /CAS precharge time 8 - 10 - 12 - ns tASR Row address set-up time 0 - 0 - 0 - ns tRAH Row address hold time 8 - 10 - 10 - ns tASC Column address set-up time 0 - 0 - 0 - ns tCAH Column address hold time 10 - 10 - 10 - ns tRAL Column address to /RAS lead time 25 - 30 - 35 - ns tRCS Read command set-up time 0 - 0 - 0 - ns tRCH Read command hold time referenced to /CAS 0 - 0 - 0 - ns 9 tRRH Read command hold time referenced to /RAS 0 - 0 - 0 - ns 9 tWCH Write command hold time 8 - 10 - 10 - ns tWP Write command pulse width 8 - 10 - 10 - ns tRWL Write command to /RAS lead time 10 - 12 - 12 - ns tCWL Write command to /CAS lead time 10 - 12 - 12 - ns 4Mx4,EDO DRAM Rev.00 / Sep.97 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY5117404C,HY5116404C AC CHARACTERISTICS Continued 50ns Symbol 60ns 70ns Parameter tDS Data-in set-up time tDH Data-in hold time Unit Note - ns 10 10 - ns 10 Min Max Min Max Min Max 0 - 0 - 0 - 10 - Refresh period(2048 cycles) - 32 - 32 - 32 ms Refresh period(4096 cycles) - 64 - 64 - 64 ms Refresh period(SL-part) - 256 - 256 - 256 ms tWCS Write command set-up time 0 - 0 - 0 - ns 11 tCWD /CAS to /WE delay time 30 - 34 - 40 - ns 11 tRWD /RAS to /WE delay time 67 - 79 - 92 - ns 11 tAWD Column address to /WE delay time 42 - 49 - 57 - ns 11 tCSR /CAS set-up time(CBR cycle) 5 - 5 - 5 - ns tCHR /CAS hold time(CBR cycle) 10 - 10 - 10 - ns tRPC /RAS to /CAS precharge time 5 - 5 - 5 - ns tCPT /CAS precharge time(CBR counter test) 15 - 20 - 25 - ns tROH /RAS hold time referenced to /OE 10 - 10 - 10 - ns tOEA /OE access time - 13 - 15 - 18 ns tOED /OE to data delay time 13 - 15 - 18 - ns tOEZ Output buffer turn-off delay time from /OE 3 13 3 15 3 18 ns tOEH /OE command hold time 13 - 15 - 18 - ns tCPWD /WE delay time from /CAS precharge 47 - 54 - 62 - ns tRHCP /RAS hold time from /CAS precharge 30 - 35 - 40 - ns tWRP /WE to /RAS precharge time(CBR cycle) 10 - 10 - 10 - ns tWRH /WE to /RAS hold time(CBR cycle) 10 - 10 - 10 - ns tRASS /RAS pulse width(self refresh) 100K - 100K - 100K - ns tRPS /RAS Precharge Time (Self refresh) 90 - 110 - 130 - ns tCHS /CAS Hold Time (Self refresh) -50 - -50 - -50 - ns tDOH Output Data Hold Time 5 - 5 - 5 - ns tREZ Output Buffer Turn Off Delay Time from /RAS 3 13 3 15 3 18 ns tWEZ Output Buffer Turn Off Delay Time from /WE 3 13 3 15 3 18 ns tWED /WE to Data Delay Time 13 - 15 - 18 - ns tOEP /OE Precharge Time 5 - 5 - 5 - ns tWPE /WE Pulse Width (EDO cycle) 5 - 5 - 5 - ns tOCH /OE to /CAS Hold Time 5 - 5 - 5 - ns tCHO /CAS Hold Time to /OE 5 - 5 - 5 - ns tREF 4Mx4,EDO DRAM Rev.00 / Sep.97 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 11 HY5117404C,HY5116404C TEST MODE 50ns Symbol 60ns 70ns Parameter Unit Min Max Min Max Min Max Note tRC Random read or write cycle time 89 - 109 - 129 - ns tRWC Read-modify-write cycle time 118 - 142 - 165 - ns tHPC EDO mode cycle time 25 - 30 - 35 - ns 2 tHPRWC EDO mode read-modify-write cycle time 66 - 75 - 83 - ns 2 tRAC Access time from /RAS - 55 - 65 - 75 ns 5,6,7 tCAC Access time from /CAS - 18 - 20 - 23 ns 5,6 tAA Access time from column address - 30 - 35 - 40 ns 5,7 tCPA Access time from column precharge - 35 - 40 - 45 ns 5 tRAS /RAS pulse width 55 10K 65 10K 75 10K ns tRASP /RAS pulse width(EDO mode) 55 200K 65 200K 75 200K ns tRSH /RAS hold time 18 - 20 - 23 - ns tCSH /CAS hold time 45 - 50 - 55 - ns tCAS /CAS pulse width 13 10K 16 10K 19 10K ns tRAL Column address to /RAS lead time 30 - 35 - 40 - ns tCWD /CAS to /WE delay time 35 - 39 - 45 - ns 11 tRWD /RAS to /WE delay time 72 - 84 - 97 - ns 11 tAWD Column address to /WE delay time 47 - 54 - 62 - ns 11 tOEA /OE access time - 18 - 20 - 23 ns tOED /OE to data delay Time 18 - 20 - 23 - ns tOEH /OE command hold time 18 - 20 - 23 - ns tCPWD /WE delay time from /CAS precharge 52 - 59 - 67 - ns 11 In test mode, data are written into 16 sectors (each is composed of 1M bits) in parallel and retrieved the same way. Column address A0 and A1 are not used. If, upon reading, 4-bit data from 4sectors connected to one DQ pin are equal (all `1`s or `0`s), the DQ pin indicates a `1`. If they are not equal, the DQ indicates a `0`. The 4Mx4 DRAM can be tested in the same way as a 1Mx4 DRAM is tested. /WE (when in /CAS-before-/RAS cycle) puts the 4Mx4 DRAM into Test Mode and a /CAS-before-/RAS or a /RAS-only refresh cycle put it back into Normal Mode. /WE (when in /CAS-before-/RAS cycle) shall be used for the refresh operation in the test mode. The test mode function reduces test time(1/4 in case of N test pattern). 4Mx4,EDO DRAM Rev.00 / Sep.97 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY5117404C,HY5116404C NOTE 1. An initial pause of 200µs is required after power-up followed by 8 /RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of 8 /RAS-only refresh cycles are required. 2 tASC ≥ tCP(min), assume tT=2ns. 3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.) 4. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (TA=0 to 70¡ ÆC) is assured. 5. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 100pF. 6. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 7. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 8. tWEZ, tREZ, tCEZ and tOEZ define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10.These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in read-modify-write cycles. 11.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min), and tCPWD ≥ tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 12.If /RAS goes to high before /CAS high going,the open circuit condition of the output is achieved by /CAS high going. If /CAS goes to high before /RAS high going,the open circuit condition of the output is achieved by /RAS high going. CAPACITANCE (TA = 25°C, VCC = 5V ± 10%, VSS = 0V and f=1MHz, unless otherwise noted.) Symbol Parameter Typ. Max Unit CIN1 Input Capacitance (A0~A11) - 5 pF CIN2 Input Capacitance (/RAS, /CAS, /WE, /OE) - 7 pF CDQ Data Input / Output Capacitance (DQ0~DQ3) - 7 pF 4Mx4,EDO DRAM Rev.00 / Sep.97 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003