ICS ICS9248-95

ICS9248-95
Integrated
Circuit
Systems, Inc.
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9248-95 is the single chip clock solution for Desktop
designs using the VIA MVP4 style chipset. It provides all
necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-95
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Features
•
•
•
•
•
Block Diagram
•
Up to 124MHz frequency support.
Spread Spectrum for EMI control ±0.5% center
spread and ±0.25% center spread
Serial I2C interface for Power Management,
Frequency Select, Spread Spectrum.
Provides the following system clocks
- 4-CPUs @ 3.3V, up to 124MHz.
- 13-SDRAMs @3.3V, up to 124MHz
(including SDRAM_F)
- 6-PCI @3.3V, CPU/2 or CPU/3
(including PCICLK_F)
(including 1 free running).
- 1-24MHz @3.3V fixed.
- 1-48MHz @3.3V fixed.
- 2-REF @3.3V, 14.318MHz.
Efficient Power management scheme through PCI
and STOP CLOCKS.
Spread Spectrum ±.25%, & ±.5% center spread
Pin Configuration
48-Pin SSOP
* Internal Pull-up Resistor of 240K to VDD
Power Groups
VDDCPU, GNDCPU = CPUCLK [2:0], CPUCLK_F
VDDSDR, GNDSDR = SDRAMCLKS [11:0], SDRAM_F
VDDPCI, GNDPCI = PCICLKS [4:0], PCICLK_F
VDD48 = 48MHz, 24MHz
VDDREF, GNDREF = REF, X1, X2
310D—04/12/05
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS9248-95
Pin Descriptions
PIN NUMBER
1
P I N NA M E
VDDREF
REF0
TYPE
PWR
OUT
2
PCI_STOP#1
3,9,16,22,
33,40,44
4
5
6,14
GND
X1
IN
PWR
IN
X2
VDDPCI
OUT
PWR
PCICLK_F
OUT
7
8
13, 12, 11, 10
MODE1, 2
IN
FS31
IN
PCICLK0
OUT
PCICLK [4:1]
OUT
15
BUFFER IN
17
SDRAM11
18, 20, 21, 28, 29,
31, 32, 34, 35, 37, SDRAM [10:0]
38
19,30,36
VDDSDR
23
SDATA
24
SCLK
25
26
IN
OUT
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER
buffer for ISA BUS loads
Halts PCICLK [4:1]clocks at logic 0 level, when input low (In
mobile mode, MODE=0)
Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz.
Supply for PCICLK_F and PCICLK [4:0], nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power
management.
Pin 17, pin 2 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
Frequency select pin. Latched Input.
PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew
(CPU early)
PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew
(CPU early)
Input to Fanout Buffers for SDRAM outputs.
SDRAM clock output Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
PWR
IN
IN
Supply for SDRAM [11:0] and CPU PLL Core, nominal 3.3V.
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
24MHz
OUT
24MHz output clock
FS11, 2
IN
48MHz
OUT
FS01, 2
IN
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
27
VDD48
PWR
Power for 24 & 48MHz output buffers and fixed PLL core.
39
SDRAM_F
OUT
41
CLK_STOP#
42, 43, 45
46
47
48
CPUCLK [2:0]
OUT
Free running SDRAM clock output. Not affected by CPU_STOP#
This asynchronous input halts CPUCLK & SDRAM (0:11) at logic
"0" level when driven low.
CPU clock outputs, powered by VDDCPU
CPUCLK_F
VDDCPU
REF1
FS21, 2
OUT
PWR
OUT
IN
Free running CPU clock. Not affected by the CPU_STOP#
Supply for CPU clocks, 3.3V nominal
14.318 MHz reference clock.
Frequency select pin. Latched Input
IN
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
310D—04/12/05
2
ICS9248-95
Mode Pin - Power Management Input Control
MODE
(Latched Input)
PCI_STOP#
(Input)
REF0
(Output)
0
1
Functionality
VDD1,2,3 = 3.3V±5%, VDDL1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
124.00
120.00
114.99
109.99
105.00
83.31
80.00
75.00
100.00
95.19
83.31
80.00
90.00
70.00
66.82
60.00
PCI
(MHz)
41.33
40.00
38.33
36.66
35.00
41.65
40.00
37.50
33.33
31.73
27.77
26.67
30.00
35.00
33.41
30.00
310D—04/12/05
3
ICS9248-95
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ICS (Slave/Receiver)
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
310D—04/12/05
4
ICS9248-95
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Bit
[2, 6:4]
Bit 3
Bit 1
Bit 0
Description
0 - ±0.25% Spread Spectrum Modulation
1 - ±0.5% Spread Spectrum Modulation
CPUCLK
PCICLK
Bit [2, 6:4]
(MHz)
(MHz)
0000
124.00
41.33
0001
120.00
40.00
0010
114.99
38.33
0011
109.99
36.66
0100
105.00
35.00
0101
83.31
41.65
0110
80.00
40.00
0111
75.00
37.50
1000
100.00
33.33
1001
95.19
31.73
1010
83.31
27.77
1011
80.00
32.33
1100
90.00
30.00
1101
70.00
35.00
1110
66.82
33.41
1111
60.00
30.00
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit [2, 6:4]
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Note 1. Default at Power-up will be for latched logic inputs to define frequency.
Bit [2, 6:4] are default to 0000.
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
310D—04/12/05
5
PWD
1
Note1
0
1
0
ICS9248-95
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
46
39
42
43
45
PWD
X
1
1
1
1
1
1
1
Description
Latched FS2#
CPUCLK_F (Act/Inact)
(Reserved)
(Reserved)
SDRAM_F (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
7
13
12
11
10
8
PWD
X
1
1
1
1
1
1
1
Description
Latched FS0#
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
17
18
20
21
28
29
31
32
PW D
1
1
1
1
1
1
1
1
Description
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
310D—04/12/05
6
ICS9248-95
Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
PWD
1
1
1
1
X
1
X
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Latched FS1#
(Reserved)
Latched FS3#
(Reserved)
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
34
35
37
38
26
25
48
2
PWD
1
1
1
1
1
1
1
1
Description
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
48MHz (Act/Inact)
24MHz (Act/Inact)
REF1 (Act/Inact)
REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
310D—04/12/05
7
ICS9248-95
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS9248-95. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-95.
3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-95
CLK_STOP# signal. SDRAM (0:11) are controlled as shown.
5. All other clocks continue to run undisturbed.
310D—04/12/05
8
ICS9248-95
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-95. It is used to turn off the PCICLK [4:0] clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-95 internally. The minimum that the PCICLK [4:0] clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK [4:0] clocks. PCICLK [4:0] clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK [4:0] clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
310D—04/12/05
9
ICS9248-95
Shared Pin Operation Input/Output Pins
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
The I/O pins designated by (input/output) on the ICS924895 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 4-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the device’s
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
310D—04/12/05
10
ICS9248-95
Fig. 2a
Fig. 2b
310D—04/12/05
11
ICS9248-95
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . .
5.5 V
GND –0.5 V to VDD +0.5 V
0°C to +70°C
115°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Supply Current
Input frequency
Input Capacitance1
Transition Time1
Clk Stabilization
Skew1
1
1
SYMBOL
VIH
VIL
IDD
IDDL
Fi
VDD = 3.3 V;
MAX UNITS
VDD+0.3
V
0.8
V
77
180
mA
6.0
30
mA
14.318
MHz
C IN
CINX
Logic Inputs
X1 & X2 pins
36
5
45
pF
pS
Ttrans
To 1st crossing of target Freq.
1.5
3
mS
3
mS
4.0
nS
TSTAB
TCPU-BUS
CONDITIONS
MIN
2
VSS-0.3
CL = 0 pF; Select @ 66M
27
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V;
Guarenteed by design, not 100% tested in production.
310D—04/12/05
12
1.0
TYP
2.2
ICS9248-95
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
1
Output Impedance
RDSP2A
VO = VDD*(0.5) Output P
Output Impedance
RDSN2A1
VO = VDD*(0.5) Output N
Output High Voltage
VOH2B
IOH = -12.0 mA
Output Low Voltage
VOL2B
IOL = 12 mA
Output High Current
IOH2B
VOH = 1.7 V
Output Low Current
IOL2B
VOL = 0.7 V
1
Rise Time
tr2A
VOL = 0.4 V, VOH = 2.4 V
1
Fall Time
tf2A
VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
dt2A1
VT = 1.25 V
1
Skew (Window)
tsk2A
VT = 1.25 V
tc-c1
VT = 1.25 V
1
tj1s
VT = 1.25 V
1
tjabs
VT = 1.25 V
Jitter
MIN
10
10
2
19
0.4
0.4
45.0
TYP
2.3
0.2
-41
37
1.0
51.0
120
250
208
MAX UNITS
20
Ω
20
Ω
V
0.4
V
-19
mA
mA
2.0
nS
2.0
nS
55.0
%
250
pS
300
pS
150
pS
250
pS
1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 24M, 48M, REF 1
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Jitter
RDSP5
VO = VDD*(0.5)
20
1
VO = VDD*(0.5)
IOH = -14 mA
IOL = 6.0 mA
VOH = 2.0 V
VOL = 0.8 V
20
2.4
RDSN5
VOH5
VOL5
IOH5
IOL5
10
TYP
2.9
0.25
-42
18
MAX UNITS
60
Ω
60
Ω
V
V
mA
mA
0.4
-20
tr5
1
VOL = 0.4 V, VOH = 2.4 V
4.0
nS
tf5
1
VOH = 2.4 V, VOL = 0.4 V
4.0
nS
1
VT = 1.5 V
50.0
55.0
%
dt5
tj1s5
45.0
1
VT = 1.5 V
100
250
pS
1
VT = 1.5 V
250
800
pS
tjabs5
1
MIN
1
Guarenteed by design, not 100% tested in production.
310D—04/12/05
13
ICS9248-95
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
1
Output Impedance
RDSP1
VO = VDD*(0.5)
12
1
Output Impedance
RDSN1
VO = VDD*(0.5)
12
Output High Voltage
VOH1
IOH = -18 mA
2.4
Output Low Voltage
VOL1
IOL = 9.4 mA
Output High Current
IOH1
VOH = 2.0 V
Output Low Current
IOL1
VOL = 0.8 V
25
1
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
1
Duty Cycle
dt1
VT = 1.5 V
45.0
1
Skew Window
tsk1
VT = 1.5 V
1
Jitter
tj1s1
VT = 1.5 V
1
tjabs1
VT = 1.5 V
1
TYP
23
20
2.9
0.2
-58
52
1.5
1.4
50.0
80
50
200
MAX
55
55
0.4
-22
2.0
2.0
55.0
500
150
500
UNITS
Ω
Ω
V
V
mA
mA
nS
nS
%
pS
pS
pS
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD =VDDL 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
1
Output Impedance
RDSP2A
VO = VDD*(0.5)
1
Output Impedance
RDSN2A
VO = VDD*(0.5)
IOH = -28 mA
Output High Voltage
VOH2A
IOL = 19 mA
Output Low Voltage
VOL2A
VOH = 2.0 V
Output High Current
IOH2A
VOL = 0.8 V
Output Low Current
IOL2A
1
Rise Time
tr2A
VOL = 0.4 V, VOH = 2.4 V
1
Fall Time
tf2A
VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
dt2A1
VT = 1.5 V
1
Skew Window ( output to output )
tsk2A
VT = 1.5 V
tsk2A1
VT = 1.5 V
Skew ( Bufferin to output )
1
Guarenteed by design, not 100% tested in production.
310D—04/12/05
14
MIN
10
10
2.4
33
0.5
0.5
45
TYP
2.8
0.3
-72
50
50
200
MAX UNITS
20
Ω
20
Ω
V
0.4
V
-42
mA
mA
2.0
nS
2
nS
55
%
250
pS
5
nS
ICS9248-95
SYMBOL
A
A1
A2
B
C
D
E
e
H
h
L
N
∝
X
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095
.101
.110
.008
.012
.016
.088
.090
.092
.008
.010
.0135
.005
.010
See Variations
.299
.292
.296
0.025 BSC
.400
.406
.410
.010
.013
.016
.024
.032
.040
See Variations
0°
5°
8°
.085
.093
.100
VARIATIONS
AC
MIN.
.620
D
NOM.
.625
N
MAX.
.630
48
SSOP Package
Ordering Information
ICS9248yF-95LF
Example:
ICS XXXX y F - PPP LF
Annealed Lead Free (optional)
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
310D—04/12/05
Prefix
ICS, AV = Standard Device
15
ICS9248-95
Revision History
Rev.
C
Issue Date Description
4/4/2005 1. Updated CPU,PCI, and SDRAM Electrical Characteristics.
1. Updated Electrical Characteristics for Input/Output Parameters, CPU and SDRAM.
Page #
13-14
2. Added Lead Free option.
D
4/12/2005 3. Datasheet Release.
12-15
310D—04/12/05
16