ICS950223 Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for P4™ Pin Configuration *MULTSEL1/REF1 1 48 REF0/MULTSEL0** 47 GNDREF VDDREF 2 X1 3 46 VDDCPU 45 CPUCLKT2 X2 4 GND 5 44 CPUCLKC2 43 GNDCPU 42 PD#* *FS2/PCICLK0 6 *FS3/PCICLK1 7 VDDPCI 9 *FS4/PCICLK3 10 PCICLK4 11 PCICLK5 12 GND 13 PCICLK6 14 Features/Benefits: • QuadRomTM frequency selection. • Programmable output frequency. • Programmable asynchronous 3V66 & PCI frequency. • Programmable output divider ratios. • Programmable output rise/fall time. • Programmable output skew. • Programmable spread percentage for EMI control. • Watchdog timer technology to reset system if system malfunctions. • Programmable watchdog safe frequency. • Support I2C Index read/write and block read/write operations. • Uses external 14.318MHz reference input. Key Specifications: • CPU Output Jitter <150ps • 3V66 Output Jitter <250ps • CPU Output Skew <100ps Block Diagram PLL2 X1 X2 XTAL OSC 48MHz 24_48MHz /2 REF (1:0) 3V66_48MHz 3V66 DIVDER PLL1 Spread Spectrum CPU DIVDER 3 PCI DIVDER PD# MULTSEL(1:0) FS (4:0) SDATA SCLK Vtt_PWRGD# SEL 48_24# SEL 66_48# 0496C—05/06/05 Control Logic Config. Reg. 3 3V66 DIVDER 10 4 CPUCLKT (2:0) CPUCLKC (2:0) PCICLK (9:0) 3V66 (2:0) RESET# I REF 41 CPUCLKT0 40 CPUCLKC0 39 VDDCPU **SEL48_24#/PCICLK2 8 ICS950223 Recommended Application: Brookdale and Brookdale-G chipset with P4 processor. Output Features: • 3 - Pairs of differential CPU clocks (differential current mode) • 3 - 3V66 @ 3.3V • 10 - PCI @ 3.3V • 1 - 48MHz @ 3.3V fixed • 2 - REF @ 3.3V, 14.318MHz • 1 - 48_66MHz selectable @ 3.3V fixed • 1 - 24_48MHz selectable @ 3.3V 38 CPUCLKT1 37 CPUCLKC1 36 GNDCPU 35 IREF 34 AVDD 33 GND PCICLK7 15 PCICLK8 16 32 VDD3V66 31 3V66_0 30 3V66_1 PCICLK9 17 VDDPCI 18 Vttpwr_GD# 19 29 GND 28 3V66_2 27 3V66_3_48MHz/Sel66_48#** RESET# 20 GND 21 ~ *FS0/48MHz 22 *FS1/24_48MHz 23 26 SCLK AVDD48 24 25 SDATA 48-SSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive strength Frequency Table Bit4 FS4 Bit3 FS3 Bit2 FS2 Bit1 FS1 Bit0 FS0 CPU MHz 3V66 MHz PCI MHz 0 0 0 0 0 102.00 68.00 34.00 0 0 0 0 1 105.00 70.00 35.00 0 0 0 1 0 108.00 72.00 36.00 0 0 0 1 1 111.00 74.00 37.00 0 0 1 0 0 114.00 76.00 38.00 0 0 1 0 1 117.00 78.00 39.00 0 0 1 1 0 120.00 80.00 40.00 0 0 1 1 1 123.00 82.00 41.00 0 1 0 0 0 126.00 72.00 36.00 0 1 0 0 1 130.00 74.29 37.14 0 1 0 1 0 136.00 68.00 34.00 0 1 0 1 1 140.00 70.00 35.00 0 1 1 0 0 144.00 72.00 36.00 0 1 1 0 1 148.00 74.00 37.00 0 1 1 1 0 152.00 76.00 38.00 0 1 1 1 1 156.00 78.00 39.00 1 0 0 0 0 160.00 80.00 40.00 1 0 0 0 1 164.00 82.00 41.00 1 0 0 1 0 166.60 66.64 33.32 1 0 0 1 1 170.00 68.00 34.00 1 0 1 0 0 175.00 70.00 35.00 1 0 1 0 1 180.00 72.00 36.00 1 0 1 1 0 185.00 74.00 37.00 1 0 1 1 1 190.00 76.00 38.00 1 1 0 0 0 66.80 66.80 33.40 1 1 0 0 1 100.20 66.80 33.40 1 1 0 1 0 133.60 66.80 33.40 1 1 0 1 1 200.40 66.80 33.40 1 1 1 0 0 66.67 66.67 33.34 1 1 1 0 1 100.00 66.67 33.33 1 1 1 1 0 200.00 66.67 33.33 1 1 1 1 1 133.33 66.67 33.33 ICS950223 Integrated Circuit Systems, Inc. General Description The ICS950223 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR memory. It provides all necessary clock signals for such a system. The ICS950223 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple. Pin Description PIN PIN PIN # NAME TYPE 1 *MULTSEL1/REF1 2 3 4 5 6 7 VDDREF X1 X2 GND *FS2/PCICLK0 *FS3/PCICLK1 8 **SEL48_24#/PCICLK2 I/O 9 10 11 12 13 14 15 16 17 18 VDDPCI *FS4/PCICLK3 PCICLK4 PCICLK5 GND PCICLK6 PCICLK7 PCICLK8 PCICLK9 VDDPCI PWR I/O OUT OUT PWR OUT OUT OUT OUT PWR 19 Vttpwr_GD# 20 RESET# GND ~*FS0/48MHz *FS1/24_48MHz AVDD48 21 22 23 24 DESCRIPTION 3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference clock. PWR Ref, XTAL power supply, nominal 3.3V IN Crystal input, Nominally 14.318MHz. OUT Crystal output, Nominally 14.318MHz PWR Ground pin. I/O Frequency select latch input pin / 3.3V PCI clock output. I/O Frequency select latch input pin / 3.3V PCI clock output. I/O Latched select input for 48/24MHz output. 0=24MHz, 1 = 48MHz / 3.3V PCI clock output. Power supply for PCI clocks, nominal 3.3V Frequency select latch input pin / 3.3V PCI clock output. PCI clock output. PCI clock output. Ground pin. PCI clock output. PCI clock output. PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are IN valid and are ready to be sampled. This is an active low input. Real time system reset signal for frequency gear ratio change or watchdog timer timeout. OUT This signal is active low. PWR Ground pin. I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V I/O Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V. PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive 0496C—05/06/05 2 Integrated Circuit Systems, Inc. ICS950223 Pin Description (Continued) PIN PIN # NAME PIN 25 SDATA 26 SCLK I/O IN 27 3V66_3_48MHz/Sel66_48#** I/O 28 29 30 31 32 33 34 3V66_2 GND 3V66_1 3V66_0 VDD3V66 GND AVDD OUT PWR OUT OUT PWR PWR PWR 35 IREF OUT 36 GNDCPU PWR 37 CPUCLKC1 OUT 38 CPUCLKT1 OUT 39 VDDCPU PWR 40 CPUCLKC0 OUT 41 CPUCLKT0 OUT 42 PD#* IN 43 GNDCPU PWR 44 CPUCLKC2 OUT 45 CPUCLKT2 OUT 46 VDDCPU 47 GNDREF PWR PWR 48 REF0/MULTSEL0** DESCRIPTION TYPE I/O Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant Selectable 66.66MHz, 48MHz clock output / Select input for 66.66/48MHz output. 0=48mHz, 1 = 66.66MHz 3.3V 66.66MHz clock output Ground pin. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Power pin for the 3V66 clocks. Ground pin. 3.3V Analog Power pin for Core PLL This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the CPU outputs "Complimentary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal "Complimentary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. Ground pin for the CPU outputs "Complimentary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Ground pin for the REF outputs. 3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference clock. * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive 0496C—05/06/05 3 ICS950223 Integrated Circuit Systems, Inc. Maximum Allowed Current Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND Condition Powerdown Mode (PWRDWN# = 0) 40mA Full Active 360mA CPUCLK Swing Select Functions MULTSEL0 MULTSEL1 Board Target Trace/Term Z 0 0 60 ohms 0 0 50 ohms 0 1 60 ohms 0 1 50 ohms 1 0 60 ohms 1 0 50 ohms 1 1 60 ohms 1 1 50 ohms 0 0 30 (DC equiv) 0 0 25 (DC equiv) 0 1 30 (DC equiv) 0 1 25 (DC equiv) 1 0 30 (DC equiv) 1 0 25 (DC equiv) 1 1 30 (DC equiv) 1 1 25 (DC equiv) Reference R, Iref= Vdd/(3*Rr) Output Current Voh @ Z, Iref=2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Ioh = 5*Iref 0.71V @ 60 Ioh = 5*Iref 0.59V @ 50 Ioh = 6*Iref 0.85V /2 60 Rr = 475 1% Iref = 2.32mA Ioh = 6*Iref 0.71V @ 50 Ioh = 4*Iref 0.56V @ 60 Ioh = 4*Iref 0.47V @ 50 Ioh = 7*Iref 0.99V @ 60 Ioh = 7*Iref 0.82V @ 50 Ioh = 5*Iref 0.75V @ 30 Ioh = 5*Iref 0.62V @ 20 Ioh = 6*Iref 0.90V @ 30 Ioh = 6*Iref 0.75V @ 20 Ioh = 4*Iref 0.60 @ 20 Ioh = 4*Iref 0.5V @ 20 Ioh = 7*Iref 1.05V @ 30 Ioh = 7*Iref 0.84V @ 20 Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA 0496C—05/06/05 4 Integrated Circuit Systems, Inc. ICS950223 General I2C serial interface information How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P *See notes on the following page. 0496C—05/06/05 5 Not acknowledge stoP bit ICS950223 Integrated Circuit Systems, Inc. Table1: QuadRom Frequency Selection Table Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 X X FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1 CPU MHz 102.00 105.00 108.00 111.00 114.00 117.00 120.00 123.00 126.00 130.00 136.00 140.00 144.00 100.99 134.66 133.99 160.00 164.00 166.60 170.00 175.00 180.00 185.00 190.00 66.80 100.20 200.40 133.60 66.67 100.00 200.00 133.33 3V66 MHz 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 72.00 74.29 68.00 70.00 72.00 67.32 67.32 67.00 80.00 82.00 66.64 68.00 70.00 72.00 74.00 76.00 66.80 66.80 66.80 66.80 66.67 66.67 66.67 66.67 0496C—05/06/05 6 PCI MHz 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 36.00 37.14 34.00 35.00 36.00 33.66 33.66 35.00 40.00 41.00 33.32 34.00 35.00 36.00 37.00 38.00 33.40 33.40 33.40 33.40 33.34 33.33 33.33 33.33 Spreading Spread Off Spread Off Spread Off Spread Off Spread Off Spread Off Spread Off Spread Off Spread Off Spread Off Spread Off Spread Off Spread Off Center Spread Center Spread Center Spread Spread Off Spread Off Center Spread Spread Off Spread Off Spread Off Spread Off Spread Off Center Spread Center Spread Center Spread Center Spread Down Spread Down Spread Down Spread Down Spread Integrated Circuit Systems, Inc. Table1: QuadRom Frequency Selection Table Continued Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CPU MHz X X FS4 FS3 FS2 FS1 FS0 0 1 0 0 0 0 0 114.00 0 1 0 0 0 0 1 115.00 0 1 0 0 0 1 0 116.00 0 1 0 0 0 1 1 117.00 0 1 0 0 1 0 0 118.00 0 1 0 0 1 0 1 119.00 0 1 0 0 1 1 0 120.00 0 1 0 0 1 1 1 121.00 0 1 0 1 0 0 0 122.00 0 1 0 1 0 0 1 123.00 0 1 0 1 0 1 0 125.00 0 1 0 1 0 1 1 127.00 0 1 0 1 1 0 0 129.00 0 1 0 1 1 0 1 131.00 0 1 0 1 1 1 0 133.00 0 1 0 1 1 1 1 135.00 0 1 1 0 0 0 0 152.00 0 1 1 0 0 0 1 153.00 0 1 1 0 0 1 0 154.00 0 1 1 0 0 1 1 155.00 0 1 1 0 1 0 0 156.00 0 1 1 0 1 0 1 157.00 0 1 1 0 1 1 0 158.00 0 1 1 0 1 1 1 159.00 0 1 1 1 0 0 0 160.00 0 1 1 1 0 0 1 161.00 0 1 1 1 0 1 0 162.00 0 1 1 1 0 1 1 163.00 0 1 1 1 1 0 0 164.00 0 1 1 1 1 0 1 165.00 0 1 1 1 1 1 0 144.00 0 1 1 1 1 1 1 148.00 ICS950223 3V66 MHz 76.00 76.67 77.33 78.00 78.67 79.33 80.00 80.67 81.33 82.00 83.33 84.67 86.00 87.33 88.67 90.00 76.00 76.50 77.00 77.50 78.00 78.50 79.00 79.50 80.00 80.50 81.00 81.50 82.00 82.50 72.00 74.00 0496C—05/06/05 7 PCI MHz 38.00 38.33 38.67 39.00 39.33 39.67 40.00 40.33 40.67 41.00 41.67 42.33 43.00 43.67 44.33 45.00 38.00 38.25 38.50 38.75 39.00 39.25 39.50 39.75 40.00 40.25 40.50 40.75 41.00 41.25 36.00 37.00 ICS950223 Integrated Circuit Systems, Inc. Table1: QuadRom Frequency Selection Table Continued Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CPU MHz X X FS4 FS3 FS2 FS1 FS0 1 0 0 0 0 0 0 66.67 1 0 0 0 0 0 1 68.00 1 0 0 0 0 1 0 70.00 1 0 0 0 0 1 1 72.00 1 0 0 0 1 0 0 74.00 1 0 0 0 1 0 1 76.00 1 0 0 0 1 1 0 78.00 1 0 0 0 1 1 1 80.00 1 0 0 1 0 0 0 82.00 1 0 0 1 0 0 1 84.00 1 0 0 1 0 1 0 86.00 1 0 0 1 0 1 1 88.00 1 0 0 1 1 0 0 90.00 1 0 0 1 1 0 1 92.00 1 0 0 1 1 1 0 94.00 1 0 0 1 1 1 1 96.00 1 0 1 0 0 0 0 98.00 1 0 1 0 0 0 1 100.00 1 0 1 0 0 1 0 102.00 1 0 1 0 0 1 1 104.00 1 0 1 0 1 0 0 106.00 1 0 1 0 1 0 1 108.00 1 0 1 0 1 1 0 110.00 1 0 1 0 1 1 1 112.00 1 0 1 1 0 0 0 166.67 1 0 1 1 0 0 1 167.00 1 0 1 1 0 1 0 168.00 1 0 1 1 0 1 1 169.00 1 0 1 1 1 0 0 170.00 1 0 1 1 1 0 1 171.00 1 0 1 1 1 1 0 172.00 1 0 1 1 1 1 1 173.00 3V66 MHz 66.67 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 84.00 86.00 88.00 90.00 92.00 94.00 96.00 98.00 100.00 102.00 104.00 106.00 108.00 110.00 112.00 66.67 66.80 67.20 67.60 68.00 68.40 68.80 69.20 0496C—05/06/05 8 PCI MHz 33.34 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 42.00 43.00 44.00 45.00 46.00 47.00 48.00 49.00 50.00 51.00 52.00 53.00 54.00 55.00 56.00 33.33 33.40 33.60 33.80 34.00 34.20 34.40 34.60 Integrated Circuit Systems, Inc. Table1: QuadRom Frequency Selection Table Continued Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CPU MHz X X FS4 FS3 FS2 FS1 FS0 1 1 0 0 0 0 0 174.00 1 1 0 0 0 0 1 175.00 1 1 0 0 0 1 0 176.00 1 1 0 0 0 1 1 177.00 1 1 0 0 1 0 0 178.00 1 1 0 0 1 0 1 179.00 1 1 0 0 1 1 0 180.00 1 1 0 0 1 1 1 181.00 1 1 0 1 0 0 0 160.00 1 1 0 1 0 0 1 165.00 1 1 0 1 0 1 0 170.00 1 1 0 1 0 1 1 175.00 1 1 0 1 1 0 0 180.00 1 1 0 1 1 0 1 185.00 1 1 0 1 1 1 0 190.00 1 1 0 1 1 1 1 195.00 1 1 1 0 0 0 0 200.00 1 1 1 0 0 0 1 201.00 1 1 1 0 0 1 0 202.00 1 1 1 0 0 1 1 203.00 1 1 1 0 1 0 0 204.00 1 1 1 0 1 0 1 206.00 1 1 1 0 1 1 0 208.00 1 1 1 0 1 1 1 210.00 1 1 1 1 0 0 0 212.00 1 1 1 1 0 0 1 214.00 1 1 1 1 0 1 0 216.00 1 1 1 1 0 1 1 218.00 1 1 1 1 1 0 0 220.00 1 1 1 1 1 0 1 222.00 1 1 1 1 1 1 0 224.00 1 1 1 1 1 1 1 226.00 ICS950223 3V66 MHz 69.60 70.00 70.40 70.80 71.20 71.60 72.00 72.40 53.33 55.00 56.67 58.33 60.00 61.67 63.33 65.00 66.67 67.00 67.33 67.67 68.00 68.67 69.33 70.00 70.67 71.33 72.00 72.67 73.33 74.00 74.67 75.33 0496C—05/06/05 9 PCI MHz 34.80 35.00 35.20 35.40 35.60 35.80 36.00 36.20 26.67 27.50 28.33 29.17 30.00 30.83 31.67 32.50 33.33 33.50 33.67 33.83 34.00 34.33 34.67 35.00 35.33 35.67 36.00 36.33 36.67 37.00 37.33 37.67 ICS950223 Integrated Circuit Systems, Inc. 2 I C Table: Frequency Select Register Byte 0 Bit 7 Bit Bit Bit Bit Bit Bit Bit Name Control Function Type 0 1 PWD FS Source Frequency H/W IIC Select RW Latch Inputs IIC 0 FS6 FS5 FS4 FS3 FS2 FS1 FS0 Freq Select Bit 6 Freq Select Bit 5 Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 RW RW RW RW RW RW RW Pin # - 6 5 4 3 2 1 0 See Table 1: QuadRom Frequency Selection Table 0 0 0 0 0 0 0 2 I C Table: Spreading and Device Behavior Control Register Byte 1 Pin # Name Control Function Type 0 1 PWD Bit 7 Bit 6 - SS1 SS0 Spread Select 1 Spread Select 0 RW RW See Table 2: Spread Spectrum Table Bit 5 - SS_EN Spread Enable Control RW OFF ON 1 45/44 38/37 41/40 WDS_Status Reserved CPUT2/CPUC2 CPUT1/CPUC1 CPUT0/CPUC0 WD Soft Alarm Status Reserved Output Control Output Control Output Control RW RW RW RW RW Normal Disable Disable Disable Alarm Enable Enable Enable 0 1 1 1 1 Type 0 1 PWD CPU_PLL Sync Disable Disable Disable Disable Disable Disable Disable FIX_PLL Async Enable Enable Enable Enable Enable Enable Enable Bit Bit Bit Bit Bit 4 3 2 1 0 0 0 Table2: Spread Spectrum Select SS1 (Byte 1 bit 7) 0 SS0 (Byte 1 bit 6) 0 Spread % 0.35% Note Spread 1 0 1 0.50% Spread 2 1 0 0.75% Spread 3 1 1 1.00% Spread 4 2 I C Table: Output Control Register Byte 2 Bit 7 Bit Bit Bit Bit Bit Bit Bit 6 5 4 3 2 1 0 Pin # Name - AEN# 17 16 15 14 12 11 10 PCICLK9 PCICLK8 PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 Control Function 3V66/PCI Freq Source Select Output Control Output Control Output Control Output Control Output Control Output Control Output Control 0496C—05/06/05 10 RW RW RW RW RW RW RW RW 0 1 1 1 1 1 1 1 Integrated Circuit Systems, Inc. ICS950223 2 I C Table: Output Control Register Byte 3 Pin # Name Control Function Type 0 1 PWD Output Control Output Control Geashift Reset Enable 24_48 Frequency H/W / IIC Select Sel24_48 Output Control Output Control Output Control RW RW RW Disable Disable ON Enable Enable OFF 1 1 0 RW Latch Inputs IIC 0 RW RW RW RW 24MHz Disable Disable Disable 48MHz Enable Enable Enable 0 1 1 1 Control Function Type 0 1 PWD RW Latch Inputs IIC 0 RW RW RW RW RW RW RW 48MHz Disable Disable Disable Disable Disable Disable 66.66MHz Enable Enable Enable Enable Enable Enable 0 1 1 1 1 1 1 Bit 7 Bit 6 Bit 5 23 22 - 24_48MHz 48MHz GR_EN Bit 4 - 24_48 FS Source Bit Bit Bit Bit 8 7 6 FS 24_48 PCICLK2 PCICLK1 PCICLK0 3 2 1 0 2 I C Table: Output Control Register Byte 4 Bit 7 Bit Bit Bit Bit Bit Bit Bit 6 5 4 3 2 1 0 Pin # Name - 66_48 FS Source 31 30 48 1 27 28 FS 66_48# 3V66_0 3V66_1 REF0 REF1 3V66_3 3V66_2 66_48 Frequency H/W / IIC Select Sel66_48# Output Control Output Control Output Control Output Control Output Control Output Control 2 I C Table: 3V66 & PCICLK Asynchronous Frequency Control Register Byte 5 Bit Bit Bit Bit Bit Bit Bit Bit N PLL2 Div0 N PLL2 Div1 N PLL2 Div2 N PLL2 Div3 N PLL2 Div4 N PLL2 Div5 N PLL2 Div6 N PLL2 Div7 - 7 6 5 4 3 2 1 0 Name Pin # Control Function Type 0 1 PWD The decimal representation of N PLL2 Div (0:7) + 8 is equal to VCO divider value for PLL2. RW RW RW RW RW RW RW RW - - X X X X X X X X Control Function Type 0 1 PWD WD Hard Alarm Status Read back Sel48_24# Read Back Sel66_48# Read Back FS4 Read back FS3 Read back FS2 Read back FS1 Read back FS0 Read back R - - X R R R R R R R - - X X X X X X X 2 I C Table: Read Back Register Byte 6 Pin # Name Bit 7 - WDHRB Bit Bit Bit Bit Bit Bit Bit - SEL48_24RB SEL66_48RB FS4RB FS3RB FS2RB FS1RB FS0RB 6 5 4 3 2 1 0 0496C—05/06/05 11 - ICS950223 Integrated Circuit Systems, Inc. 2 I C Table: Vendor & Revision ID Register Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function Type 0 1 PWD R R R R R R R R - - 1 1 0 1 0 0 0 1 Control Function Type 0 1 PWD Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. RW RW RW RW RW RW RW RW - - 0 0 0 0 1 1 1 1 Control Function Type 0 1 PWD RW - - 0 RW RW RW RW RW RW RW - - 0 0 0 1 0 0 0 Type 0 1 PWD Latched Input Disable Latched FS/Byte0 - IIC Prog. B(11:17) Enable WD B10 b(4:0) - REVISION ID VENDOR ID 2 I C Table: Byte Count Register Byte 8 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 2 I C Table: Watchdog Timer Register Byte 9 Bit 7 Bit Bit Bit Bit Bit Bit Bit 6 5 4 3 2 1 0 Pin # - Name WD7 - WD6 WD5 WD4 WD3 WD2 WD1 WD0 These bits represent X*290ms the watchdog timer will wait before it goes to alarm mode. Default is 8 X 290ms =2.32 seconds 2 I C Table: VCO Control Select Bit & WD Timer Control Register Byte 10 Pin # Name Bit 7 - M/NEN Bit 6 - WDEN Bit 5 - WDFSEN Bit Bit Bit Bit Bit - WD SF4 WD SF3 WD SF2 WD SF1 WD SF0 4 3 2 1 0 Control Function M/N Programming Enable Watchdog Enable WD Safe Frequency Mode Writing to these bit will configure the safe frequency as Byte 0 Bit (6:0) 0496C—05/06/05 12 RW RW RW RW RW RW RW RW 0 0 0 1 1 0 0 1 Integrated Circuit Systems, Inc. ICS950223 2 I C Table: VCO Frequency Control Register Byte 11 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Control Function Type 0 1 PWD N Div8 M Div6 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 N Divider Bit 8 The decimal representation of M Div (6:0) +2 is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table. RW RW RW RW RW RW RW RW - - X X X X X X X X Control Function Type 0 1 PWD RW - - X RW - - X RW RW RW RW RW RW - - X X X X X X 2 I C Table: VCO Frequency Control Register Byte 12 Bit 7 Pin # Name N Div7 - Bit 6 - N Div6 Bit Bit Bit Bit Bit Bit - N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 5 4 3 2 1 0 The decimal representation of N Div (8:0) + 8 is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table. 2 I C Table: Spread Spectrum Control Register Byte 13 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Control Function Type 0 1 PWD SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 These Spread Spectrum bits will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. RW RW RW RW RW RW RW RW - - X X X X X X X X 2 I C Table: Spread Spectrum Control Register Byte 14 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Control Function Type 0 1 PWD Reserved Reserved SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Reserved Reserved R R RW RW RW RW RW RW - - 1 0 X X X X X X It is recommended to use ICS Spread % table for spread programming. 0496C—05/06/05 13 ICS950223 Integrated Circuit Systems, Inc. 2 I C Table: Output Divider Control Register Byte 15 Bit Bit Bit Bit Bit Bit Bit Bit Pin # 7 6 5 4 3 2 1 0 Name CPU Div3 CPU Div2 CPU Div1 CPU Div0 CPU Div3 CPU Div2 CPU Div1 CPU Div0 - Type Control Function RW RW RW RW RW RW RW RW CPUCLK2 divider ratio can be configured via these 4 bits individually. CPUCLK [1:0] divider ratio can be configured via these 4 bits individually. 0 1 PWD X X X X X X X X See Table 3: Divider Ratio Combination Table See Table 3: Divider Ratio Combination Table Table 3: CPU, AGP and PCI Divider Ratio Combination Table Divider (3:2) Bit 00 01 Divider (1:0) 1 00 0 01 1 10 10 11 2 2 100 3 101 10 5 11 11 LSB Address MSB 4 4 1000 6 1001 110 10 7 111 Div Address 8 8 1100 16 12 1101 24 1010 20 1110 40 14 1011 28 1111 56 Div Address Div Address Div 2 I C Table: Output Divider Control Register Byte 16 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name 3V66 Div3 3V66 Div2 3V66 Div1 3V66 Div0 3V66 Div3 3V66 Div2 3V66 Div1 3V66 Div0 - Control Function 3V66 [3:2] divider ratio can be configured via these 4 bits individually 3V66 [1:0] divider ratio can be configured via these 4 bits individually. Type RW RW RW RW RW RW RW RW 0 1 See Table 3: Divider Ratio Combination Table See Table 3: Divider Ratio Combination Table PWD X X X X X X X X 2 I C Table: Output Divider Control Register Byte 17 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Control Function Type 0 1 PWD 3V66INV 3V66INV CPUINV CPUINV PCI Div3 PCI Div2 PCI Div1 PCI Div0 3V66[3:2] Phase Invert 3V66[1:0] Phase Invert CPU Phase Invert CPU Phase Invert RW RW RW RW RW RW RW RW Default Default Default Default Inverse Inverse Inverse Inverse X X X X X X X X PCI divider ratio can be configured via these 4 bits individually. 0496C—05/06/05 14 See Table 3: Divider Ratio Combination Table Integrated Circuit Systems, Inc. ICS950223 2 I C Table: Group Skew Control Register and Frequency Select PLL3 Byte 18 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name Control Function Type CPUSkw1 CPUSkw0 Reserved Reserved CPUSkw1 CPUSkw0 Reserved Reserved CPU_T2/C2 Skew Control Reserved Reserved CPU_T/C [1:0]Skew Control Reserved Reserved RW RW RW RW RW RW RW RW Name Control Function Type Reserved Reserved Reserved Reserved 3V66Skw3 3V66Skw2 3V66Skw1 3V66Skw0 Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW 0 1 See Table 4: 4-Steps Skew Programming Table See Table 4: 4-Steps Skew Programming Table - PWD 1 0 0 0 1 0 0 0 Table 4: 4-Steps Skew Programming Table 4 Step 0 1 LSB 0 0ps 250ps - 1 500ps 750ps - MSB - - - 2 I C Table: Group Skew Control Register Byte 19 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - 3V66 [3:0] Skew Control 0 1 16-Steps Skew Control. This byte will advance or delay the skew by 100ps per step PWD 1 0 0 0 0 1 0 0 2 I C Table: Group Skew Control Register Byte 20 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name PCISkw3 PCISkw2 PCISkw1 PCISkw0 Reserved Reserved Reserved Reserved Control Function PCI Skew Control Reserved Reserved Reserved Reserved 0496C—05/06/05 15 Type RW RW RW RW RW RW RW RW 0 1 16-Steps Skew Control. This byte will advance or delay the skew by 100ps per step - - PWD 1 0 0 0 1 0 0 0 ICS950223 Integrated Circuit Systems, Inc. 2 I C Table: Slew Rate Control Register Byte 21 Pin # Name Control Function Type 0 1 PWD PCICLK_2 Slew Rate Control RW - - 1 RW - - 0 PCICLK [1:0] Slew Rate Control RW - - 1 RW - - 0 3V66[3:2] Slew Rate Control RW - - 1 RW - - 0 3V66 [1:0] Slew Rate Control RW - - 1 RW - - 0 Control Function Type 0 1 PWD PCI [9:7] Slew Rate Control PCI [6:5] Slew Rate Control PCI [4:3] Slew Rate Control RW RW RW RW RW RW RW RW - - 1 0 1 0 1 0 1 0 Name Control Function Type 0 1 PWD Reserved Reserved Reserved Reserved 48Slw1 48Slw0 24_48Slw1 24_48Slw0 Reserved Reserved Reserved Reserved 24_48 Slew Rate Control RW RW RW RW RW RW RW RW - - 1 0 1 0 1 0 1 0 Name Control Function Type 0 1 PWD Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW - - 0 0 0 0 0 0 1 0 Bit 7 - PCISlw1 Bit 6 - PCISlw0 Bit 5 - PCISlw1 Bit 4 - PCISlw0 Bit 3 - 3V66Slw1 Bit 2 - 3V66Slw1 Bit 1 - 3V66Slw1 Bit 0 - 3V66Slw0 2 I C Table: Slew Rate Control Register Byte 22 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name REFSlw1 REFSlw0 PCISlw1 PCISlw0 PCISlw1 PCISlw0 PCISlw1 PCISlw0 REF Slew Rate Control 2 I C Table: Slew Rate Control Register Byte 23 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - 48 Slew Rate Control 2 I C Table: Slew Rate Control Register Byte 24 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - 0496C—05/06/05 16 Integrated Circuit Systems, Inc. ICS950223 2 I C Table: Slew Rate Control Register Byte 25 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Control Function Type 0 1 PWD Reserved Reserved Reserved Reserved Reserved Reserved Reserved - Reserved Reserved Reserved Reserved Reserved Reserved Reserved Transfer Mode Control RW RW RW RW RW RW RW Transfer No transfer 0 0 0 0 0 0 0 0 0496C—05/06/05 17 ICS950223 Integrated Circuit Systems, Inc. Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL Input High Voltage VIH MIN Input Low Voltage VIL Input High Current IIH VIN = VDD Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors Input Low Current Operating Supply Current Power Down Supply Current IIL2 VIN = 0 V; Inputs with pull-up resistors Input frequency Input Capacitance1 Clk Stabilization1 Skew 1 CONDITIONS 1 MAX UNITS 2 TYP VDD + 0.3 V VSS - 0.3 0.8 V 5 mA -5 mA -200 mA IDD(op) CL = 0 pF; Select @ 100MHz 217 260 mA IDDPD CL = 0 pF; With input address to Vdd or GND 31 40 mA 14.31818 16 MHz 5 pF 45 pF 1 1.8 ms 2.5 3.5 ns Fi VDD = 3.3 V; CIN Logic Inputs CINX X1 & X2 pins TSTAB From VDD = 3.3 V to 1% target Freq. TCPU-PCI 11 27 VT = 1.5 V 1.5 Guaranteed by design, not 100% tested in production. 0496C—05/06/05 18 Integrated Circuit Systems, Inc. ICS950223 Electrical Characteristics - CPUCLKT/C TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP Current Source Output VO = Vx 3000 Zo1 Impedance VHigh 660 718 Voltage High Statistical Voltage Low VLow -150 17 measurement on single Max Voltage Measurement on single Vovs 730 ended signal using Min Voltage Vuds -450 -7 Crossing Voltage Vcross(abs) 250 340 (abs) Variation of crossing Crossing Voltage (var) d-Vcross 15 over all edges V OL = 0.175V, VOH = Rise Time tr 175 324 0.525V VOH = 0.525V VOL = 175 453 Fall Time tf 0.175V Measurement from Duty Cycle dt3 45 50.3 differential wavefrom Skew tsk3 VT = 50% 58 Jitter, Cycle to cycle tjcyc-cyc 1 VT = 50% 56 MAX UNITS Ω 850 150 1150 mV mV 550 mV 140 mV 700 ps 700 ps 55 % 100 ps 150 ps 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCICLK TA = 0 - 70°C; VDD = 3.3 V,+/-5%; CL = 30 pF PARAMETER Output Frequency Output High Voltage SYMBOL FO1 CONDITIONS MIN V OH1 IOH = -18mA 2.1 Output Low Voltage V OL1 IOH1 IOL1 tr11 tf11 dt11 t sk11 Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter,cycle to cyc 1 tjcyc-cyc MAX UNITS MHz V IOL = 9.4mA 0.4 V V -22 mA 57 mA OH = TYP 33.33 2.0 V V OL = 0.8 V 16 V OL = 0.4 V, V OH = 2.4 V 1.7 2 ns V OH = 2.4 V, V OL = 0.4 V 1.6 2 ns 51.5 55 % VT = 1.5 V 61 500 ps VT = 1.5 V 114 500 ps VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0496C—05/06/05 19 45 ICS950223 Integrated Circuit Systems, Inc. Electrical Characteristics - 3V66 TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance SYMBOL FO1 CONDITIONS RDSP11 VO = V DD*(0.5) MIN 12 Output High Voltage V OH1 IOH = -1 mA Output Low Voltage Output High Current Output Low Current IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, V OL @MAX = 0.4 V -33 30 VOL = 0.4 V, VOH = 2.4 V 0.5 VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V 0.5 45 Skew V OL1 IOH1 IOL1 tr11 tf11 dt11 tsk11 Jitter t additive1 Rise Time Fall Time Duty Cycle TYP MAX UNITS 66.6 MHz Ω 33 55 2.4 VT = 1.5 V VT = 1.5 V V 0.55 -33 38 V mA mA 1.9 2 ns 1.7 51.5 2 55 ns % 71 250 ps 105 250 ps Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL Output Frequency Output Impedance FO1 MIN Output Low Voltage Output High Current VO = VDD*(0.5) 20 IOH = -1 mA 2.4 -29 IOH1 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output Low Current IOL1 VOL @MIN = 1.95 V, V OL @MAX = 0.4 V 29 48MHz Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 0.5 48MHz Fall Time tf11 tr11 tf11 dt11 dt11 VOH = 2.4 V, VOL = 0.4 V 24MHz Rise Time 24MHz Fall Time 48 MHz Duty Cycle 24MHz Duty Cycle 48 MHz Jitter 24MHz Jitter TYP MAX UNITS 48 RDSP11 VOH1 VOL1 Output High Voltage CONDITIONS 60 MHz Ω V 0.4 V -23 mA 27 mA 1 2 ns 0.5 1 2 ns VOL = 0.4 V, VOH = 2.4 V 1 1.3 2 ns VOH = 2.4 V, VOL = 0.4 V 1 1.4 2 ns V T = 1.5 V 45 52.3 55 % V T = 1.5 V 45 50.2 55 % t jcyc-cyc 1 V T = 1.5 V 139 350 ps t jcyc-cyc 1 V T = 1.5 V 123 350 ps 1 Guaranteed by design, not 100% tested in production. 0496C—05/06/05 20 Integrated Circuit Systems, Inc. ICS950223 Electrical Characteristics - REF TA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance SYMBOL FO1 CONDITIONS MIN RDSP11 VO = V DD*(0.5) 20 Output High Voltage VOH1 V OL1 IOH1 IOL1 tr11 tf11 dt11 IOH = -12mA Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter tjcyc-cyc TYP 14.3 MAX 60 UNITS MHz Ω 0.4 V IOL = 9 mA V 1 V = 2.0 V -33 mA V OL = 0.8 V 38 mA OH VOL = 0.4 V, VOH = 2.4 V 1 2.2 4 ns VOH = 2.4 V, V OL = 0.4 V 1 2.3 4 ns VT = 1.5 V 45 54.1 55 % 129 1000 ps VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0496C—05/06/05 21 ICS950223 Integrated Circuit Systems, Inc. Shared Pin Operation Input/Output Pins pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 0496C—05/06/05 22 Integrated Circuit Systems, Inc. ICS950223 c N SYMBOL L E1 INDEX AREA A A1 b c D E E1 e h L N α E 1 2 α h x 45° D 300 mil SSOP In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° A N A1 48 -Ce SEATING PLANE b .10 (.004) C VARIATIONS D mm. MIN MAX 15.75 16.00 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° D (inch) MIN .620 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS950223yFLFT Example: ICS XXXXXX y F LF - T Designation for tape and reel packaging Annealed Lead Free (optional) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0496C—05/06/05 23 MAX .630 ICS950223 Integrated Circuit Systems, Inc. Revision History Rev. C Issue Date Description 5/6/2005 Added LF Ordering Information Page # 23 0496C—05/06/05 24