IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: IDT74LVCH16260A bus multiplexer/transceiver for use in high-speed microprocessor applications. This bus exchanger supports memory interleaving with latched outputs on the B ports and address multiplexing with latched inputs on the B ports. – – Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages – Extended commercial range of -40°C to +85°C – VCC = 3.3V ±0.3V, Normal Range – VCC = 2.7V to 3.6V, Extended Range – CMOS power levels (0.4µ W typ. static) – All inputs, outputs and I/O are 5 Volt tolerant – Supports hot insertion Drive Features for LVCH16260A: – High Output Drivers: ±24mA – Reduced system switching noise The LVCH16260A tri-port bus exchanger has three 12-bit ports. Data may be transferred between the A port and either/both of the B ports. The latch enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage. When a latch-enable input is high, the latch is transparent. When a latchenable input is low, the data at the input is latched and remains latched until the latch enable input is returned high. Independent output enables (OE1B and OE2B) allow reading from one port while writing to the other port. All pins of the 12-bit Bus Exchanger can be driven from either 3.3V or 5V devices. This feature allows the use of the device as a translator in a mixed 3.3V/5V supply system. APPLICATIONS: The LVCH16260A has been designed with a ±24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance. • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems DESCRIPTION: The LVCH16260A has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. The LVCH16260A tri-port bus exchanger is built using advanced dual metal CMOS technology. The LVCH16260A is a high-speed 12-bit latched Functional Block Diagram OE1B LEA1B 29 30 A-1B LATCH 2 LE1B 1B-A LATCH 12 SEL 1B 1:12 12 12 12 28 1 OEA A 1:12 12 M U X 1 0 12 12 27 2B-A LATCH 55 A-2B LATCH LE2B LEA2B 12 2B 1:12 12 56 OE2B EXTENDED COMMERCIAL TEMPERATURE RANGE MARCH 1999 1 c 1999 Integrated Device Technology, Inc. DSC-4229/1 IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS (1) OEA 1 56 OE2B Symbol VTERM(2) Description Terminal Voltage with Respect to GND Max. – 0.5 to +6.5 Unit V LE1B 2 55 LEA2B VTERM(3) Terminal Voltage with Respect to GND – 0.5 to +6.5 V 2B 3 3 54 2B 4 TSTG Storage Temperature – 65 to +150 °C IOUT DC Output Current – 50 to +50 mA IIK IOK ICC Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through – 50 mA ±100 mA ISS each VCC or GND 53 GND 52 2B 5 51 2B 6 7 50 V CC A1 8 49 2B 7 A2 9 48 2B 8 A3 10 47 2B 9 GND 11 46 GND A4 12 45 2B 10 A5 13 2B 11 A6 14 A7 15 44 SO 56-1 SO 56-2 43 SO 56-3 42 A8 16 41 1B 11 Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 4.5 Max. 6 Unit pF A9 17 40 1B 10 COUT VOUT = 0V 6.5 8 pF GND 18 39 GND VIN = 0V 6.5 8 pF A 10 19 38 1B 9 Output Capacitance I/O Port Capacitance A 11 20 37 1B 8 A 12 21 36 1B 7 V CC 22 35 V CC 1B 1 23 34 1B 6 1B 2 24 33 1B 5 GND 25 32 GND 1B 3 26 31 1B 4 LE2B 27 30 LEA1B SEL 28 29 OE1B GND 4 2B 2 5 2B 1 6 V CC LVC Link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. 2B 12 CAPACITANCE (TA = +25OC, f = 1.0MHz) 1B 12 CI/O LVC Link NOTE: 1. As applicable to the device type. SSOP/ TSSOP/ TVSOP TOP VIEW c 1998 Integrated Device Technology, Inc. 2 DSC-123456 IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O FUNCTION TABLES 1Bx 2Bx H X L Inputs SEL LE1B H X H H H EXTENDED COMMERCIAL TEMPERATURE RANGE (1) Inputs LE2B OEA Outputs Ax Ax X L H H H H L L H H H H L X L (2) LEA1B LEA2B Outputs OE1B OE2B 1Bx 2Bx L L H H L L L L L L H B0(2) X X H L X L A0 X H L X H L H L H L L L L B0(2) X L L X H L L H L H L L B0(2) H L L H L L B0(2) L (2) X X L X L L A0(2) X X X X X H Z NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance B0(2) X L L L L B0 X X X H H Z X X X L H Active Z X X X H L Z Active X X X L L Active Active Z 2. A0, B0 = Output level before the indicated steady-state input conditions were established. PIN DESCRIPTION Signal A(1:12) I/O I/O Description Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.(1) 1B(1:12) I/O Bidirectional Data Port 1B. Connected to the even path or even bank of memory.(1) 2B(1:12) I/O Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.(1) LEA1B I LEA2B I LE1B I LE2B I SEL I OEA I Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA1B. Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA2B. Latch Enable Input for 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched on the HIGH to LOW transition of LE1B. Latch Enable Input for 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched on the HIGH to LOW transition of LE2B. 1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer from 2B Port to A Port. Output Enable for A Port (Active LOW). OE1B I Output Enable for 1B Port (Active LOW). OE2B I Output Enable for 2B Port (Active LOW). NOTE: 1. These pins have “Bus-hold”. All other pins are standard inputs, outputs, or I/Os. 3 IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40OC to +85OC Symbol VIH VIL Parameter Input HIGH Voltage Level VCC = 2.3V to 2.7V Min. 1.7 Typ.(1) — Max. — VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Test Conditions Input LOW Voltage Level Unit V V IIH IIL IOZH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V ICCL ICCH ICCZ Quiescent Power Supply Current VCC = 3.6V ∆ICC Quiescent Power Supply Current Variation — 100 — mV VIN = GND or VCC — — 10 µA 3.6 ≤ VIN ≤ 5.5V(2) — — 10 — — 500 One input at VCC - 0.6V other inputs at VCC or GND µA LVC Link NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Bus-Hold Input Sustain Current VCC = 3.0V Test Conditions VI = 2.0V Min. – 75 Typ.(2) — Max. — VI = 0.8V 75 — — IBHL IBHH Bus-Hold Input Sustain Current VCC = 2.3V IBHL IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 1.7V — — — VI = 0.7V — — — VI = 0 to 3.6V — — ± 500 Unit µA µA µA IBHLO LVC Link NOTES: 1. Pins with Bus-hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 4 IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = – 0.1mA IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — 2.2 — VCC = 3.0V Output LOW Voltage Max. — VCC = 2.3V VCC = 2.7V VOL Min. VCC – 0.2 2.4 — VCC = 3.0V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3.0V IOL = 24mA — 0.55 Unit V V LVC Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to +85°C. OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol CPD Parameter Power Dissipation Capacitance per bus exchanger Outputs enabled CPD Power Dissipation Capacitance per bus exchanger Outputs disabled SWITCHING CHARACTERISTICS Test Conditions CL = 0pF, f = 10Mhz Typical pF (1) VCC = 2.7V±0.2V Symbol Parameter Unit pF VCC = 3.3V±0.3V Min. Max. Min. Max. Unit 1.5 5.7 1.5 5 ns 1.5 6.1 1.5 5.2 ns 1.5 6.1 1.5 5.2 ns 1.5 6.1 1.5 5 ns 1.5 6.3 1.5 5.2 ns 1.5 6.7 1.5 5.5 ns 1.5 5.9 1.5 5.2 ns tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay AX to 1BX or Ax to 2BX Propagation Delay 1BX to AX or 2BX to AX Propagation Delay LEXB to AX Propagation Delay LEA1B to 1BX or LEA2B to 2BX Propagation Delay SEL to AX Output Enable Time OEA to AX, OE1B to 1BX, or OE2B to 2BX Output Disable Time OEA to AX, OE1B to 1BX, or OE2B to 2BX tSU Set-Up Time, HIGH or LOW Data to Latch 1 — 1 — ns tH Hold Time, Latch to Data 1.2 — 1 — ns tW Pulse Width, Latch HIGH 3 — 3 — ns tSK(o) Output Skew (2) — — — 500 ps NOTES: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 5 IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) = 2.7V VCC(2)= 2.5V ±0.2V Unit 2 x Vcc V 6 6 VIH 2.7 2.7 Vcc V VT 1.5 1.5 VCC / 2 V VLZ 300 300 150 mV VHZ 300 300 150 CL 50 50 30 V IH VT 0V SAME PHASE INPUT TRANSITION tPLH t PHL tPLH t PHL V OH VT V OL OUTPUT V IH VT 0V OPPOSITE PHASE INPUT TRANSITION mV pF LVC Link LVC Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V CC Pulse (1, 2) Generator V IN t PZL GND V OUT OUTPUT SW ITCH NORMALLY CLO SED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH D.U.T. 500 Ω RT CL LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. INPUT DATA INPUT tPHZ V OH V HZ VT 0V 0V tS U V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH tR EM ASYNCHRONOUS CONTROL GND SYNCHRONOUS CONTROL Open t SU tH LVC Link LVC Link V IH PULSE WIDTH VT 0V t PHL1 t SK (x) V LZ V OL TIM ING INPUT V OH OUTPUT 1 V LOAD/2 SET-UP, HOLD, AND RELEASE TIMES Switch VLOAD tPLH1 V LOAD/2 VT NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION OUTPUT SKEW - tsk (x) 0V t PLZ LVC Link NOTE: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests V IH VT CONTROL INPUT Open 500 Ω DISABLE ENABLE V LOAD t SK (x) LOW -HIGH-LOW PULSE VT V OL tW V OH HIGH-LOW -HIGH PULSE VT V OL OUTPUT 2 VT VT LVC Link t PLH2 tPHL2 t SK (x) = tPLH2 - tPLH1 or tPHL2 - tP HL1 LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 6 IDT74LVCH16260A 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX LVC Temp. Range X XX XXXX XX Bus-Hold Family Device Type Package PV PA PF Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 260A 12-Bit Tri-Port Bus Exchanger 16 Double-D ensity with Resistors, ±24m A H Bus-hold 74 -40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 7