for AT&T CMOS SRAM K6R1016V1D Document Title 64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Rev. 0.0 Rev. 0.1 Rev. 0.2 Initial document. Speed bin modify Current modify May. 11. 2001 June. 18. 2001 September. 9. 2001 Preliminary Preliminary Preliminary Rev. 1.0 1. Delete 12ns speed bin. 2. Change Icc for Industrial mode. Item Previous 8ns 100mA ICC(Industrial) 10ns 85mA December. 18. 2001 Final Draft Data Remark Current 90mA 75mA Rev. 2.0 1. Add tBA,tBLZ,tBHZ,tBW AC parematers. February. 14. 2002 Final Rev. 3.0 1. Correct read cycle timing diagram(2). June. 19. 2002 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Revision 3.0 June 2002 for AT&T CMOS SRAM K6R1016V1D 1Mb Async. Fast SRAM Ordering Information Org. 256K x4 128K x8 64K x16 Part Number VDD(V) Speed ( ns ) K6R1004C1D-JC(I) 10/12 5 10/12 K6R1004V1D-JC(I) 08/10 3.3 8/10 K6R1008C1D-J(T)C(I) 10/12 5 10/12 K6R1008V1D-J(T)C(I) 08/10 3.3 8/10 K6R1016C1D-J(T,E)C(I) 10/12 5 10/12 K6R1016V1D-J(T,E)C(I) 08/10 3.3 8/10 -2- PKG Temp. & Power J : 32-SOJ J : 32-SOJ T : 32-TSOP2 C : Commercial Temperature ,Normal Power Range I : Industrial Temperature ,Normal Power Range J : 44-SOJ T : 44-TSOP2 E : 48-TBGA Revision 3.0 June 2002 for AT&T CMOS SRAM K6R1016V1D 64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating) FEATURES GENERAL DESCRIPTION • Fast Access Time 8,10ns(Max.) • Low Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.) Operating K6R1016V1D- 08: 80mA(Max.) K6R1016V1D-10: 65mA(Max.) • Single 3.3V Power Supply • TTL Compatible Inputs and Outputs • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Center Power/Ground Pin Configuration • Data Byte Control: LB: I/O1~ I/O 8, UB: I/O9~ I/O16 • Standard Pin Configuration: K6R1016V1D-J: 44-SOJ-400 K6R1016V1D-T: 44-TSOP2-400BF K6R1016V1D-E: 48-TBGA ( 6.0mm X 7.0mm ) with 0.75mm ball pitch • Operating in Commercial and Industrial Temperature range. The K6R1016V1D is a 1,048,576-bit high-speed Static Random Access Memory organized as 65,536 words by 16 bits. The K6R1016V1D uses 16 common input and output lines and has at output enable pin which operates faster than address access time at read cycle. Also it allows that lower and upper byte access by data byte control (UB, LB). The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R1016V1D is packaged in a 400mil 44-pin plastic SOJ or TSOP2 forward or 48-TBGA. FUNCTIONAL BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 Row Select Clk Gen. Pre-Charge Circuit Memory Array 512 Rows 128x16 Columns PIN FUNCTION Pin Name I/O1~I/O8 Data Cont. I/O9 ~I/O16 Data Cont. I/O Circuit & Column Select A0 - A15 Gen. CLK A9 A10 A11 A12 A13 A14 A15 Pin Function Address Inputs WE Write Enable CS Chip Select OE Output Enable LB Lower-byte Control(I/O1~I/O8) UB Upper-byte Control(I/O9~I/O16) I/O 1 ~ I/O16 Data Inputs/Outputs WE OE VCC Power(+3.3V) VSS Ground UB LB CS N.C No Connection -3- Revision 3.0 June 2002 for AT&T CMOS SRAM K6R1016V1D PIN CONFIGURATION(TOP VIEW) A0 1 44 A15 A1 2 43 A14 A2 3 42 A13 A3 4 41 OE A4 5 40 UB CS 6 39 LB I/O1 7 38 I/O16 I/O2 8 37 I/O15 I/O3 9 36 I/O14 SOJ/ I/O4 10 Vcc 11 2 3 4 5 6 A LB OE A0 A1 A2 N.C B I/O1 UB A3 A4 CS I/O9 C I/O2 I/O3 A5 A6 I/O11 I/O10 D Vss I/O4 N.C A7 I/O12 Vcc E Vcc I/O5 N.C N.C I/O13 Vss F I/O7 I/O6 A14 A15 I/O14 I/O15 G I/O8 N.C A12 A13 WE I/O16 H N.C A8 A9 A10 A11 N.C 35 I/O13 34 Vss TSOP2 Vss 12 1 33 Vcc I/O5 13 32 I/O12 I/O6 14 31 I/O11 I/O7 15 30 I/O10 I/O8 16 29 I/O9 WE 17 28 N.C A5 18 27 A12 A6 19 26 A11 A7 20 25 A10 A8 21 24 A9 N.C 22 23 N.C 48-TBGA ( Top View ) ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to V SS Symbol Rating Unit VIN, VOUT -0.5 to 4.6 V VCC -0.5 to 4.6 V Voltage on VCC Supply Relative to VSS Power Dissipation Pd 1 W TSTG -65 to 150 °C Commercial TA 0 to 70 °C Industrial TA -40 to 85 °C Storage Temperature Operating Temperature * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (TA= 0 to 70°C) Parameter Supply Voltage Symbol Min Typ Max Unit V VCC 3.0 3.3 3.6 Ground VSS 0 0 0 Input High Voltage VIH 2.0 - Input Low Voltage VIL -0.3 (2) - VCC+0.3 0.8 V (1) V V (1) V IH(Max) = VCC + 2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA (2) V IL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA. -4- Revision 3.0 June 2002 for AT&T CMOS SRAM K6R1016V1D DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current ILI VIN=VSS to VCC -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC -2 2 µA Operating Current ICC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA 8ns - 80 mA 10ns - 65 8ns - 90 Com. Ind. - 75 ISB Min. Cycle, CS=VIH 10ns - 20 ISB1 f=0MHz, CS≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤0.2V - 5 Output Low Voltage Level VOL IOL=8mA - 0.4 V Output High Voltage Level VOH IOH=-4mA 2.4 - V Standby Current mA * The above parameters are also guaranteed at industrial temperature range. CAPACITANCE*(TA=25°C, f=1.0MHz) Symbol Test Conditions MIN Max Unit Input/Output Capacitance Item CI/O VI/O=0V - 8 pF Input Capacitance C IN VIN=0V - 6 pF * Capacitance is sampled and not 100% tested. AC CHARACTERISTICS(TA=0 to 70°C, Vcc=3.3V+0.3V/-0.15V, unless otherwise noted.) TEST CONDITIONS* Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below * The above test conditions are also applied at industrial temperature range. Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ Output Loads(A) +3.3V RL = 50Ω DOUT VL = 1.5V ZO = 50Ω 319Ω DOUT 30pF* 353Ω * Capacitive Load consists of all components of the test environment. 5pF* * Including Scope and Jig Capacitance -5- Revision 3.0 June 2002 for AT&T CMOS SRAM K6R1016V1D READ CYCLE* K6R1016V1D-08 Parameter Symbol K6R1016V1D-10 Unit Min Max Min Max tRC 8 - 10 - ns Address Access Time tAA - 8 - 10 ns Chip Select to Output tCO - 8 - 10 ns Output Enable to Valid Output tOE - 4 - 5 ns UB, LB Access Time tBA - 4 - 5 ns Read Cycle Time Chip Enable to Low-Z Output tLZ 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - ns UB, LB Enable to Low-Z Output tBLZ 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 4 0 5 ns Output Disable to High-Z Output tOHZ 0 4 0 5 ns UB, LB Disable to High-Z Output tBHZ 0 4 0 5 ns Output Hold from Address Change tOH 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - ns Chip Selection to Power DownTime tPD - 8 - 10 ns * The above parameters are also guaranteed at industrial temperature range. WRITE CYCLE* K6R1016V1D-08 Parameter Symbol K6R1016V1D-10 Min Max Min Max Unit Write Cycle Time tWC 8 - 10 - ns Chip Select to End of Write tCW 6 - 7 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 6 - 7 - ns Write Pulse Width(OE High) tWP 6 - 7 - ns Write Pulse Width(OE Low) tWP1 8 - 10 - ns UB, LB Valid to End of Write tBW 6 - 7 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 4 0 5 ns Data to Write Time Overlap tDW 4 - 5 - ns Data Hold from Write Time tDH 0 - 0 - ns End of Write to Output Low-Z tOW 3 - 3 - ns * The above parameters are also guaranteed at industrial temperature range. TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL) tRC Address tOH Data Out tAA Valid Data Previous Valid Data -6- Revision 3.0 June 2002 for AT&T CMOS SRAM K6R1016V1D TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tHZ(3,4,5) tBHZ(3,4,5) tBA UB, LB tBLZ(4,5) tOHZ tOE OE tOLZ Data out High-Z VCC ICC Current ISB tDH tLZ(4,5) Valid Data tPU tPD 50% 50% NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE =Clock) tWC Address tAW tWR(5) OE tCW(3) CS tBW UB, LB tWP(2) tAS(4) WE tDW Data in High-Z Valid Data tDH High-Z tOHZ(6) Data out -7- Revision 3.0 June 2002 for AT&T CMOS SRAM K6R1016V1D TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed) tWC Address tAW tWR(5) tCW(3) CS tBW UB, LB tWP1(2) tAS(4) WE tDW High-Z Data in tDH Valid Data tWHZ(6) tOW (10) (9) High-Z Data out TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled) tWC Address tAW tWR(5) tCW(3) CS tBW UB, LB tWP(2) tAS(4) WE tDW Data in High-Z High-Z Valid Data tLZ Data out tDH tWHZ(6) High-Z(8) High-Z -8- Revision 3.0 June 2002 for AT&T CMOS SRAM K6R1016V1D TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled) tWC Address tAW tCW(3) tWR(5) CS tBW UB, LB tAS(4) tWP(2) WE tDH tDW High-Z Data in Valid Data tBLZ tWHZ(6) High-Z(8) High-Z Data out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE going low; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS WE OE LB UB H X X* X X L H H X X L X X H H L H L H L L L X H L L L L H H L L L I/O Pin Mode Supply Current I/O1~I/O8 I/O9~I/O16 Not Select High-Z High-Z ISB, ISB1 Output Disable High-Z High-Z ICC DOUT High-Z High-Z DOUT DOUT DOUT Read Write DIN High-Z High-Z DIN DIN DIN ICC ICC * X means Don′t Care. -9- Revision 3.0 June 2002 for AT&T CMOS SRAM K6R1016V1D Units:millimeters/Inches PACKAGE DIMENSIONS 44-SOJ-400 #23 9.40 ±0.25 0.370 ±0.010 10.16 0.400 #44 11.18 ±0.12 0.440 ±0.005 0.20 +0.10 -0.05 0.008 +0.004 -0.002 #1 #22 28.98 MAX 1.141 0.69 MIN 0.027 25.58 ±0.12 1.125 ±0.005 1.19 ) 0.047 3.76 1.27 ( 0.050 ) 0.148 MAX 0.10 MAX 0.004 ( +0.10 ( 0.95 ) 0.0375 0.43 -0.05 0.017 +0.004 -0.002 +0.10 0.71 -0.05 0.028 +0.004 -0.002 1.27 0.050 44-TSOP2-400BF Units:millimeters/Inches 0~8° 0.25 0.010 TYP #23 #44 11.76 ±0.20 0.463 ±0.008 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 ( 0.50 ) 0.020 #1 #22 18.81 MAX 0.741 0.075 0.125 +- 0.035 + 0.003 18.41 ±0.10 0.725 ±0.004 0.005 - 0.001 1.00 ±0.10 0.039 ±0.004 ( 0.805 ) 0.032 0.30 +0.10 −0.05 0.012 +0.004 −0.002 0.05 0.002MIN 0.80 0.0315 - 10 1.20 MAX 0.047 0.10 0.004 MAX Revision 3.0 June 2002 for AT&T CMOS SRAM K6R1016V1D PACKAGE DIMENSION Unit: millimeters 48 TAPE BALL GRID ARRAY(0.75mm ball pitch) Top View Bottom View B B1 B 6 5 4 3 2 1 A B #A1 C C C C1 D C1/2 E F G H B/2 Detail A Side View A Y 0.55/Typ. E1 E 0.35/Typ. E2 D C Min Typ Max A - 0.75 - B 5.90 6.00 6.10 1. Bump counts: 48(8 row x 6 column) B1 - 3.75 - 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) C 6.90 7.00 7.10 C1 - 5.25 - D 0.40 0.45 0.50 E 0.80 0.90 1.00 E1 - 0.55 - E2 0.30 0.35 0.40 Y - - 0.08 Notes. 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ: Typical 5. Y is coplanarity: 0.08(Max) - 11 Revision 3.0 June 2002