Ordering number : EN4868A CMOS LSI LC7872E CD Graphics Decoder Overview Features The LC7872E is a CMOS LSI that integrates in a single chip the signal processing functions required for compact disk graphics (CD-G) decoding. The LC7872E accepts the subcode R to W signals output by a CD-DSP chip such as the Sanyo LC786X series, LC7862XE series or LC7863XE series and performs de-interleaving, error detection and correction, graphics instruction processing and image processing. • A CD-G decoder can be implemented with just two chips: a controller is not required. • Silicon gate CMOS structure for low power operation • Single 5 V power supply • 64-pin QFP (QIP) package Functions 3159-QFP64E • Built-in RGB encoder allows a CD-G decoder to be implemented in just two chips: the LC7872E and an external 64-kword × 4-bit DRAM • Interpolation and protection for the CD subcode synchronization signals as well as de-interleaving, error detection and correction for the R to W signals. • Two crystal oscillator systems, one for NTSC and one for PAL are provided and can be switched easily using the control pin provided. The standard clock and all required internal timings can be generated by connecting a 14.31818 MHz crystal for NTSC and/or a 17.734476 MHz crystal for PAL. • The LC7872E performs CD graphics instruction processing and drawing processing and controls the image display. • Composition video 8-bit D/A converter output provided • Superimposition support • Microprocessor interface provided to support set upgrades. • Define transparency support • Color bar output function Package Dimensions unit: mm [LC7872E] SANYO: QFP64E • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN O3097HA (OT)/20695TH (OT) No. 4868-1/17 DB0 to DB3 Block Diagram Microcontroller interface A0 to A7 LC7872E TRANS0 to TRANS5 Pin Assignment No. 4868-2/17 LC7872E Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD max VSS – 0.3 to +7.0 V Maximum input voltage VIN max VSS – 0.3 to VDD + 0.3 V VOUT max VSS – 0.3 to VDD + 0.3 Maximum output voltage Allowable power dissipation Pd max 300 V mW Operating temperature Topr –30 to +85 °C Storage temperature Tstg –40 to +125 °C Allowable Operating Ranges at Ta = 25°C, VSS = 0 V Parameter Supply voltage Input high level voltage Input low level voltage Symbol VDD Conditions VDD1, VDD2 VIH (1) RESET VIH (2) SFSY, PW, SBSY, CE, DI, CL, MUTE, DB0 to DB3, PALID, HRESET, VRESET, N/P1, N/P2, SON min typ max Unit 4.5 5.5 V 0.7 VDD VDD V 2.2 VDD V VIH (3) S1, S2, CB, TEST, TEST1, LINE, DEN 0.8 VDD VDD V VIL (1) RESET VSS 0.3 VDD V VIL (2) SFSY, PW, SBSY, CE, DI, CL, MUTE, DB0 to DB3, PALID, HRESET, VRESET, N/P1, N/P2, SON VSS 0.8 V VIL (3) 0.2 VDD S1, S2, CB, TEST, TEST1, LINE, DEN VSS tøH CL: Figure 1 400 ns Low level clock pulse width tøL CL: Figure 1 400 ns Data setup time tDS CL, DI: Figure 1 200 ns Data hold time tDH CL, DI: Figure 1 200 ns CE wait time tCP CE, CL: Figure 1 400 ns CE setup time tCS CE, CL: Figure 1 400 ns CE hold time tCH CE, CL: Figure 1 400 tDOS CL, DO: Figure 1 130 fin (1) XIN1 fin (2) XIN2 High level clock pulse width DO setup time Input frequency fin (3) fin (4) Input amplitude Reset pulse width VIN tWRES 4FSC2 FSCIN V ns 300 ns 14.31818 MHz 17.734476 MHz 14.31818 MHz 17.734476 MHz NTSC mode 3.58 MHz PAL mode 4.43 MHz NTSC mode PAL mode XIN1, XIN2, 4FSC2, FSCIN: sine wave, capacitive coupling 0.3 RESET 400 5 Vp-p ns Electrical Characteristics at Ta = 25°C, VSS = 0 V, VDD = 5 V Parameter Current drain Input high level current Input low level current Output high level voltage Symbol max Unit IDD (1) VDD1 24 40 mA IDD (2) VDD2 12 20 mA IIH (1) S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, LINE, HRESET, VRESET, N/P1, N/P2, RESET, SON: VIN = VDD 5 µA IIH (2) CB, TEST, TEST1, DEN: VIN = VDD 30 200 µA VIL (1) S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, LINE, HRESET, VRESET, N/P1, N/P2, RESET, SON: VIN = VSS –5 VIL (2) PALID: VIN = VSS VOH Conditions SBCK, WE, RAS, CAS, OE, A0 to A7, DB0 to DB3, CDGM, TRANS0 to TRANS5, VSYNC, YS, CSYNC, EFLG, FSX, FSC: IO = –0.5 mA min –200 VDD – 1 typ 100 µA –100 –30 µA VDD V Continued on next page. No. 4868-3/17 LC7872E Continued from preceding page. Parameter Output low level voltage Symbol Conditions VOL (1) SBCK, WE, RAS, CAS, OE, A0 to A7, DB0 to DB3, CDGM, TRANS0 to TRANS5, VSYNC, YS, CSYNC, EFLG, FSX, FSC: IO = 2 mA VSS 0.4 DO: IO = 5 mA VSS 0.75 V –5 +5 µA VOL (2) Output off leakage current Built-in feedback resistance IOFF RX DO, DB0 to DB3 min XIN1, XIN2, 4FSC2, FSCIN VREF VIDEO 8-bit D/A converter output resistance RDA VIDEO 8-bit D/A converter output level VDAC VIDEO: Figure 9 Random read/write cycle time tRC Figures 2 and 3 250 Page mode cycle time tPC Figures 4 and 5 130 tRAC Figure 2 CAS access time tCAC Output turn-off delay time max 1 8-bit D/A converter reference voltage RAS access time typ 2.40 2.45 Unit V MΩ 2.50 V Ω 300 ns ns 210 ns Figures 2 and 4 10 ns tOFF Figures 2 and 4 20 ns RAS precharge time tRP Figures 2, 3, 4, 5 and 6 100 RAS pulse width tRAS Figures 2, 3 and 6 120 RAS pulse width (page mode) tRASP Figures 4 and 5 RAS hold time tRSH Figures 2, 3, 4 and 5 CAS hold time tCSH Figures 2 and 3 CAS pulse width tCAS CAS precharge time tCPN ns ns 18000 ns 60 ns 120 ns Figures 2, 3, 4 and 5 60 ns Figure 6 50 ns 50 ns ns CAS precharge time (page mode) tCP Figures 4 and 5 Row address setup time tASR Figures 2, 3, 4 and 5 100 Row address hold time tRAH Figures 2, 3, 4 and 5 50 ns Column address setup time tASC Figures 2, 3, 4 and 5 0 ns Column address hold time tCAH Figures 2, 3, 4 and 5 50 ns Read command setup time tRCS Figure 2 150 ns Read command hold time (referenced to CAS) tRCH Figure 2 120 ns Read command hold time (referenced to RAS) tRRH Figure 2 120 ns Write command setup time tWCS Figure 3 100 ns Write command hold time tWCH Figure 3 50 ns tWP Figure 3 150 ns Write data setup time tDS Figure 3 100 ns Write data hold time tDH Figure 3 100 ns CAS setup time (CAS before RAS) tCSR Figure 6 50 ns CAS hold time (CAS before RAS) tCHR Figure 6 50 ns RAS precharge · CAS active time tRPC Figure 6 50 Superimposition: Figure 7 20 25 ns NTSC mode: Figure 8 4.74 5.03 µs PAL mode: 4.79 5.08 Write command pulse width Video setup time tVS SBCK output delay time tSD SBCK cycle frequency PW setup time fSC tPWS NTSC mode: Figure 8 PAL mode: Figure 8 100 ns µs 224 kHz 222 kHz ns No. 4868-4/17 LC7872E Figure 1 Microcontroller Interface Timing A0 to A7 DB0 to DB3 Figure 2 DRAM Read Cycle No. 4868-5/17 LC7872E A0 to A7 DB0 to DB3 Figure 3 DRAM Early Write Cycle A0 to A7 DB0 to DB3 Figure 4 DRAM Page Mode Read Cycle No. 4868-6/17 LC7872E A0 to A7 DB0 to DB3 Figure 5 DRAM Page Mode Write Cycle Figure 6 DRAM CAS before RAS Refresh Cycle Figure 7 Phase Relationships in Superimposition Mode No. 4868-7/17 LC7872E Pin S1 = Pin S2 = High Figure 8 Subcode Interface Figure 9 Composite Video 8-Bit Digital Values (Color Bar Output) at VDD2 = 5 V No. 4868-8/17 LC7872E Pin Functions Pin No. Symbol I/O 1 S1 I Function CD DSP selection 2 S2 I 3 SBCK O Subcode R to W readout clock 4 SFSY I Subcode frame synchronization signal 5 PW I Subcode R to W data 6 SBSY I 7 VDD1 — S1 S2 0 0 CD DSP LC7861N/67 1 0 LC7860K/63 1 1 LC7868/69/681 Subcode block synchronization signal Digital system power supply 8 CE I Serial input or control pin during serial output 9 DO O Serial data output (N-ch open drain) 10 DI I Serial data input 11 CL I Serial data I/O clock 12 MUTE I Control signal that invalidates the subcode data 13 VSS1 — Digital system ground 14 WE O DRAM control 15 RAS O DRAM control 16 A0 O DRAM address 17 A1 O DRAM address 18 A2 O DRAM address 19 A3 O DRAM address 20 A4 O DRAM address 21 A5 O DRAM address 22 A6 O DRAM address 23 A7 O DRAM address 24 DB0 I/O DRAM data 25 CAS O DRAM control 26 DB1 I/O DRAM data 27 OE O DRAM control 28 DB2 I/O DRAM data 29 DB3 I/O DRAM data 30 CB I High: color bar output Low: normal mode 31 CDGM O Outputs a high level when a CD-G disk detected 32 TRANS0 O Transparency digital output 33 TRANS1 O Transparency digital output 34 TRANS2 O Transparency digital output 35 TRANS3 O Transparency digital output 36 TRANS4 O Transparency digital output 37 TRANS5 O Transparency digital output 38 VSS2 — Composite video D/A converter ground (pull-down resistor built in) 39 VDD2 — Composite video D/A converter power supply 40 BIAS O Ripple exclusion capacitor connection 41 VIDEO O Composite video output (8-bit D/A converter output) 42 TEST I Test pin. Must be tied low in normal operation (pull-down resistor built in) 43 LINE I When pin NP2 is high: High: 263H, Low: 262H When pin NP2 is low: High: 312H, Low: 314H 44 FSCIN I Subcarrier clock input (feedback resistor built in) 45 VSYNC O Vertical synchronization signal output 46 TEST1 I Test pin. Must be tied low in normal operation (pull-down resistor built in) 47 YS O Superimposition control output 48 CSYNC O Composite synchronization signal output 49 4FSC2 I Superimposition mode external clock input (feedback resistor built in) 50 EFLG O Error state monitor Continued on next page. No. 4868-9/17 LC7872E Continued from preceding page. Pin No. Symbol I/O 51 FSX O Error state monitor trigger Function 52 DEN I Disk information display enable pin 53 PALID I Superimposition PAL mode external control (pull-up resistor built in) 54 HRESET I Horizontal timing external control 55 FSC O Subcarrier clock output 56 VRESET I Vertical timing external control 57 RESET I Reset input 58 N/P1 I NTSC/PAL selection High: NTSC (RGB encoder) Low: PAL 59 N/P2 I NTSC/PAL selection High: NTSC (CD-G decoder) Low: PAL 60 SON I Superimposition on/off 61 XIN2 I Crystal oscillator connection 17.734476 MHz (PAL) 62 XOUT2 O Crystal oscillator connection 17.734476 MHz (PAL) 63 XIN1 I Crystal oscillator connection 14.31818 MHz (NTSC) 64 XOUT1 O Crystal oscillator connection 14.31818 MHz (NTSC) High: BGC (pull-down resistor built in) Low: Enable NTSC mode: 3.579545 MHz PAL mode: 4.433619 MHz CD-G Instructions The LC7872E supports the following instructions that appear in the R to W subcodes as described in the CD Red Book. 1. MODE = 0, ITEM = 0 ZERO mode 2. MODE = 1, ITEM = 0 LINE GRAPHICS mode • Write FONT instruction (4) • Write Scroll SCREEN instruction (12) 3. MODE = 1, ITEM = 1 TV-GRAPHICS mode • Preset MEMORY instruction (1) • Preset BORDER instruction (2) • Write FONT FOREGROUND/BACKGROUND instruction (6) • Scroll SCREEN with preset instruction (20) • Scroll SCREEN with Copy instruction (24) • Load CLUT Color-0...7 instruction (30) • Load CLUT Color-8...15 instruction (31) • EXCLUSIVE-OR FONT instruction (38) • Define Color Transparency instruction (28) No. 4868-10/17 LC7872E Pin Applications 1. Crystal Clock Oscillator; XIN1, XOUT1, XIN2, XOUT2, N/P1, N/P2, FSC, CSYNC, LINE and VSYNC The LC7872E provides two crystal oscillator systems as follows. Pins XIN1 and XOUT1 are for use with a 14.31818 MHz crystal oscillator (NTSC) Pins XIN2 and XOUT2 are for use with a 17.734476 MHz crystal oscillator (PAL) Crystals can be connected to either crystal system 1 or 2 according to the application, or both systems can be used under the control of pins N/P1 and N/P2 to implement an application that supports both video standards. The N/P1 pin switches the LC7872E RGB encoder block between NTSC and PAL and the N/P2 pin switches the decoder block between NTSC and PAL. The FSC pin outputs a clock that is the crystal oscillator frequency divided by four. The CSYNC pin is the composite synchronization signal output and VSYNC is the vertical synchronization signal output. The LINE pin switches the number of lines on a screen. The table below lists the pin states in each mode. XIN1, XOUT1 XIN2, XOUT2 14.31818 MHz * * 17.734476 MHz 14.30244 MHz * N/P1 High Low Low N/P2 High Low High Television system NTSC/M PAL/GBIDH PAL/M FSC 3.579545 MHz 4.433619 MHz 3.575611 MHz LINE CSYNC H 16.71511323 ms L 16.65155767 ms H 19.96788628 ms L 20.09588555 ms H 16.73350841 ms L 16.6698829 ms 2. Subcode Interface; S1, S2, SBSY, SFSY, PW, SBCK and MUTE The LC7872E supports three interface modes under the control of pins S1 and S2. When the MUTE pin is set high, SBSY and PW input is disabled and SBCK output stops. S1 Low High S2 Low Low High High Mode LC7861N/67 interface LC7860K/63 interface LC7868/69/681 interface The SBCK delivery condition is that SFSY be confirmed to be low about 2.2 µs after the SFSY falling edge in LC7860K/63 interface mode. In the other interface modes, the condition is that SFSY be confirmed to be high and SBSY be confirmed to be low about 2.2 µs after the SFSY rising edge. • LC7860 interface (Pin names in parentheses are LC7860 pins.) Note: 1. PWSY will be high during the S0 and S1 periods. 2. The SBSY pin must be held low. No. 4868-11/17 LC7872E • LC7861N/67 interface (Pin names in parentheses are DSP pins.) • LC7868/69/681 interface Identical to the LC7861N/67 interface except that the SBCK polarity is reversed (the shift occurs on the rising edge). 3. DRAM Interface; A0 to A7, DB0 to DB3, RAS, CAS, WE, OE The LC7872E uses an external 64-kword × 4-bit DRAM. 4. Display Format; DEN, N/P1, N/P2, CSYNC, VRESET, HRESET, YS, VIDEO, PALID and TRANS0 to TRANS5 • Data to which error detection and correction has been applied is encoded by the RGB encoder and the 8-bit D/A converter output is output from the VIDEO pin. This circuit handles both NTSC and PAL formats and either mode can be specified using the N/P pins. See item 1 for details on the pin states for the NTSC and PAL specifications. • The 4FSC2, FSCIN, YS, VRESET, HRESET, PALID and TRANS0 to TRANS5 pins are used in superimposition mode. The image may be disrupted if the VRESET and HRESET signals are not synchronized with 4FSC2. The PALID pin is controlled in PAL mode, and is used to match the LC7872E burst signal to the burst component of the external video signal. When this pin is high, the phase of the burst signal changes every horizontal period, and when this pin is low, the phase does not change. The YS pin outputs a control signal used to switch between an external video signal and the LC7872E video signal. The output conditions for this signal are set by the 2N byte command input registers 0, E, F, and G. The pins TRANS0 through TRANS5 output signals according to the define transparency instruction. • The DEN pin is a display control pin. The internal font data is output when DEN is low and the color data set up in the registers is used when DEN is high. The default state is blue. No. 4868-12/17 LC7872E 5. CD Graphics Monitor; CDGM The CDGM pin goes high when the LC7872E receives any CD-G instruction. Since once this pin goes high it remains high as long as power is applied, using this pin requires a reset when the disk is changed. 6. Video Output; VIDEO A composite video signal is output from the VIDEO pin. The output level of the 8-bit D/A converter is 2.5 Vp-p. Therefore only an external 75 Ω driver is required to acquire a 1 Vp-p rated output. 7. Error Flag Output; EFLG and FSX The result of the error detection process can be monitored from the EFLG pin. 8. Color Bar Output; CB The VIDEO pin outputs a color bar pattern when the CB pin is set high. The tables below describe this color bar pattern. RGB Mixture Ratio (HEX) R G WHITE Item F F B F GRAY B B B YELLOW F F 0 CYAN 0 F F GREEN 0 F 0 MAGENTA F 0 F RED F 0 0 BLUE 0 0 F BORDER (BLACK) 0 0 0 No. 4868-13/17 LC7872E Microcontroller Interface (CCB Bus) 1. 2N byte input command Address (F4h): lsb [ 0 0 1 0 1 1 1 1 ] msb Control item: lsb [ 0 - - - A A A A ] msb; Where AAAA is the register number. Register 0 (mode setting) Data: lsb [ A B C D E F G H ] msb; Default: [ 0 0 0 0 0 1 1 0 ] A = VRAM/BG 0: Display the contents of VRAM 1: Display the background color (BGC) B = TV/LINE 0: TV graphics mode 1: Line graphics mode C = Disk command enable 0: Only disk commands are accepted. 1: Disk commands are ignored and only MGC is accepted. D = Color bar on/off 0: Off 1: Color bar on EFG = Comparison conditions in superimposition mode (only valid when SON = 1) EF = 00: Comparison not performed. 01: When the border color is not black, YS is set high (display) for section whose color does not match the border color and is set low (clear) otherwise. 11: YS is set high for sections that do not match the chroma key color, and is set low otherwise. G = 0: The whole screen is set low (clear) when the comparison condition does not hold for EF = 00 and EF = 01. G = 1: The whole screen is set high (display) when the comparison condition does not hold for EF = 00 and EF = 01. H = INIT 0: Normal 1: Internal reset On an internal reset the display screen is set to a blue background screen. Register 1 (screen position adjustment) Data: lsb [ H H H H V V V V ] msb; Default: [ 0 0 0 0 0 0 0 0 ] H = horizontal direction. The value is specified as a two’s complement value with left being the positive direction. Position is adjustable in two dot units from –16 to +14 dots from the center. V = vertical direction. The value is specified as a two’s complement value with up being the positive direction. Position is adjustable in two dot units from –16 to +14 dots from the center. Register 2 (on/off settings for channels 0 to 7) Data: lsb [ C C C C C C C C ] msb; Default: [ 1 1 0 0 0 0 0 0 ] C = channel 0 to 7 0: off 1: on No. 4868-14/17 LC7872E Register 3 (on/off settings for channels 8 to 15) Data: lsb [ C C C C C C C C ] msb; Default: [ 0 0 0 0 0 0 0 0 ] C = channel 8 to 15 0: off 1: on Register 4 (BGC R and G setting) Data: lsb [ R R R R G G G G ] msb; Default: [ 0 0 0 0 0 0 0 0 ] Register 5 (BGC B setting) Data: lsb [ B B B B - - - - ] msb; Default: [ 0 1 0 1 - - - - ] Register 6 (chroma key color R and G settings) Data: lsb [ R R R R G G G G ] msb; Default: [ 0 0 0 0 0 0 0 0 ] Register 7 (chroma key color B setting) Data: lsb [ B B B B - - - - ] msb; Default: [ 0 0 0 0 - - - - ] Register 8 (burst phase setting, only valid when SON = 1) Data: lsb [ F F - - - - - P ] msb; Default: [ 0 0 - - - - - 0 ] Register 9 (YS and TRANS output timing) Data: lsb [ T T T - - - - - ] msb; Default: [ 0 0 1 - - - - - ] T = phase setting. The phase difference between YS and TRANS (the digital output) and the video signal can be set to one of 8 levels from 0 to 7 in units of single 4FSC clock cycles. At a value of 4 the phase is identical to that of the VIDEO pin. Register 10 (External synchronization on/off, test mode) Data: lsb [ T T T - - Y S R ] msb; Default: [ 0 0 0 - - - 0 0 ] T = test mode setting R = 0:Only the display area is moved 1:Motion also includes the border area (only left/right motion supported) S = 0:Normal 1:Initializes the TLUT contents to all 0.* Y = 0:Resets HRESET and VRESET when an external clock is used (SON = 1) 1:Resets VRESET when an external clock is used (SON = 1) (HRESET is not required) Note: * In this state the define transparency command will not be accepted. (Return the system to the S = 0 state.) Register 11 (subtitle scrolling, vertical) Data: lsb [ V V V V V - - - ] msb; Default: [ 0 0 0 0 0 - - - ] This setting allows the subtitle screen display position to be scrolled in font height units. V = vertical (up) scrolling distance (0 to 17 font height units) Register 12 (subtitle scrolling, horizontal) Data: lsb [ H H H H H H - - ] msb; Default: [ 0 0 0 0 0 0 - - ] This setting allows the subtitle screen display position to be scrolled in font width units. H = horizontal (left) scrolling distance (0 to 49 font width units) Register 13 (TRANS setting, only valid when SON = 1) Data: lsb [ B B B B B B - P ] msb; Default: [ 0 0 0 0 0 0 - 1 ] P = 1: Enables the TRANS setting. 0: Invalid (The whole screen is displayed and burst goes to the CDG side.) B = the BGC TRANS value No. 4868-15/17 LC7872E 2. 19-byte input command (MGC write) Address (F4h): lsb [ 0 0 1 0 1 1 1 1 ] msb Control item: lsb [ 1 - - - - - - - ] msb Data: lsb [ - - WV U T S R ] msb; R to W is the subcode input. This command is executed on the CE falling edge. 3. 19-byte output command (packed data readout) Address (F5h): lsb [ 1 0 1 0 1 1 1 1 ] msb Check flags: lsb [ A B C D Q Q P P ] msb Data: lsb [ - - WV U T S R ] msb A = Set to 1 when the following 18 bytes are guaranteed and furthermore this is the first data item read out. (The readout operation must be completed within 1.1 ms.) B = 0: Command execution in progress 1: Command wait state C = VBLANK:Set to 1 during the vertical blanking period D = Disk identifier flag 0: CD 1: CD-G Q = QF0 and QF1 (Q error correction flags) P = PF0 and PF1 (P error correction flags) Note that when it is not necessary to read out all 19 bytes, the readout can be interrupted at any point in byte units. (In particular, this command can be used to read out only the check flags.) No. 4868-16/17 LC7872E NTSC Application Circuit Using the LC7872E ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 1997. Specifications and information herein are subject to change without notice. No. 4868-17/17