MC74F543 OCTAL REGISTERED TRANSCEIVER, NON-INVERTING, 3-STATE OCTAL REGISTERED TRANSCEIVER, NON-INVERTING, 3-STATE The MC74F543 Octal Registered Transceivers contain two sets of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The MC74F543 has a noninverting data path. The A outputs are guaranteed to sink 20 mA while the B outputs are rated for 64 mA. • • • • • • • • • • • FAST SCHOTTKY TTL Combines 74F245 and 74F373 Type Functions in One Chip 8-Bit Octal Transceiver Non-Inverting Back-to-Back Registers for Storage Separate Controls for Data Flow in Each Direction Glitchless Outputs During 3-State Power Up or Power Down Operation High Impedance Outputs in Power Off State A Outputs Sink 24 mA and Source 3.0 mA B Outputs Sink 64 mA and Source 15 mA See F544 for Inverting Version ESD Protection > 4000 Volts 1 PIN ASSIGNMENT VCC EBA 24 23 N SUFFIX PLASTIC CASE 724-03 24 DW SUFFIX SOIC CASE 751E-03 24 B0 B1 B2 B3 B4 B5 B6 B7 LEAB OEAB 22 21 20 19 18 17 16 15 14 1 13 ORDERING INFORMATION MC74FXXXN Plastic MC74FXXXDW SOIC 1 2 3 LEBA OEBA A0 4 5 6 7 8 9 10 11 A1 A2 A3 A4 A5 A6 A7 EAB GND 12 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 74 0 25 70 °C IOH Output Current — High 74 – 3.0 / – 15 mA IOL Output Current — Low 74 24 / 64 mA FAST AND LS TTL DATA 4-212 MC74F543 FUNCTION TABLE Inputs EXX LEXX Data Outputs H X X X Z Outputs disabled L L H H L L l h Z Z Outputs disabled Data latched L L L L H H l h L H Data latched L L L L L L L H L H Transparent OEXX Status H = HIGH voltage level: h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): L = LOW Voltage Level: I = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): X = Don’t care: Z = HIGH impedance state. FUNCTIONAL DESCRIPTION The MC74F543 contains two sets of eight D-type latches, with separate input and controls for each set. For data flow from A to B, for example, the A-to-B Enable (EAB) Input must be LOW in order to enter data from A0 – A7 or take data from B0 – B7, as indicated in the Function Table. With EAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-State B output buffers are active and reflects the data present at the output of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA, and OEBA inputs. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage Typ Max 2.0 –0.73 Unit Test Conditions V Guaranteed Input HIGH Voltage 0.8 V Guaranteed Input LOW Voltage – 1.2 V VCC = MIN, IIN = – 18 mA V IOH = – 3.0 mA V IOH = – 15 mA 2.4 VOH VOL A0 – A7 74 B0 – B7 74 A0 – A7 74 0.35 0.5 V IOL = 24 mA B0 – B7 74 0.4 0.55 V IOL = 64 mA 1.0 mA 2.7 Output HIGH Voltage 3.4 2.0 Output LOW Voltage I/O Pins IIH 100 Input HIGH Current Control Pins 20 IIL Input LOW Current IOZH Off-State Output Current, High-Level Voltage Applied IOZL Off-State Output Current, Low-Level Voltage Applied IOS Output Short Circuit Current (Note 2) ICC Total Supply Current EAB, EBA – 1.2 Other Inputs – 0.6 µA mA 70 µA VCC = 4.5 V VCC = 4.75 V VCC = 4.5 V VCC = MIN VCC = MAX, VIN = 5.5 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 0.5 V VCC = MAX VOUT = 2.7 V 1.0 mA – 600 µA VCC = MAX, VOUT = 0.5 V mA VCC = MAX, VOUT = 0 V mA VCC = MAX An Outputs – 60 –150 Bn Outputs – 100 –225 ICCH 70 100 ICCL 95 125 ICCZ 95 125 VOUT = 5.5 V NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-213 MC74F543 AC ELECTRICAL CHARACTERISTICS Symbol Parameter 74F 74F TA = + 25°C VCC = + 5.0 V CL = 50 pF TA = 0°C to + 70°C VCC = + 5.0 V ± 10% CL = 50 pF Min Typ Max Min Max 70 Unit fMAX Maximum Clock Frequency 70 100 MHz tPLH tPHL Propagation Delay Transparent Mode An to Bn or Bn to An 3.0 3.0 5.5 5.0 7.5 6.5 3.0 3.0 8.5 7.5 ns tPLH tPHL Propagation Delay LEBA to An 4.5 4.5 8.5 8.5 11 11 4.5 4.5 12.5 12.5 ns tPLH tPHL Propagation Delay LEAB to Bn 4.5 4.5 8.5 8.5 11 11 4.5 4.5 12.5 12.5 ns tPZH tPZL Output Enable Time to OEBA or OEAB to An or Bn EBA or EAB to An or Bn 3.0 4.0 7.0 7.5 9.0 10.5 3.0 4.0 10 12 ns tPHZ tPLZ Output Disable Time to OEBA or OEAB to An or Bn EBA or EAB to An or Bn 2.5 2.0 6.0 5.5 8.0 7.5 2.5 2.0 9.0 8.5 ns AC OPERATING REQUIREMENTS Symbol Parameter Min 74F 74F TA = + 25°C VCC = + 5.0 V CL = 50 pF TA = 0°C to + 70°C VCC = + 5.0 V ± 10% CL = 50 pF Typ Max Min Typ Max Unit ts(H) ts(L) Setup Time, HIGH or LOW An or Bn to LEBA or LEAB 3.0 3.0 3.5 3.5 ns th(H) th(L) Hold Time, HIGH or LOW An to Bn to LEBA or LEAB 3.0 3.0 3.5 3.5 ns tw(L) Latch Enable, B to A Pulse Width, LOW 8.0 9.0 ns FAST AND LS TTL DATA 4-214 MC74F543 LOGIC DIAGRAM DETAIL A D Q B0 LE Q D A0 LE A1 A2 B1 B2 A3 A4 B3 B4 DETAIL A X 7 A5 B5 A6 B6 A7 B7 OEBA OEAB EBA EAB LEBA LEAB NOTE: Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FAST AND LS TTL DATA 4-215