NSC MM74HC595

MM54HC595/MM74HC595
8-Bit Shift Registers with Output Latches
General Description
Features
This high speed shift register utilizes advanced silicon-gate
CMOS technology. This device possesses the high noise
immunity and low power consumption of standard CMOS
integrated circuits, as well as the ability to drive 15 LS-TTL
loads.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage
register has 8 TRI-STATEÉ outputs. Separate clocks are
provided for both the shift register and the storage register.
The shift register has a direct-overriding clear, serial input,
and serial output (standard) pins for cascading. Both the
shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
The 54HC/74HC logic family is speed, function, and pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Y
Connection Diagram
Truth Table
Dual-In-Line Package
Y
Y
Y
Y
Y
Y
Low quiescent current: 80 mA maximum (74HC Series)
Low input current: 1 mA maximum
8-bit serial-in, parallel-out shift register
with storage
Wide operating voltage range: 2V – 6V
Cascadable
Shift register has direct clear
Guaranteed shift frequency: DC to 30 MHz
RCK
SCK
SCLR
G
Function
X
X
X
H
QA thru QH e TRI-STATE
X
X
L
L
Shift Register cleared
Q'H e 0
X
u
H
L
Shift Register clocked
QN e Qn-1, Q0 e SER
u
X
H
L
Contents of Shift
Register transferred
to output latches
TL/F/5342 – 1
Top View
Order Number MM54HC595 or MM74HC595
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
C1995 National Semiconductor Corporation
TL/F/5342
RRD-B30M105/Printed in U. S. A.
MM54HC595/MM74HC595 8-Bit Shift Registers with Output Latches
January 1988
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
b 0.5 to a 7.0V
Supply Voltage (VCC)
b 1.5 to VCC a 1.5V
DC Input Voltage (VIN)
b 0.5 to VCC a 0.5V
DC Output Voltage (VOUT)
g 20 mA
Clamp Diode Current (IIK, IOK)
g 35 mA
DC Output Current, per pin (IOUT)
g 70 mA
DC VCC or GND Current, per pin (ICC)
b 65§ C to a 150§ C
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temp. (TL) (Soldering 10 seconds)
260§ C
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
0
VCC
Units
V
V
b 40
b 55
a 85
a 125
§C
§C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
VCC e 2.0V
(tr, tf)
VCC e 4.5V
VCC e 6.0V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA e 25§ C
VCC
74HC
TA eb40 to 85§ C
Typ
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
VOH
Minimum High Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
Q'H
QA thru QH
VOL
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
VIN e VIH or VIL
4.0 mA
lIOUTl s
lIOUTl s5.2 mA
4.5V
6.0V
4.2
5.2
3.98
5.48
3.84
5.34
3.7
5.2
V
V
VIN e VIH or VIL
6.0 mA
lIOUTl s
lIOUTl s7.8 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
Maximum Low Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
Q'H
VIN e VIH or VIL
4 mA
lIOUTl s
lIOUTl s5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN e VIH or VIL
6.0 mA
lIOUTl s
lIOUTl s7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
QA thru QH
IIN
Maximum Input
Current
VIN e VCC or GND
6.0V
g 0.1
g 1.0
g 1.0
mA
IOZ
Maximum TRI-STATE
Output Leakage
VOUT e VCC or GND
G e VIH
6.0V
g 0.5
g 5.0
g 10
mA
ICC
Maximum Quiescent
Supply Current
VIN e VCC or GND
IOUT e 0 mA
6.0V
8.0
80
160
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,
ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics VCC e 5V, TA e 25§ C, tr e tf e 6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
50
30
MHz
fMAX
Maximum Operating
Frequency of SCK
tPHL, tPLH
Maximum Propagation
Delay, SCK to QH'
CL e 45 pF
12
20
ns
tPHL, tPLH
Maximum Propagation
Delay, RCK to QA thru QH
CL e 45 pF
18
30
ns
tPZH, tPZL
Maximum Output Enable
Time from G to QA thru QH
RL e 1 kX
CL e 45 pF
17
28
ns
tPHZ, tPLZ
Maximum Output Disable
Time from G to QA thru QH
RL e kX
CL e 5 pF
15
25
ns
tS
Minimum Setup Time
from SER to SCK
20
ns
tS
Minimum Setup Time
from SCLR to SCK
20
ns
tS
Minimum Setup Time
from SCK to RCK
(See Note 5)
40
ns
tH
Minimum Hold Time
from SER to SCK
0
ns
tW
Minimum Pulse Width
of SCK or RCK
16
ns
Note 5: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be
connected together in which case the storage register state will be one clock pulse behind the shift register.
AC Electrical Characteristics VCC e 2.0 – 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
74HC
TA eb40 to 85§ C
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
CL e 50 pF
2.0V
4.5V
6.0V
10
45
50
6
30
35
4.8
24
28
4.0
20
24
MHz
MHz
MHz
tPHL, tPLH
Maximum Propagation
Delay from SCK to Q'H
CL e 50 pF
CL e 150 pF
2.0V
2.0V
58
83
210
294
265
367
315
441
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
14
17
42
58
53
74
63
88
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
10
14
36
50
45
63
54
76
ns
ns
CL e 50 pF
CL e 150 pF
2.0V
2.0V
70
105
175
245
220
306
265
368
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
21
28
35
49
44
61
53
74
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
18
26
30
42
37
53
45
63
ns
ns
tPHL, tPLH
Maximum Propagation
Delay from RCK to QA thru QH
3
AC Electrical Characteristics
VCC e 2.0 – 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) (Continued)
Symbol
Parameter
Conditions
TA e 25§ C
VCC
Typ
tPHL, tPLH
Maximum Propagation
Delay from SCLR to Q'H
tPZH, tPZL
Maximum Output Enable
from G to QA thru QH
2.0V
4.5V
6.0V
74HC
TA eb40 to 85§ C
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
175
35
30
221
44
37
261
52
44
ns
ns
ns
RL e 1 kX
CL e 50 pF
CL e 150 pF
2.0V
2.0V
75
100
175
245
220
306
265
368
ns
ns
CL e 50 pF
CL e 150 pF
4.5V
4.5V
15
20
35
49
44
61
53
74
ns
ns
CL e 50 pF
CL e 150 pF
6.0V
6.0V
13
17
30
42
37
53
45
63
ns
ns
RL e 1 kX
CL e 50 pF
2.0V
4.5V
6.0V
75
15
13
175
35
30
220
44
37
265
53
45
ns
ns
ns
tPHZ, tPLZ
Maximum Output Disable
Time from G to QA thru QH
tS
Minimum Setup Time
from SER to SCK
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
tR
Minimum Removal Time
from SCLR to SCK
2.0V
4.5V
6.0V
50
10
9
63
13
11
75
15
13
ns
ns
ns
tS
Minimum Setup Time
from SCK to RCK
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
26
ns
ns
ns
tH
Minimum Hold Time
SER to SCK
2.0V
4.5V
6.0V
5
5
5
5
5
5
5
5
5
ns
ns
ns
tW
Minimum Pulse Width
of SCK or SCLR
2.0V
4.5V
6.0V
80
16
14
100
20
18
120
24
22
ns
ns
ns
tr, tf
Maximum Input Rise and
Fall Time, Clock
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
tTHL, tTLH
Maximum Output
Rise and Fall Time
QA ± QH
2.0V
4.5V
6.0V
60
12
10
75
15
13
90
18
15
ns
ns
ns
tTHL, tTLH
Maximum Output
Rise & Fall Time
Q'H
2.0V
4.5V
6.0V
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPD
Power Dissipation
Capacitance, Outputs
Enabled (Note 6)
CIN
Maximum Input
Capacitance
5
10
10
10
pF
COUT
Maximum Output
Capacitance
15
20
20
20
pF
30
9
8
25
7
6
G e VCC
G e GND
90
150
pF
pF
Note 6: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.
4
Logic Diagram (positive logic)
TL/F/5342 – 3
5
Timing Diagram
MM54HC595/MM74HC595
TL/F/5342 – 2
6
Physical Dimensions inches (millimeters)
Order Number MM54HC595J or MM54HC595J
NS Package J16A
7
MM54HC595/MM74HC595 8-Bit Shift Registers with Output Latches
Physical Dimensions inches (millimeters) (Continued)
Order Number MM54HC595N
NS Package N16E
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