¡ Semiconductor MSM51V18165B/BSL ¡ Semiconductor MSM51V18165B/BSL E2G0087-17-41 1,048,576-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM51V18165B/BSL is a 1,048,576-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM51V18165B/BSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ double-layer metal CMOS process. The MSM51V18165B/BSL is available in a 42-pin plastic SOJ or 50/44-pin plastic TSOP. The MSM51V18165BSL (the self-refresh version) is specially designed for lower-power applications. FEATURES • 1,048,576-word ¥ 16-bit configuration • Single 3.3 V power supply, ±0.3 V tolerance • Input : LVTTL compatible, low input capacitance • Output : LVTTL compatible, 3-state • Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (SL version) • Fast page mode with EDO, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • CAS before RAS self-refresh capability (SL version) • Package options: 42-pin 400 mil plastic SOJ (SOJ42-P-400-1.27) (Product : MSM51V18165B/BSL-xxJS) 50/44-pin 400 mil plastic TSOP (TSOPII50/44-P-400-0.80-K) (Product : MSM51V18165B/BSL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM51V18165B/BSL-50 50 ns 25 ns 13 ns 13 ns 84 ns 684 mW MSM51V18165B/BSL-60 60 ns 30 ns 15 ns 15 ns 104 ns 576 mW MSM51V18165B/BSL-70 70 ns 35 ns 20 ns 20 ns 124 ns 504 mW 1.8 mW/ 0.72 mW (SL version) 409 MSM51V18165B/BSL ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 42 VSS VCC 1 50 VSS 41 DQ16 DQ1 2 49 DQ16 40 DQ15 DQ2 3 48 DQ15 39 DQ14 DQ3 4 47 DQ14 38 DQ13 DQ4 5 46 DQ13 37 VSS VCC 6 45 VSS 36 DQ12 DQ5 7 44 DQ12 35 DQ11 DQ6 8 43 DQ11 34 DQ10 DQ7 9 42 DQ10 33 DQ9 DQ8 10 41 DQ9 32 NC NC 11 40 NC 28 A9 NC 15 36 NC 27 A8 NC 16 35 LCAS 26 A7 WE 17 34 UCAS 25 A6 RAS 18 33 OE 24 A5 NC 19 32 A9 A3 20 23 A4 NC 20 31 A8 VCC 21 22 VSS A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VCC 25 26 VSS DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 NC 12 WE 13 RAS 14 NC 15 NC 16 A0 17 A1 18 A2 19 31 LCAS 30 UCAS 29 OE 42-Pin Plastic SOJ 50/44-Pin Plastic TSOP (K Type) Pin Name A0 - A9 RAS 410 Address Input Row Address Strobe LCAS Lower Byte Column Address Strobe UCAS Upper Byte Column Address Strobe DQ1 - DQ16 Note : Function Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (3.3 V) VSS Ground (0 V) NC No Connection The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. ¡ Semiconductor MSM51V18165B/BSL BLOCK DIAGRAM RAS WE Timing Generator OE I/O Controller LCAS UCAS 10 Column Address Buffers 10 Internal Address Counter A0 - A9 10 Refresh Control Clock Row Address 10 Buffers Row Decoders Output Buffers 8 I/O Controller 8 DQ1 - DQ8 Column Decoders Sense Amplifiers I/O Selector 16 8 Input Buffers 8 8 Input Buffers 8 16 Memory Cells Word Drivers DQ9 - DQ16 8 Output Buffers 8 VCC On Chip VBB Generator VSS FUNCTION TABLE Input Pin DQ Pin Function Mode RAS LCAS UCAS WE OE DQ1 - DQ8 DQ9 - DQ16 H * H * * High-Z High-Z L * H Refresh H * L High-Z L * H High-Z L DOUT High-Z Lower Byte Read L H L H L High-Z DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L H L H DIN H L L H Don't Care Don't Care DIN Lower Byte Write L Standby Upper Byte Write L L L L H DIN DIN Word Write L L L H H High-Z High-Z — *: "H" or "L" 411 MSM51V18165B/BSL ¡ Semiconductor ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Symbol Rating Voltage on Any Pin Relative to VSS VT –0.5 to 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD * 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Parameter Unit *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage Symbol (Ta = 0°C to 70°C) Min. Typ. Max. Unit VCC 3.0 3.3 3.6 V VSS 0 0 0 V Input High Voltage VIH 2.0 — VCC + 0.3 V Input Low Voltage VIL –0.3 — 0.8 V Capacitance Parameter Input Capacitance (A0 - A9) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Output Capacitance (DQ1 - DQ16) 412 (VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit CIN1 — 5 pF CIN2 — 7 pF CI/O — 7 pF ¡ Semiconductor MSM51V18165B/BSL DC Characteristics Parameter (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Symbol Condition MSM51V18165 MSM51V18165 MSM51V18165 B/BSL-50 B/BSL-60 B/BSL-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –2.0 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.0 mA 0 0.4 0 0.4 0 0.4 V Input Leakage Current ILI –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 190 — 160 — 140 mA 1, 2 — 2 — 2 — 2 — 0.5 — 0.5 — 0.5 mA 1 — 200 — 200 — 200 mA 1, 5 — 190 — 160 — 140 mA 1, 2 — 5 — 5 — 5 mA 1 — 190 — 160 — 140 mA 1, 2 — 190 — 160 — 140 mA 1, 3 — 300 — 300 — 300 mA — 300 — 300 — 300 mA 0 V £ VI £ VCC + 0.3 V; All other pins not under test = 0 V Output Leakage Current ILO Average Power ICC1 Supply Current (Operating) DQ disable 0 V £ VO £ VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, Average Power ICC3 CAS = VIH, Supply Current (RAS-only Refresh) tRC = Min. RAS = VIH, Power Supply Current (Standby) ICC5 CAS = VIL, DQ = enable Average Power ICC6 Supply Current (CAS before RAS Refresh) RAS cycling, CAS before RAS RAS = VIL, Average Power ICC7 CAS cycling, Supply Current (Fast Page Mode) tHPC = Min. Average Power tRC = 125 ms, ICC10 CAS before RAS, Supply Current tRAS £ 1 ms (Battery Backup) 1, 4, 5 Average Power Supply Current (CAS before RAS ICCS RAS £ 0.2 V, CAS £ 0.2 V 1, 5 Self-Refresh) Notes : 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ VCC + 0.3 V, –0.3 V £ VIL £ 0.2 V. SL version. 413 MSM51V18165B/BSL ¡ Semiconductor AC Characteristics (1/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol tRC MSM51V18165 MSM51V18165 MSM51V18165 B/BSL-50 B/BSL-60 B/BSL-70 Unit Note Min. Max. Min. Max. Min. Max. — 104 135 25 — — — — ns — 124 160 30 — ns Random Read or Write Cycle Time Read Modify Write Cycle Time tRWC 84 110 Fast Page Mode Cycle Time tHPC 20 — — tHPRWC 58 — 68 — 78 — ns Access Time from RAS tRAC — 50 — 60 — 70 ns 4, 5, 6 Access Time from CAS tCAC — 13 — 15 — 20 ns 4, 5 Access Time from Column Address Access Time from CAS Precharge tAA tCPA — — 25 30 — — 30 35 — — 35 40 ns ns 4, 6 4, 13 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 13 — — 0 15 — — 0 20 — ns ns 4 4 Data Output Hold After CAS Low tDOH 5 — 5 — 5 — ns CAS to Data Output Buffer Turn-off Delay Time tCEZ tREZ 13 13 0 0 15 15 0 0 20 20 ns RAS to Data Output Buffer Turn-off Delay Time 0 0 ns 7, 8 7, 8 OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time tOEZ tWEZ 0 0 13 13 0 0 15 15 0 0 20 20 ns ns 7 7 Transition Time Refresh Period tT tREF 1 — 50 16 1 — 50 16 1 — 50 16 ns ms 3 Refresh Period (SL version) tREF — 128 — 128 — 128 ms 16 RAS Precharge Time tRP 30 — 40 — 50 — ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode with EDO) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time tRSH RAS Hold Time referenced to OE tROH 7 7 — — 10 10 — — 13 13 — — ns ns CAS Precharge Time (Fast Page Mode with EDO) tCP 7 — 10 — 10 — ns Fast Page Mode Read Modify Write Cycle Time ns 15 CAS Pulse Width tCAS 7 10,000 10 10,000 13 10,000 ns CAS Hold Time CAS to RAS Precharge Time tCSH tCRP 35 5 — — 40 5 — — 45 5 — — ns ns 13 RAS Hold Time from CAS Precharge tRHCP 30 — 35 — 40 — ns 13 OE Hold Time from CAS (DQ Disable) tCHO RAS to CAS Delay Time tRCD tRAD — 37 25 5 14 12 — 45 30 5 14 12 — 50 35 ns ns ns 5 RAS to Column Address Delay Time 5 11 9 Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 7 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns 12 Column Address Hold Time tCAH tRAL 7 25 — — 10 30 — — 13 35 — — ns ns 12 Column Address to RAS Lead Time 414 6 ¡ Semiconductor MSM51V18165B/BSL AC Characteristics (2/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM51V18165MSM51V18165 MSM51V18165 B/BSL-50 B/BSL-60 B/BSL-70 Unit Note Min. Max. Min. Max. Min. Max. Read Command Set-up Time tRCS 0 — 0 — 0 — ns 12 Read Command Hold Time tRCH 0 — 0 — 0 — ns 9, 12 Read Command Hold Time referenced to RAS Write Command Set-up Time tRRH tWCS 0 0 — — 0 0 — — 0 0 — — ns ns 9 10, 12 Write Command Hold Time tWCH 7 — 10 — 13 — ns 12 Write Command Pulse Width tWP 7 — 10 — 10 — ns WE Pulse Width (DQ Disable) tWPE 7 — 10 — 10 — ns OE Command Hold Time OE Precharge Time tOEH tOEP 7 — 10 — 13 — ns 7 — 10 — 10 — ns OE Command Hold Time tOCH 7 — 10 — 10 — ns Write Command to RAS Lead Time tRWL Write Command to CAS Lead Time tCWL 7 7 — — 10 10 — — 13 13 — — ns ns Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time tDS tDH tOED tCWD tAWD RAS to WE Delay Time tRWD — — — — — — 0 10 15 34 49 79 — — — — — — 0 13 20 44 59 94 — — — — — — ns ns ns ns ns ns 11, 12 11, 12 CAS to WE Delay Time Column Address to WE Delay Time 0 7 13 30 42 67 CAS Precharge WE Delay Time 14 10 10 10 tCPWD 47 — 54 — 64 — ns 10 CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — 5 — ns 12 RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) tCSR tCHR 5 10 — — 5 10 — — 5 10 — — ns ns 12 13 tRASS 100 — 100 — 100 — ms 16 tRPS 90 — 110 — 130 — ns 16 tCHS –50 — –50 — –50 — ns 16 RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh) 415 MSM51V18165B/BSL Notes: ¡ Semiconductor 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF. The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 14. tCWL should be satisfied by both UCAS and LCAS. 15. tCP is determined by the time both UCAS and LCAS are high. 16. Only SL version. See ADDENDUM Q for AC Timing Waveforms 416