NTE7131 Integrated Circuit DC–Coupled Vertical Deflection Circuit Description: The NTE7131 is an integrated circuit in a 9–Lead SIP type package designed for use in 90° and 110° color deflection systems for field frequencies of 50 to 120Hz. The circuit provides a DC driven vertical deflection output circuit, operating as a highly efficient class G system. Features: D Few External Components D Highly Efficient Fully DC–Coupled Vertical Output Bridge Circuit D Vertical Flyback Switch D Guard Circuit D Protection Against: Short–Circuit of the Output Pins (7 and 4) Short–Circuit of the Output Pins to VP D Temperature (Thermal) Protection D High EMC Immunity because of Common Mode Inputs D A Guard Signal in Zoom Mode Absolute Maximum Ratings: DC Supply Supply Voltage, VP Non–Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Flyback Supply Voltage, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V Vertical Circuit Output Current (Peak–to–Peak Value, Note 1), IO(p–p) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2A Output Voltage (Pin7), VO(A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52V Flyback Switch Peak Output Current, IM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.5A Thermal Data Virtual Junction Temperature, TVJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Operating Ambient Temperatrure Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25° to +75°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Thermal Resistance, Virtual Junction–to–Ambient (In Free Air), RthVJA . . . . . . . . . . . . . . . . . 40K/W Thermal Resistance, Virtual Junction–to–Case, RthVJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4K/W Short–Circuiting Time (Note 2), tsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Hour Note 1. IO maximum determined by current protection. Note 2. Up to VP = 18V. Electrical Characteristics: (VP = 14.5V, TA = +25°C, VFB = 45V, fi = 50Hz, II(sb) = 400µA unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit DC Supply Operating Supply Voltage VP 9.0 4.5 25.0 V Flyback Supply Voltage VFB VP – 50 V – 30 55 mA 13.2 – – V Supply Current IP No Signal, No Load Output Voltage Swing (Scan) VO Idiff = 0.6mA(p–p), Vdiff = 1.8V(p–p), IO = 2A(p–p) Linearity Error LE IO = 2A(p–p), Note 3 – 1 4 % IO = 50mA(p–p), Note 3 – 1 4 % Vertical Circuit Output Voltage Swing (Flyback) VO(A) – VO(B) VO Idiff = 0.3mA, IO = 1A (M) – 40 – V Forward Voltage of the Internal Efficiency Diode (VO(A) – VFB) VDF IO = –1A (M), Idiff = 0.3mA – – 1.5 V Output Offset Current |IOS| Idiff = 0, II(sb) = 50 to 500µA – – 40 mA Offset Voltage at the Input of the Feedback Amplifier (VI(fb) – VO(B)) |VOS| Idiff = 0, II(sb) = 50 to 500µA – – 24 mV Idiff = 0 – – 72 µV/K VO(A) Idiff = 0, Note 4 – 6.5 – V Gvo Note 5, Note 6 – 80 – dB Note 5 – 80 – dB – 0 – dB – 40 – Hz Output Offset Voltage as a Function of Temperature DC Output Voltage Open–Loop Voltage Gain (V7–4/V1–2) ∆VOST Open–Loop Voltage Gain (V7–4/V9–4, V1–2 = 0) Voltage Ratio V1–2/V9–4 VR Frequency Response (–3dB) fres Current Gain (IO/Idiff) GI – 5000 – Current Gain Drift as a Function of Temperature ∆GcT – – 10–4 K Signal Bias Current II(sb) 50 400 500 µA Flyback Supply Current IFB During Scan – – 100 µA Note 8 – 80 – dB – 2.7 – V Open Loop, Note 7 Power Supply Ripple Rejection PSRR DC Input Voltage VI(DC) Common Mode Input Voltage VI(CM) II(sb) = 0 0 – 1.6 V Ibias II(sb) = 0 – 0.1 0.5 µA ∆II(sb) = 300µA(p–p), fi = 50Hz, Idiff = 0 – 0.2 – mA Not Active, VO(guard) = 0V – – 50 µA 1.0 – 2.5 mA – – 5.5 V – – 40 V Input Bias Current Common Mode Output Current IO(CM) Guard Circuit Output Current IO Active, VO(guard) = 4.5V Output Voltage on Pin8 Allowable Voltage on Pin8 VO(guard) IO = 100µA Maximum Leakage Current = 10µA Notes: Note 3. The linearity error is measured without S–correction and based on the same measurement principle as performed on the screen. The measuring method is as follows: Divide the output signal I4 – I7 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 22 (block 10). Thus part 1 and 22 are unused. The equation for linearity error for adjacent blocks (LEAB) and not adjacent blocks (NAB) are given below LEAD = a ak – a(k + 1) – amin ; NAB = max aavg aavg Note 4. Related to VP. Niote 5. V values within formulae, relate to voltages at or between relative pin numbers, i.e. V7–4/V1–2 = voltage value across pins 7 and 4 divided by voltage value across pins 1 and 2. Note 6. V9–4 AC short–circuited. Note 7. Frequency response V7–4/V9–4 is equal to frequency response V7–4/V1–2. Note 8. At V(ripple) = 500mV eff; measured across RM; fi = 50Hz. Functional Description: The vertical driver circuit is a bridge configuration. The deflection coil is connected between the output amplifiers, which are driven in phase opposition. An external resistor (RM) connected in series with the deflection coil provides internal feedback information. The differential input circuit is voltage driven. The input circuit has been adapted to enable it to be used with devices that deliver symmetrical current signals. An external reisitor (RCON) connected between the differential input determines the output current through the deflection coil. The relationship between the differential input current and the output current is defined by: Idiff x RCON = Icoil x RM. The output current is adjustable from 0.5A(p–p) to 2A(p–p) by varying RM. The maximum input differential voltage is 1.8V. In the application it is recommended that Vdiff = 1.5V (Typ). This is recommended because of the spread of input current and the spread in the value of RCON. The flyback voltage is determined by an additional supply voltage VFB. The principle of operating with two supply voltages (class G) makes it possible to fix the supply voltage VP optimum for the scan voltage and the second supply voltage VFB optimum for the flyback voltage. Using this method, very high efficiency is achieved. The supply voltage VFB is almost totally available as flyback voltage across the coil, this being possible due to the absence of a decoupling capacitor (not necessary, due to the bridge configuration). The output circuit is fully protected against the following: D Thermal Protection D Short–Circuit Protection of the Output Pins (Pin4 and Pin7) D Short–Circuit of the Output pins to VP. A guard circuit VO(guard) is provided. The guard circuit is activated at tghe following conditions: D During Flyback D During Short–Circuit of the Coil and During Short–Circuit of the Output Pins (Pin4 and Pin7) to VP or GND D During Open Loop D When the Thermal Protection is Activated This signal can be used for blanking the picture tube screen. Pin Connection Diagram (Front View) 9 VI(fb) 8 VO(guard) 7 VO(A) 6 VFB 5 GND 4 VO(B) 3 VP 2 Idrive (neg) 1 Idrive (pos) .961 (24.4) .780 (19.8) .185 (4.7) .489 (12.4) 9 1 .079 (2.0) .674 (17.0) .079 (2.0) .100 (2.54)