PHILIPS PH6325L

PH6325L
N-channel TrenchMOS™ logic level FET
Rev. 01 — 28 April 2004
M3D748
Preliminary data
1. Product profile
1.1 Description
Logic level N-channel enhancement mode field-effect transistor in a plastic package
using TrenchMOS™ technology.
1.2 Features
■ Optimized for use in DC-to-DC
converters
■ Low threshold voltage
■ Very low switching and conduction
losses
■ Low thermal resistance.
1.3 Applications
■ DC-to-DC converters
■ Voltage regulators
■ Switched-mode power supplies
■ Notebook computers.
1.4 Quick reference data
■ VDS ≤ 25 V
■ Qgd = 3.3 nC (typ)
■ RDSon ≤ 6.3 mΩ (VGS = 10 V)
■ ID ≤ 78.7 A
■ Qg(tot) = 13.3 nC (typ)
■ RDSon ≤ 9.5 mΩ (VGS = 4.5 V).
2. Pinning information
Table 1:
Pinning - SOT669 (LFPAK), simplified outline and symbol
Pin
Description
1,2,3
source (s)
4
gate (g)
mb
mounting base;
connected to drain (d)
Simplified outline
Symbol
d
mb
g
MBB076
1
2
Top view
3
4
MBL286
SOT669 (LFPAK)
s
PH6325L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
3. Ordering information
Table 2:
Ordering information
Type number
PH6325L
Package
Name
Description
Version
LFPAK
Plastic single-ended surface mounting package; 4 leads
SOT669
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
25 °C ≤ Tj ≤ 150 °C
-
25
V
-
±20
V
Tmb = 25 °C; VGS = 10 V; Figure 2 and 3
-
78.7
A
Tmb = 100 °C; VGS = 10 V; Figure 2
-
49.6
A
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
-
236
A
Tmb = 25 °C; Figure 1
-
62.5
W
storage temperature
−55
+150
°C
junction temperature
−55
+150
°C
VDS
drain-source voltage (DC)
VGS
gate-source voltage
ID
drain current (DC)
IDM
peak drain current
Ptot
total power dissipation
Tstg
Tj
Source-drain diode
IS
source (diode forward) current (DC) Tmb = 25 °C
-
52
A
ISM
peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs
-
208
A
-
115
mJ
-
1.2
mJ
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 34 A;
tp = 0.15 ms; VDD = 25 V; RGS = 50 Ω;
VGS = 10 V; starting at Tj = 25 °C
EDS(AL)R repetitive drain-source avalanche
energy
unclamped inductive load; ID = 3.4 A;
tp = 0.015 ms; VDD = 25 V; RGS = 50 Ω;
VGS = 10 V; starting at Tj = 25 °C
[1]
[2]
[1]
[2]
Duty cycle is limited by the maximum junction temperature.
Repetitive avalanche failure is not determined simply by thermal effects. Repetitive avalanche transients should only be applied for short
bursts, not every switching cycle.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12307
Preliminary data
Rev. 01 — 28 April 2004
2 of 13
PH6325L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa15
120
03aa23
120
Ider
(%)
Pder
(%)
80
80
40
40
0
0
0
50
100
150
200
Tmb (°C)
0
P tot
P der = ----------------------- × 100%
P
°
50
100
200
Tmb (°C)
ID
I der = ------------------- × 100%
I
°
tot ( 25 C )
D ( 25 C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
003aaa559
103
ID
(A)
150
Limit RDSon = VDS / ID
tp = 10 µs
102
100 µs
DC
1 ms
10
10 ms
100 ms
1
10-1
1
102
10
VDS (V)
Tmb = 25 °C; IDM is single pulse; VGS = 10 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12307
Preliminary data
Rev. 01 — 28 April 2004
3 of 13
PH6325L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
thermal resistance from junction to mounting base Figure 4
Rth(j-mb)
Min
Typ
Max
Unit
-
-
2
K/W
5.1 Transient thermal impedance
003aaa560
10
Zth(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
0.05
10-1
0.02
δ=
P
single pulse
tp
T
t
tp
T
10-2
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12307
Preliminary data
Rev. 01 — 28 April 2004
4 of 13
PH6325L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
ID = 250 µA; VGS = 0 V
25
-
-
V
Tj = 25 °C
1
1.5
2
V
Tj = 150 °C
0.5
-
-
V
Tj = 25 °C
-
0.06
1
µA
Tj = 150 °C
-
-
500
µA
-
10
100
nA
Tj = 25 °C
-
7.4
9.5
mΩ
Tj = 150 °C
-
11.8
15.2
mΩ
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th)
IDSS
gate-source threshold voltage
drain-source leakage current
ID = 1 mA; VDS = VGS; Figure 9 and 10
VDS = 25 V; VGS = 0 V
IGSS
gate-source leakage current
VGS = ±16 V; VDS = 0 V
RDSon
drain-source on-state resistance
VGS = 4.5 V; ID = 25 A; Figure 7 and 8
VGS = 10 V; ID = 25 A; Figure 7 and 8
RG(int)
internal gate resistance
Tj = 25 °C
-
4.7
6.3
mΩ
Tj = 150 °C
-
7.5
10.1
mΩ
f = 1 MHz
-
1.8
-
Ω
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
Figure 11 and 12
-
13.3
-
nC
-
4.9
-
nC
Dynamic characteristics
Qg(tot)
total gate charge
Qgs
gate-source charge
Qgs1
pre-VGS(th) gate-source charge
-
2.6
-
nC
Qgs2
post-VGS(th) gate-source charge
-
2.3
-
nC
Qgd
gate-drain (Miller) charge
-
3.3
-
nC
Vplat
plateau voltage
-
2.4
-
V
Qg(tot)
total gate charge
ID = 0 A; VDS = 0 V; VGS = 4.5 V
-
11.1
-
nC
Ciss
input capacitance
-
1871
-
pF
Coss
output capacitance
VGS = 0 V; VDS = 12 V; f = 1 MHz;
Figure 13 and 14
-
517
-
pF
Crss
reverse transfer capacitance
-
179
-
pF
Ciss
input capacitance
VGS = 0 V; VDS = 0 V; f = 1 MHz
-
2420
-
pF
td(on)
turn-on delay time
-
25
-
ns
tr
rise time
VDS = 12 V; ID = 25 A; VGS = 4.5 V;
RG = 4.7 Ω
-
25
-
ns
td(off)
turn-off delay time
-
32
-
ns
tf
fall time
-
12
-
ns
Source-drain diode
VSD
source-drain (diode forward)
voltage
IS = 25 A; VGS = 0 V; Figure 15
-
0.85
1.2
V
trr
reverse recovery time
-
33
-
ns
Qr
recovered charge
IS = 20 A; dIS/dt = −100 A/µs;
VGS = 0 V; VR = 25 V
-
13
-
nC
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12307
Preliminary data
Rev. 01 — 28 April 2004
5 of 13
PH6325L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
003aaa561
40
10 V
ID
4.5 V
2.7 V
003aaa562
40
VGS = 2.6 V
ID
(A)
(A)
2.5 V
30
30
2.4 V
2.3 V
20
Tj = 150 °C
20
2.2 V
25 °C
2.1 V
2V
10
10
1.8 V
1.6 V
0
0
0
0.5
1
1.5
2
VDS (V)
0
Tj = 25 °C
1
2
VGS (V)
3
Tj = 25 °C and 150 °C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
VGS = 2.4 V
RDSon
03af18
2
003aaa563
20
2.5 V
2.6 V
a
(mΩ)
1.5
15
2.7 V
3V
10
1
4.5 V
10 V
5
0.5
0
0
0
10
20
30
ID (A)
40
Tj = 25 °C
-60
60
120
Tj (°C)
180
R DSon
a = ---------------------------R DSon ( 25 °C )
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12307
Preliminary data
0
Rev. 01 — 28 April 2004
6 of 13
PH6325L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa33
2.5
VGS(th)
(V)
2
1.5
03aa36
10-1
ID
(A)
max
10-2
typ
10-3
min
max
10-4
min
1
typ
10-5
0.5
0
-60
10-6
0
60
120
Tj (°C)
180
0
1
2
VGS (V)
3
Tj = 25 °C; VDS = 5 V
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
003aaa566
10
003aaa508
VDS = 4.5 V
VGS
(V)
8
12 V
VDS
19 V
ID
6
Vplat
VGS(th)
4
VGS
Qgs1
2
Qgs2
Qgs
Qgd
Qg(tot)
0
0
10
20
QG (nC)
30
ID = 25 A; VDS = 4.5 V, 12 V and 19 V
Fig 11. Gate-source voltage as a function of gate
charge; typical values.
Fig 12. Gate charge waveform definitions.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12307
Preliminary data
Rev. 01 — 28 April 2004
7 of 13
PH6325L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
003aaa564
104
003aaa633
4000
C
(pF)
C
(pF)
Ciss
3000
Ciss
Crss
103
2000
Coss
1000
Crss
102
10-1
0
1
10
VDS (V)
102
0
2
4
6
8
10
VGS (V)
Tj = 25 °C and 150 °C; VDS = 0 V
VGS = 0 V; f = 1 MHz
Fig 13. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
Fig 14. Input and reverse transfer capacitances as a
function of gate-source voltage; typical values.
003aaa565
40
IS
(A)
30
Tj = 150 °C
20
25 °C
10
0
0.2
0.4
0.6
0.8
1
VSD (V)
Tj = 25 °C and 150 °C; VGS = 0 V
Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12307
Preliminary data
Rev. 01 — 28 April 2004
8 of 13
PH6325L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
7. Package outline
Plastic single-ended surface mounted package (Philips version LFPAK); 4 leads
A2
A
E
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
4
X
e
w M A
b
1/2
c
e
A
(A 3)
A1
C
θ
L
detail X
y C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
A2
A3
b
b2
1.20 0.15 1.10
0.50 4.41
0.25
1.01 0.00 0.95
0.35 3.62
mm
b3
b4
2.2
2.0
0.9
0.7
c
D (1)
c2
D1(1)
E(1) E1(1)
max
e
H
L
L1
L2
w
y
θ
5.0
4.8
1.27
6.2
5.8
0.85
0.40
1.3
0.8
1.3
0.8
0.25
0.1
8°
0°
0.25 0.30 4.10
4.20
0.19 0.24 3.80
3.3
3.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT669
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
03-02-05
03-09-15
MO-235
Fig 16. SOT669 (LFPAK).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12307
Preliminary data
Rev. 01 — 28 April 2004
9 of 13
PH6325L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
8. Soldering
5.70
4.70
solder lands
4.60
0.075
3.70
solder resist
2.50
occupied area
2.00
0.90 (3×)
solder paste
0.25 (2×)
0.25
(2×)
2.00
2.05
3.45 3.50
3.68
3.30
3.48
2.50
0.60 (3×)
0.85
1.10
2.15
MSD864
1.27
3.81
0.70 (4×)
0.05 around (4×)
Fig 17. SOT669 (LFPAK) optimized soldering footprint
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12307
Preliminary data
Rev. 01 — 28 April 2004
10 of 13
PH6325L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
9. Revision history
Table 6:
Revision history
Rev Date
01
20040428
CPCN
Description
-
Preliminary data (9397 750 12307)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12307
Preliminary data
Rev. 01 — 28 April 2004
11 of 13
PH6325L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
10. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
11. Definitions
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
13. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
12. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected].
Preliminary data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12307
Rev. 01 — 28 April 2004
12 of 13
Philips Semiconductors
PH6325L
N-channel TrenchMOS™ logic level FET
Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
5.1
6
7
8
9
10
11
12
13
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
© Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 28 April 2004
Document order number: 9397 750 12307