Philips Semiconductors Product specification TrenchMOS transistor Logic level FET FEATURES PHP130N03LT, PHB130N03LT SYMBOL • ’Trench’ technology • Very low on-state resistance • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance QUICK REFERENCE DATA VDSS = 30 V d ID = 75 A RDS(ON) ≤ 6 mΩ (VGS = 5 V) g s RDS(ON) ≤ 5 mΩ (VGS = 10 V) GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP130N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB130N03LT is supplied in the SOT404 surface mounting package. PINNING SOT78 (TO220AB) PIN SOT404 DESCRIPTION tab tab 1 gate 2 drain1 3 source tab 2 drain 1 1 23 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 30 30 ± 13 75 75 240 187 175 V V V A A A W ˚C Tmb = 25 ˚C; VGS = 5 V Tmb = 100 ˚C; VGS = 5 V Tmb = 25 ˚C Tmb = 25 ˚C 1 It is not possible to make connection to pin 2 of the SOT404 package. January 1998 1 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP130N03LT, PHB130N03LT ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Human body model (100 pF, 1.5 kΩ) Electrostatic discharge capacitor voltage, all pins MIN. MAX. UNIT - 2 kV THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78 package, in free air SOT404 package, pcb mounted, minimum footprint TYP. MAX. UNIT - - 0.8 K/W - 60 50 - K/W K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; V(BR)GSS VGS(TO) Drain-source breakdown voltage Gate-source breakdown voltage Gate threshold voltage MIN. Tj = -55˚C IG = 1 mA VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) gfs IGSS IDSS Drain-source on-state resistance VGS = 5 V; ID = 25 A VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175˚C Forward transconductance VDS = 25 V; ID = 25 A Gate-source leakage current VGS = ±5 V; VDS = 0 V; Tj = 175˚C Zero gate voltage drain VDS = 30 V; VGS = 0 V; current Tj = 175˚C TYP. MAX. UNIT 30 27 10 - - V V V 1 0.5 20 - 1.5 5 4.5 40 0.02 0.05 - 2 2.3 6 5 11 1 10 10 500 V V V mΩ mΩ mΩ S µA µA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 75 A; VDD = 24 V; VGS = 5 V - 92 10 36 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 15 V; ID = 25 A; VGS = 5 V; RG = 5 Ω Resistive load - 45 120 225 100 60 170 300 135 ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 5000 1150 500 - pF pF pF January 1998 2 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP130N03LT, PHB130N03LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IS ISM MIN. TYP. MAX. UNIT - - 75 A - - 240 A IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V - 0.85 1.0 1.2 - V IF = 75 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 25 V - 100 0.6 - ns µC AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS Drain-source non-repetitive ID = 75 A; VDD ≤ 15 V; unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C energy WDSS 120 Normalised Power Derating PD% ID (A) MIN. MAX. UNIT - 500 mJ Current Derating 140 110 100 120 90 80 Limited by package 100 70 80 60 50 60 40 30 40 20 20 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 0 0 180 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) January 1998 20 40 60 80 100 120 140 160 180 Tmb / C Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V 3 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP130N03LT, PHB130N03LT 7506-30 Drain current, ID (A) 1000 RDS(ON) / mOhm 9506-30 10 = N) S/ VD ID 8 S(O 3.5 tp = 10 us RD 100 3 4 6 100 us 5 1 ms DC 10 6 4 10 ms 100 ms 2 1 1 10 Drain-source voltage, VDS (V) 0 100 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp 0 20 Zth / (K/W) 0.2 9506-30 0.05 tp PD 0.02 0 D= T 1E-03 1E-07 1E-05 1E-03 t/s tp T 40 t 20 1E-01 0 1E+01 Tj / C = 175 0 1 2 25 3 4 5 VGS / V Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T ID / A Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj BUK9506-30 100 3.5 gfs / S 9506-30 3 5 80 100 60 0.1 6 80 80 0.5 100 60 ID / A 100 1E-02 ID / A Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 1E+00 1E-01 40 80 VGS / V = 2.8 60 40 2.6 40 20 2.4 20 60 Tj / C = 25 175 2.2 0 0 2 4 6 8 0 10 VDS / V Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS January 1998 0 20 40 ID / A 60 80 100 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V 4 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP130N03LT, PHB130N03LT a 30V TrenchMOS 2 10000 C / pF 9506-30 Ciss 1.5 1 Coss 1000 Crss 0.5 0 -100 -50 0 50 Tj / C 100 100 0.1 200 150 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V 2.5 VDS / V 10 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz BUK959-60 VGS(TO) / V 1 5 VGS / V 9506-30 max. 2 4 VDS / V = 6 24 typ. 3 1.5 min. 1 2 0.5 1 0 -100 -50 0 50 Tj / C 100 150 0 200 20 40 60 80 100 QG / nC Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 75 A; parameter VDS Sub-Threshold Conduction 1E-01 0 100 IF / A 9506-30 80 1E-02 2% 1E-03 typ 98% 60 Tj / C = 175 25 0.5 1 VSDS / V 40 1E-04 20 1E-05 0 1E-05 0 0.5 1 1.5 2 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS January 1998 0 1.5 2 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 5 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 120 PHP130N03LT, PHB130N03LT WDSS% VDD + 110 100 L 90 80 VDS - 70 VGS 60 -ID/100 50 T.U.T. 0 40 30 20 RGS 10 R 01 shunt 0 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A January 1998 6 Rev 1.300