Philips Semiconductors Product specification TrenchMOS transistor Logic level FET FEATURES PHP24N03LT, PHB24N03LT SYMBOL • ’Trench’ technology • Very low on-state resistance • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance QUICK REFERENCE DATA VDSS = 30 V d ID = 24 A RDS(ON) ≤ 56 mΩ (VGS = 5 V) g s RDS(ON) ≤ 50 mΩ (VGS = 10 V) GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP24N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB24N03LT is supplied in the SOT404 surface mounting package. PINNING SOT78 (TO220AB) PIN SOT404 DESCRIPTION tab tab 1 gate 2 drain1 3 source tab 2 drain 1 1 23 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 30 30 ± 13 24 20 96 60 175 V V V A A A W ˚C Tmb = 25 ˚C; VGS = 5 V Tmb = 100 ˚C; VGS = 5 V Tmb = 25 ˚C Tmb = 25 ˚C 1 It is not possible to make connection to pin 2 of the SOT404 package. January 1998 1 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP24N03LT, PHB24N03LT ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Human body model (100 pF, 1.5 kΩ) Electrostatic discharge capacitor voltage, all pins MIN. MAX. UNIT - 2 kV THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78 package, in free air SOT404 package, pcb mounted, minimum footprint TYP. MAX. UNIT - - 2.5 K/W - 60 50 - K/W K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; V(BR)GSS VGS(TO) Drain-source breakdown voltage Gate-source breakdown voltage Gate threshold voltage MIN. Tj = -55˚C IG = 1 mA VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) gfs IGSS IDSS Drain-source on-state resistance VGS = 5 V; ID = 25 A VGS = 10 V; ID = 25 A VGS = 5 V; ID = 12 A; Tj = 175˚C Forward transconductance VDS = 25 V; ID = 12 A Gate-source leakage current VGS = ±5 V; VDS = 0 V; Tj = 175˚C Zero gate voltage drain VDS = 30 V; VGS = 0 V; current Tj = 175˚C TYP. MAX. UNIT 30 27 10 - - V V V 1 0.5 3 - 1.5 50 45 5 0.02 0.05 - 2 2.3 56 50 104 1 10 10 500 V V V mΩ mΩ mΩ S µA µA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 10 A; VDD = 30 V; VGS = 5 V - 9 2.3 5.4 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 25 A; VGS = 5 V; RG = 10 Ω Resistive load - 12 50 30 36 - ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 460 144 78 - pF pF pF January 1998 2 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP24N03LT, PHB24N03LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IS ISM MIN. TYP. MAX. UNIT - - 24 A - - 96 A IF = 25 A; VGS = 0 V - 1.05 1.5 V IF = 12 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 25 V - 50 0.1 - ns µC AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS Drain-source non-repetitive ID = 12 A; VDD ≤ 15 V; unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C energy WDSS 120 Normalised Power Derating PD% 120 110 110 100 100 90 90 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 MAX. UNIT - 15 mJ Normalised Current Derating ID% 0 180 0 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) January 1998 MIN. 20 40 60 80 100 Tmb / C 120 140 160 180 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V 3 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP24N03LT, PHB24N03LT PHP24N03T ID, Drain current (Amps) 100 RDS(on), Drain-Source on resistance (Ohms) PHP24N03LT 3V VGS = 2.5 V 0.12 /ID DS V )= 0.1 10 us ON ( DS R 0.08 100 us 3.5 V 0.06 10 5V DC 1 ms 0.04 10 ms 15 V 0.02 Tmb = 25 C 1 Tj = 25 C 0 1 10 VDS, Drain-source voltage (Volts) 100 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp 10 0 5 10 15 ID, Drain current (Amps) 20 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS Transient thermal impedance, Zth j-mb (K/W) PHP24N03T Drain current, ID (A) 20 PHP24N03LT VDS = 25 V D= 1 15 0.5 0.2 10 0.1 0.05 0.1 0.02 PD tp D= 0 1us 10us 100us 1ms 10ms pulse width, tp (s) 5 175 C 0.1s 1s 0 10s 0 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 20 ID, Drain current (Amps) 5V 15 V Tj = 25 C t T 0.01 tp T 1 2 3 Gate-source voltage, VGS (V) 4 5 Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj PHP24N03LT 15 PHP24N03LT Transconductance, gfs (S) VDS = 25 V 3.5 V Tj = 25 C 15 10 175 C 3V 10 5 5 VGS = 2.5 V Tj = 25 C 0 0 5 10 15 20 25 VDS, Drain-Source voltage (Volts) 0 30 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS January 1998 0 5 10 Drain current, ID (A) 15 20 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 4 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP24N03LT, PHB24N03LT a 30V TrenchMOS 2 1000 Capacitances Ciss, Coss, Crss (pF) PHP24N03LT Ciss 1.5 100 1 Coss Crss 0.5 Tj = 25 C 0 -100 -50 0 50 Tj / C 100 10 200 150 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 12 A; VGS = 5 V 2.5 10 100 Drain-source voltage, VDS (V) 1000 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz BUK959-60 VGS(TO) / V 1 15 VGS, Gate-Source voltage (Volts) PHP24N03LT VDD = 30 V ID = 10 A Tj = 25 C max. 2 typ. 10 1.5 min. 1 5 0.5 0 -100 0 -50 0 50 Tj / C 100 150 200 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 5 10 15 Qg, Gate charge (nC) 20 25 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Sub-Threshold Conduction 1E-01 0 20 PHP24N03LT Source-Drain diode current, IF(A) VGS = 0 V 1E-02 15 2% 1E-03 typ 98% 10 175 C 1E-04 Tj = 25 C 5 1E-05 0 1E-05 0 0.5 1 1.5 2 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS January 1998 0 0.2 0.4 0.6 0.8 1 Source-Drain voltage, VSDS (V) 1.2 1.4 Fig.14. Typical reverse diode current. IF = f(VSDS); parameter Tj 5 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 120 PHP24N03LT, PHB24N03LT WDSS% VDD + 110 100 L 90 80 VDS - 70 VGS 60 -ID/100 50 T.U.T. 0 40 30 20 RGS 10 R 01 shunt 0 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb) January 1998 6 Rev 1.300