Preliminary R2J20652ANP Integrated Driver – MOS FET (DrMOS) REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Description The R2J20652ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating the need for an external SBD for this purpose. Features Based on Intel 6 6 DrMOS specification pin out Built-in power MOS FET suitable for Notebook, Desktop, Server application Low-side MOS FET with built-in SBD for lower loss and reduced ringing Built-in driver circuit which matches the power MOS FET Built-in tri-state input function which can support a number of PWM controllers VIN operating-voltage range: 27 V max High-frequency operation (above 1 MHz) possible Large average output current (Max. 35 A) Achieve low power dissipation Controllable driver: Remote on/off Low-side MOS FET disabled function for DCM operation Built-in bootstrapping switch Small package: QFN40 (6 mm 6 mm 0.95 mm) Terminal Pb-free/Halogen-free Outline Integrated Driver-MOS FET (DrMOS) QFN40 package 6 mm × 6 mm VCIN BOOT GH VIN 1 10 11 40 Reg5V Driver Pad High-side MOS Pad DISBL# VSWH MOS FET Driver LSDBL# Low-side MOS Pad PWM 31 CGND GL PGND 20 30 21 (Bottom view) REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 1 of 16 R2J20652ANP Preliminary Block Diagram Driver Chip VCIN Reg5V UVL BOOT GH Boot SW VIN Reg5V DISBL# High Side MOS FET 2 μA Supervisor CGND Reg5V Level Shifter 25 k 150 k LSDBL# Reg5V VSWH PWM Overlap Protection. & Logic Input Logic (TTL Level) (3 state in) Low Side MOS FET Reg5V 20 μA PGND CGND GL Notes: 1. Truth table for the DISBL# pin. DISBL# Input "L" "Open" "H" 2. Truth table for the LSDBL# pin. Driver Chip Status Shutdown (GL, GH = "L") Shutdown (GL, GH = "L") Enable (GL, GH = "Active") 3. Output signal from the UVL block UVL output Logic Level For active "H" For shutdown "L" VCIN VL REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 2 of 16 VH LSDBL# Input "L" "Open" "H" GL Status "L" "Active" "Active" R2J20652ANP Preliminary VIN 11 VIN 12 VIN 13 VIN VIN VIN VSWH GH CGND BOOT VCIN NC LSDBL# Pin Arrangement 10 9 8 7 6 5 4 3 2 1 40 PWM 39 DISBL# 38 Reg5V VIN 14 37 CGND VSWH 15 36 GL PGND 16 35 VSWH PGND 17 34 VSWH PGND 18 33 VSWH PGND 19 32 VSWH PGND 20 31 VSWH VIN CGND VSWH VSWH PGND VSWH PGND PGND PGND PGND PGND PGND PGND 21 22 23 24 25 26 27 28 29 30 (Top view) Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name LSDBL# NC VCIN BOOT CGND GH VIN VSWH PGND GL Reg5V DISBL# PWM Pin No. 1 2 3 4 5, 37, Pad 6 8 to 14, Pad 7, 15, 29 to 35, Pad 16 to 28 36 38 39 40 Description Low-side gate disable No connect Control input voltage Bootstrap voltage pin Control signal ground High-side gate signal Input voltage Phase output/Switch output Power ground Low-side gate signal +5 V logic power supply output Signal disable PWM drive logic input REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 3 of 16 Remarks When asserted "L" signal, Low-side gate disable Driver Vcc input To be supplied +5 V through internal switch Should be connected to PGND externally Pin for Monitor Pin for Monitor Disabled when DISBL# is "L" 5 V logic input R2J20652ANP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Power dissipation Supply voltage PWM voltage Symbol Pt(25) Pt(110) Iout VIN(DC) VIN(AC) VSWH(DC) VSWH(AC) VBOOT(DC) VBOOT(AC) VCIN Vpwm Other I/O voltage Reg5V voltage Reg5V current DISBL# current Vdisbl, Vlsdbl Vreg5V Ireg5V Idisbl Operating junction temperature Storage temperature Tj-opr Tstg Average output current Input voltage Switch node voltage BOOT voltage Notes: 1. 2. 3. 4. 5. 6. 7. 8. Rating 25 8 35 –0.3 to +27 30 27 30 32 36 –0.3 to +27 Units W A V V V V V –0.3 to +5.5 @UVL OFF –0.3 to +0.3 @UVL ON –0.3 to Reg5V + 0.3 –0.3 to VCIN + 0.3 –0.3 to +6 –20 to +0.1 0 to 1.0 V V mA mA –40 to +150 –55 to +150 °C °C Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. Rated voltages are relative to voltages on the CGND and PGND pins. For rated current, (+) indicates inflow to the chip and (–) indicates outflow. This rating is when UVL (Under Voltage Lock out) is ineffective (normal operation mode). This rating is when UVL (Under Voltage Lock out) is effective (lock out mode). The specification values indicated "AC" are limited within 100 ns. This rating is when the external power-source is applied to Reg5V pin. Reg5V + 0.3 V < 6 V Safe Operating Area Average Output Current (A) 45 40 35 30 25 20 VOUT = 1.3 V VIN = 12 V VCIN = 12 V L = 0.45 μH Fsw = 1 MHz 15 10 5 0 0 25 REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 4 of 16 50 75 100 125 PCB Temperature (°C) 150 175 Note 1 2 2, 4, 6 2 2, 4, 6 2 2, 4, 6 2 2, 4 2, 5 2, 7, 8 2 7 3 3 R2J20652ANP Preliminary Recommended Operating Condition Item Input voltage Supply voltage Symbol VIN VCIN Rating 4.5 to 22 Units V V 4.5 to 5.5 or 8 to 22 Note When the usage of VCIN = 4.5 V to 5.5 V, VCIN should be connected to Reg5V (Refer to "Pin Connection") Electrical Characteristics (Ta = 25C, VCIN = 12 V, VSWH = 0 V, unless otherwise specified) Item Supply PWM input 5V regulator DISBL# input LSDBL# input Note: Symbol Min Typ Max Units Test Conditions VCIN start threshold VH 7.0 7.4 7.8 V VCIN shutdown threshold VL 6.6 7.0 7.4 V UVLO hysteresis dUVL — 0.4 — V VCIN operating current ICIN — 34 — mA fPWM = 1 MHz, Ton_pwm = 120 ns VCIN disable current ICIN-DISBL — — 2.5 mA DISBL# = 0 V, PWM = 0 V, LSDBL# = Open PWM rising threshold VH-PWM 3.0 3.4 3.8 V PWM falling threshold VL-PWM 0.9 1.2 1.5 V PWM input resistance RIN-PWM 10 20 40 k VL-PWM — VH-PWM V — 100 — ns Tri-state shutdown window VIN-SD Shutdown hold-off time tHOLD-OFF *1 VH – VL PWM = 1 V Output voltage Vreg 4.95 5.2 5.45 V Line regulation Vreg-line –10 0 10 mV VCIN = 12 V to 16 V Load regulation Vreg-load –10 0 10 mV Ireg = 0 to 10 mA Disable threshold VDISBL 0.9 1.2 1.5 V Enable threshold VENBL 1.9 2.4 2.9 V Input current IDISBL 10 20 40 A Low-side activation threshold VLSDBLH 1.9 2.4 2.9 V Low-side disable threshold VLSDBLL 0.9 1.2 1.5 V Input current ILSDBL –56 –28 –14 A 1. Reference values for design. Not 100% tested in production. REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 5 of 16 DISBL# = 1 V LSDBL# = 1 V R2J20652ANP Preliminary Typical Application (1) Desktop/Server Application +12 V VCIN BOOT VIN DISBL# Reg5V R2J20652ANP PGND PWM CGND LSDBL# GH +5 V VCIN VSWH GL BOOT VIN DISBL# Reg5V R2J20652ANP PWM VSWH PGND CGND LSDBL# GH GL PWM1 PWM Control Circuit +1.3 V PWM2 PWM3 PWM4 VCIN BOOT VIN DISBL# Reg5V R2J20652ANP PGND PWM CGND LSDBL# GH VCIN VSWH GL BOOT VIN DISBL# Reg5V R2J20652ANP PWM CGND LSDBL# GH REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 6 of 16 VSWH PGND GL Power GND Signal GND R2J20652ANP Preliminary Typical Application (cont.) (2) Notebook Application +19 V +5 V VCIN BOOT VIN DISBL# Reg5V R2J20652ANP PGND PWM CGND LSDBL# GH VCIN VSWH GL BOOT VIN DISBL# Reg5V R2J20652ANP PWM VSWH PGND CGND LSDBL# GH GL PWM1 PWM Control Circuit +1.1 V PWM2 PWM3 VCIN BOOT DISBL# VIN Reg5V R2J20652ANP PWM CGND LSDBL# GH REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 7 of 16 VSWH PGND GL Power GND Signal GND R2J20652ANP Preliminary Pin Connection (1) Typical Desktop/Server Application 0.1 μF 1.0 μF 0 to 10 Ω CGND VIN 12 V Low Side Disable Signal INPUT 8 7 6 5 4 3 2 1 GH CGND BOOT VCIN NC LSDBL# 9 VIN 10 VSWH CGND 10 μF × 4 11 VIN PAD 12 13 PGND CGND PAD 14 VIN DSBL# 39 DSBL# INPUT Reg5V 38 1.0 μF CGND 37 15 VSWH GL 36 R2J20652ANP 16 PGND VSWH 35 VSWH PAD 17 18 34 33 31 22 23 24 25 26 27 VSWH 32 20 PGND 19 21 Power GND PWM INPUT PWM 40 28 29 30 0.45 μH Signal GND Vout PGND PGND (2) Typical Notebook Application 0 to 10 Ω 0.1 μF VIN 19 V Low Side Disable Signal INPUT 7 6 5 4 3 2 CGND BOOT VCIN NC 11 VIN PAD 12 13 PGND PWM INPUT PWM 40 CGND PAD 14 VIN DSBL# 39 Reg5V 38 CGND 37 15 VSWH GL 36 R2J20652ANP 16 PGND VSWH PAD 18 34 DSBL# INPUT 33 31 22 Signal GND 23 24 25 26 27 VSWH 32 20 PGND 19 21 5.0 V External Power Supply 1.0 μF VSWH 35 17 Power GND 1 LSDBL# 8 GH 9 VIN 10 VSWH CGND 10 μF × 4 28 29 30 0.45 μH Vout PGND REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 8 of 16 PGND R2J20652ANP Preliminary Test Circuit Vinput A IIN V VIN Vcont A ICIN VCIN V VCIN BOOT DISBL# VIN R2J20652ANP Reg5V VSWH LSDBL# 5 V pulse PWM CGND Note: PIN = IIN × VIN + ICIN × VCIN POUT = IO × VO Efficiency = POUT / PIN PLOSS(DrMOS) = PIN – POUT Ta = 27°C REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 9 of 16 PGND GH Electric load IO GL Average Output Voltage Averaging V VO circuit R2J20652ANP Preliminary Typical Data Power Loss vs. Output Current Power Loss vs. Input Voltage 9 1.5 VIN = 12 V 8 VCIN = Reg5V = 5 V VOUT = 1.3 V Normalized Power Loss @ VIN = 12 V Power Loss (W) 7 fPWM = 600 kHz L = 0.45 μH 6 5 4 3 2 1.2 1.1 1.0 0.9 1 0 VCIN = Reg5V = 5 V VOUT = 1.3 V 1.4 f PWM = 600 kHz L = 0.45 μH 1.3 IOUT = 25 A 0 5 10 15 20 25 30 0.8 35 4 6 8 Output Current (A) 12 VIN = 12 V VCIN = Reg5V = 5 V 1.4 f PWM = 600 kHz L = 0.45 μH 1.3 IOUT = 25 A VIN = 12 V VCIN = Reg5V = 5 V 1.4 VOUT = 1.3 V L = 0.45 μH 1.3 IOUT = 25 A 1.0 Normalized Power Loss @ fPWM = 600 kHz 1.5 1.1 20 22 1.1 1.0 0.9 0.8 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 0.8 250 REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 10 of 16 18 1.2 0.9 Output Voltage (V) 16 Power Loss vs. Switching Frequency 1.5 1.2 14 Input Voltage (V) Power Loss vs. Output Voltage Normalized Power Loss @ VOUT = 1.3 V 10 500 750 1000 Switching Frequency (kHz) 1250 R2J20652ANP Preliminary Power Loss vs. Output Inductance Power Loss vs. VCIN 1.5 1.5 1.3 Normalized Power Loss @ VCIN = Reg5V = 5 V Normalized Power Loss @ L = 0.45 μH 1.4 VIN = 12 V VCIN = Reg5V = 5 V VOUT = 1.3 V fPWM = 600 kHz IOUT = 25 A 1.2 1.1 1.0 1.2 1.1 1.0 0.9 0.9 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.8 4.5 Average ICIN vs. Switching Frequency 50 40 VIN = 12 V VCIN = Reg5V = 5 V VOUT = 1.3 V L = 0.45 μH IOUT = 0 A 30 20 10 0 250 500 750 1000 Switching Frequency (kHz) REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 11 of 16 5.0 5.5 VCIN = Reg5V (V) Output Inductance (μH) Average ICIN (mA) VIN = 12 V VOUT = 1.3 V 1.4 f PWM = 600 kHz L = 0.45 μH 1.3 IOUT = 25 A 1250 6.0 R2J20652ANP Preliminary Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, lowside MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & DISBL# The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the built-in 5 V regulator is disabled as long as VCIN is 7.4 V or less. On cancellation of UVL, the built-in 5 V regulator remains enabled until the UVL input is driven to 7.0 V or less. The built-in 5 V regulator is a series regulator with temperature compensation. A ceramic capacitor with a value of 0.1 F or more must be connected between the CGND plane and the Reg5V Pin. The output of 5 V regulator is monitored by the internal Supervisor circuits. When the Supervisor detects this output is more than 4.2 V (typ.), the driver state becomes active (figure1.1). Figure 1.2 shows the application when the external 5 V regulator is used. When the Reg5V pin is applied into external 5 V, the Supervisor can activate the driver. In this application usage, VCIN should be connected to Reg5V. The signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit, the built-in 5 V regulator does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is terminated, and the 5 V regulator is not disabled. Voltages from –0.3 V to VCIN + 0.3 V can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor, etc., to pull the DISBL# line up to VCIN are both possible. VCIN L H H H DISBL# L H Open REG5V 0 Active Active Active 12 V Driver State Disable (GL, GH = L) Disable (GL, GH = L) Active Disable (GL, GH = L) VCIN > 7.4 V VCIN VCIN 5V IN Reg5V UVL & 5 V Regulator To Internal Logic OUT OUT IN UVL & 5 V Regulator Reg5V External 5 V To Internal Logic Supervisor Figure 1.1 Typical 12 V Input Application (Activate Built-in 5 V Regulator) REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 12 of 16 Supervisor Figure 1.2 External 5 V Application R2J20652ANP Preliminary PWM & LSDBL# The PWM pin is the signal input pin for the driver chip. When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. PWM L H GH L H GL H L The LSDBL# pin is the Low Side Gate Disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is low. Figure 2 shows the Typical high-side and low-side gate switching and Inductor current (IL) during "Continuous Conduction Mode (CCM)" and low-side gate disabled when asserting LSDBL# signal. This pin is internally pulled up to Reg5V with 150 k resistor. When low-side disable function is not used, keep this pin open or pulled up to VCIN. CCM Operation (LSDBL# = "H" or Open mode) IL GH GL Figure 2.1 Typical Signals during CCM DCM Operation (LSDBL# = "L") IL 0A GH GL Figure 2.2 Typical Signals during DCM REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 13 of 16 R2J20652ANP Preliminary The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tristate function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 100 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 3.4 V or more is required to make the circuit return to normal operation. 100 ns (tHOLD-OFF) 100 ns (tHOLD-OFF) 3.4 V PWM 1.2 V GH GL 100 ns (tHOLD-OFF) 100 ns (tHOLD-OFF) 3.4 V PWM 1.2 V GH GL Figure 3 PWM Shutdown-Hold Time Signal REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 14 of 16 R2J20652ANP Preliminary The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal operation; after the PWM input signal has stayed in the hysteresis window for 100 ns (typ.) and the tri-state detection signal has been driven high, the transistor M1 is turned off. When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is asserted high signal, M1 becomes ON and shifts to normal operation. VCIN DISBL# M1 20 k PWM Pin Input Logic Tri-state detection signal To internal control 20 k Figure 4 Equivalent Circuit for the PWM-pin Input MOS FETs The MOS FETs incorporated in R2J20652ANP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 15 of 16 R2J20652ANP Preliminary Package Dimensions JEITA Package Code P-HVQFN40-p-0606-0.50 RENESAS Code PVQN0040KC-A Previous Code — MASS[Typ.] — .1 39 ) B HE E B 1pin 40 40 2.2 C0.3 1.95 E /2 INDEX 1.95 4-C0.50 1pin 2.2 (0 D /2 2.2 4- HD/2 0.2 0.2 HD D A 0.7 0.2 Reference Symbol 2.05 X4 f S AB b x 20° S AB L1 S c2 y1 S A A2 0.69 20° 2.05 ZD e t S AB Lp A1 X4 ZE 1.95 2.2 HE/2 CAV No. Die No. 1.95 2-A section y S Dimension in Millimeters Min Nom Max D 5.95 6.00 6.05 5.95 6.00 6.05 E A2 0.87 0.89 0.91 f — — 0.20 A 0.865 0.91 0.95 A1 0.005 0.02 0.04 b 0.17 0.22 0.27 b1 0.16 0.20 0.24 — 0.50 — e Lp 0.40 0.50 0.60 x — — 0.05 y — — 0.05 y1 — — 0.20 t — — 0.20 HD 6.15 6.20 6.25 HE 6.15 6.20 6.25 ZD — 0.75 — ZE — 0.75 — L1 0.06 0.10 0.14 c1 0.17 0.20 0.23 c2 0.17 0.22 0.27 Ordering Information Part Name R2J20652ANP#G3 Quantity 2500 pcs REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page 16 of 16 Shipping Container Taping Reel Notice 1. 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