Revised August 1999 74FR900 9-Bit, 3-Port Latchable Datapath Multiplexer General Description Features The 74FR900 is a data bus multiplexer routing any of three 9-bit ports to any other one of the three ports. Readback of data latched from any port onto itself is also possible. The 74FR900 maintains separate control of all latch-enable, output enable and select inputs for maximum flexibility. PINV allows inversion of the data from the C8 to A8 or B8 path. This is useful for control of the parity bit in systems diagnostics. ■ 9-bit data ports for systems carrying parity bits Fairchild’s 74FR25900 includes 25Ω resistors in series with port A and B outputs. Resistors minimize undershoot and ringing which may damage or corrupt sensitive device inputs driven by these ports. ■ FR25900 resistor option for driving MOS inputs such as DRAM arrays ■ Readback capability for system self checks. ■ Independent control lines for maximum flexibility ■ Guaranteed multiple output switching and 250 pF load delays ■ Outputs optimized for dynamic bus drive capability ■ PINV parity control facilitates system diagnostics Ordering Code: Order Number Package Number 74FR900SSC MS48A Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Description Pin Names LExx Description Latch Enable Inputs OEx Output Enable Inputs PINV Parity Invert Input S0, S1 Select Inputs A0–A8 Port A Inputs or 3-STATE Outputs B0–B8 Port B Inputs or 3-STATE Outputs C0–C8 Port C Inputs or 3-STATE Outputs © 1999 Fairchild Semiconductor Corporation DS010990 www.fairchildsemi.com 74FR900 9-Bit, 3-Port Latchable Datapath Multiplexer May 1992 74FR900 Functional Description TABLE 1. Datapath Control The 74FR900 allows 9-bit data to be transferred from any of three 9-bit I/O ports to either of the two remaining I/O ports. The device employs latches in all paths for either transparent or synchronous operation. Readback capability from any port to itself is also possible. Inputs Data transfer within the 74FR900 is controlled through use of the select (S0 and S1) and output-enable (OEA, OEB and OEC) inputs as described in Table 1. Additional control is available by use of the latch-enable inputs (LEAC, LECA, LEBC, LECB) allowing either synchronous or transparent transfers (see Table 2). Table 1 indicates several readback conditions. By latching data on a given port and initiating the readback control configuration, previous data may be read for system verification or diagnostics. This mode may be useful in implementing system diagnostics. Data at the port to be readback must be latched prior to enabling the outputs on that port. If this is not done, a closed data loop will result causing possible data integrity problems. Note that the A and B ports allow readback without affecting any other port. Port C, however, requires interruption of either port A or B to complete its readback path. PINV controls inversion of the C8 bit. A low on PINV allows C8 data to pass unaltered. A high causes inversion of the data. See Table 3. This feature allows forcing of parity errors for use in system diagnostics. This is particularly helpful in 486 processor designs as the 486 does not provide odd/even parity selection internally. Input S1 OEB OEC L X H L L Port A to Port C L L H H H Port A to Port B L O H H L Port A to B+C H L L L H Port B to Port A H X H L L Port B to Port C H O L L L Port B to A+C X H L L H Port C to Port A X H H H H Port C to Port B X H L H H Port C to A+B X X H L H Outputs Disabled L L L X X (Readback to A) (Note 1) L H L X L (Readback to A or C) (Note 1) H L X H X (Readback to B) (Note 1) H H X H L (Readback to B or C) (Note 1) Note 1: Readback operation in latched mode only. Transparent operation could result in unpredictable results. TABLE 2. Latch-Enable Control LExx OEA Function S0 TABLE 3. PINV Control Output PINV C8 L A8 or B8 L H H L L L L L H H L H X Q0 H L H H H L L = LOW Voltage H = HIGH Voltage Level Q0 = Output state prior to LExx LOW-to-HIGH transition Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage VCC Pin Potential to Ground Pin 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output in LOW State (Max) Note 3: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VCC V Conditions VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH Voltage V Min IOH = −3 mA (An, B n, Cn) V Min IOH = −15 mA (An, Bn, Cn) VOL Output LOW Voltage 0.50 V Min IOL = 24 mA (An, Bn, Cn) IIH Input HIGH Current 5 µA Max VIN = 2.7V (Control Inputs) IBVI Input HIGH Current 7 µA Max VIN = 7.0V (Control Inputs) 100 µA Max VIN = 5.5V (An, Bn, Cn) −150 µA Max VIN = 0.5V (Control Inputs) V 0.0 3.75 V 0.0 2.4 2.0 Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) IIL Input LOW Current VID Input Leakage Test IOD 4.75 Output Circuit Leakage Test Recognized HIGH Signal Recognized LOW Signal IID = 1.9 µA, All Other Pins Grounded VIOD = 150 mV, All Other Pins Grounded IIH + IOZH Output Leakage Current 25 µA Max IIIL + IOZL Output Leakage Current −150 µA Max VOUT = 0.5V (An, Bn, Cn) IOS Output Short Circuit Current −225 mA Max VOUT = 0.0V (An, Bn, Cn) ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC (An, Bn, Cn) IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.25V (An, Bn, Cn) ICCH Power Supply Current 115 150 mA Max All Outputs HIGH (Note 4) ICCL Power Supply Current 170 200 mA Max All Outputs LOW (Note 4) ICCZ Power Supply Current 147 175 mA Max Outputs in 3-STATE −100 VOUT =2.7V (An, Bn, Cn) Note 4: 2 ports active only 3 www.fairchildsemi.com 74FR900 Absolute Maximum Ratings(Note 2) 74FR900 AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay tPHL An or Bn to Cn TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Units Min Typ Max Min Max 2.0 4.2 7.0 2.0 7.0 ns 2.5 4.8 7.5 2.5 7.5 ns 4.5 6.4 10.0 4.5 10.0 ns 4.5 6.8 10.0 4.5 10.0 ns 3.0 6.0 9.5 3.0 9.5 ns 3.0 6.0 10.0 3.0 10.0 ns 3.5 6.5 11.0 3.5 11.0 ns 2.0 5.0 9.0 2.0 9.0 ns 2.0 4.0 6.5 2.0 6.5 ns 1.5 4.0 6.0 1.5 6.0 ns 2.0 5.0 7.0 2.0 7.0 ns 2.0 5.0 7.0 2.0 7.0 ns Cn to An or Bn tPLH Propagation Delay tPHL C8 to A8 or B8 (PINV HIGH) tPLH Propagation Delay tPHL An to Bn, Bn to An tPLH Propagation Delay tPHL LEAC to Cn, LEBC to Cn tPLH Propagation Delay tPHL LECA to An, LECB to Bn tPLH Propagation Delay tPHL S0 to Cn tPLH Propagation Delay tPHL S1 to An or Bn tPLH Propagation Delay tPHL PINV to A8 or B8 tPZH Output Enable Time tPZL An, Cn tPHZ Output Disable Time tPLZ An, Cn tPZH Output Enable Time tPZL Bn tPHZ Output Disable Time tPLZ Bn AC Operating Requirements Symbol Parameter tS(H) Setup Time, HIGH or LOW tS(L) An to LEAC, Bn to LEBC tH(H) Hold Time, HIGH or LOW tH(L) An to LEAC, Bn to LEBC tS(H) Setup Time, HIGH or LOW tS(L) Cn to LECA or LECB tH(H) Hold Time, HIGH or LOW tH(L) Cn to LECA or LECB tW(H) LE Pulse Width LOW TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Max Min Units Min Typ Max 4.0 2.0 4.0 ns 1.0 −2.0 1.0 ns 3.0 1.0 3.0 ns 1.0 −1.0 1.0 ns 8.0 4.0 8.0 ns Extended AC Electrical Characteristics Symbol Parameter TA = 0°C to +70°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 250 pF Nine Outputs Switching (Note 6) (Note 5) Min tPLH Propagation Delay www.fairchildsemi.com 4 Max Min Max Units Symbol Parameter 74FR900 Extended AC Electrical Characteristics (Continued) TA = 0°C to +70°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 250 pF Nine Outputs Switching (Note 6) Units (Note 5) tPHL An or Bn to Cn Min Max Min Max 2.0 9.0 2.5 10.5 ns 3.5 11.0 ns Cn to An or Bn tPLH Propagation Delay tPHL C8 to A8 or B8 (PINV HIGH) tPLH Propagation Delay tPHL An to Bn, Bn to An tPLH Propagation Delay tPHL LEAC to Cn, LEBC to Cn tPLH Propagation Delay tPHL LECA to An, LECB to Bn tPLH Propagation Delay tPHL S0 to Cn tPLH Propagation Delay tPHL S1 to An or Bn tPLH Propagation Delay tPHL PINV to A8 or B8 tPZH Output Enable Time tPZL An, Cn tPHZ Output Disable Time tPLZ An, Cn tPZH Output Enable Time tPZL Bn tPHZ Output Disable Time tPLZ Bn 4.5 12.0 5.5 13.5 ns 4.5 12.0 5.5 13.5 ns 3.0 11.5 4.0 13.5 ns 3.0 11.0 3.0 14.0 ns 3.5 12.0 4.5 15.0 ns 2.5 12.0 ns 2.0 8.0 ns 1.5 6.0 ns 2.0 8.0 ns 2.0 7.0 ns Note 5: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase, i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc. Note 6: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors standard AC load. This specification pertains to single output switching only. 5 www.fairchildsemi.com 74FR900 9-Bit, 3-Port Latchable Datapath Multiplexer Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS48A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6