PHILIPS 74LVT16500ADL

74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
Rev. 03 — 29 May 2006
Product data sheet
1. General description
The 74LVT16500A is a high-performance BiCMOS product designed for VCC operation at
3.3 V.
This device is an 18-bit universal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a
HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on
the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When
OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2. Features
n
n
n
n
n
n
n
n
n
n
n
n
n
18-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA and −32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Negative edge-triggered clock inputs
Latch-up protection:
u JESD78: exceeds 500 mA
ESD protection:
u MIL STD 883 Method 3015: exceeds 2000 V
u CDM JESD22-C101-C exceeds 1000 V
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVT16500ADGG
−40 °C to +85 °C
TSSOP56
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
SOT364-1
74LVT16500ADL
−40 °C to +85 °C
SSOP56
plastic shrink small outline package; 56 leads;
body width 7.5 mm
SOT371-1
4. Functional diagram
1
OEAB
55
CPAB
2
LEAB
LEAB
OEAB
CPAB
LEBA
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
1
OEBA
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30 28 27 55 2
CPBA
27
OEBA
30
CPBA
28
LEBA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D
4
1
1
001aaf038
Fig 1. Logic symbol
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
001aaf039
Fig 2. IEC logic symbol
74LVT16500A_3
Product data sheet
1
6D
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
2 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
OEAB
CPAB
LEAB
LEBA
CPBA
OEBA
A0
1
55
2
28
30
27
3
1D
C1
CLK
54
B0
1D
C1
CLK
to 17 other channels
001aaf035
Fig 3. Logic diagram
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
3 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
5. Pinning information
5.1 Pinning
74LVT16500A
OEAB
1
56 GND
LEAB
2
55 CPAB
A0
3
54 B0
GND
4
53 GND
A1
5
52 B1
A2
6
51 B2
VCC
7
50 VCC
A3
8
49 B3
A4
9
48 B4
A5 10
47 B5
GND 11
46 GND
A6 12
45 B6
A7 13
44 B7
A8 14
43 B8
A9 15
42 B9
A10 16
41 B10
A11 17
40 B11
GND 18
39 GND
A12 19
38 B12
A13 20
37 B13
A14 21
36 B14
VCC 22
35 VCC
A15 23
34 B15
A16 24
33 B16
GND 25
32 GND
A17 26
31 B17
OEBA 27
30 CPBA
LEBA 28
29 GND
001aaf040
Fig 4. Pin configuration
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
OEAB
1
A-to-B output enable input
LEAB
2
A-to-B latch enable input
A0
3
data input/output A0
GND
4
ground (0 V)
A1
5
data input/output A1
A2
6
data input/output A2
VCC
7
supply voltage
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
4 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
Table 2.
Pin description …continued
Symbol
Pin
Description
A3
8
data input/output A3
A4
9
data input/output A4
A5
10
data input/output A5
GND
11
ground (0 V)
A6
12
data input/output A6
A7
13
data input/output A7
A8
14
data input/output A8
A9
15
data input/output A9
A10
16
data input/output A10
A11
17
data input/output A11
GND
18
ground (0 V)
A12
19
data input/output A12
A13
20
data input/output A13
A14
21
data input/output A14
VCC
22
supply voltage
A15
23
data input/output A15
A16
24
data input/output A16
GND
25
ground (0 V)
A17
26
data input/output A17
OEBA
27
B-to-A output enable input (active LOW)
LEBA
28
B-to-A latch enable input
GND
29
ground (0 V)
CPBA
30
B-to-A clock input (active falling edge)
B17
31
data input/output B17
GND
32
ground (0 V)
B16
33
data input/output B16
B15
34
data input/output B15
VCC
35
supply voltage
B14
36
data input/output B14
B13
37
data input/output B13
B12
38
data input/output B12
GND
39
ground (0 V)
B11
40
data input/output B11
B10
41
data input/output B10
B9
42
data input/output B9
B8
43
data input/output B8
B7
44
data input/output B7
B6
45
data input/output B6
GND
46
ground (0 V)
B5
47
data input/output B5
B4
48
data input/output B4
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
5 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
Table 2.
Pin description …continued
Symbol
Pin
Description
B3
49
data input/output B3
VCC
50
supply voltage
B2
51
data input/output B2
B1
52
data input/output B1
GND
53
ground (0 V)
B0
54
data input/output B0
CPAB
55
A-to-B clock input (active falling edge)
GND
56
ground (0 V)
6. Functional description
Table 3.
Function table[1]
Operating mode
Control
Input
Output
OEAB
LEAB
CPAB
An
OEBA
LEBA
CPBA
Bn
disabled
L
H
X
X
X
Z
disabled, latch data
L
↓
X
h
H
Z
disabled, latch data
L
↓
X
l
L
Z
disabled, hold data
L
L
H or L
X
NC
Z
Bn
An
disabled, clock data
L
L
↓
h
H
Z
disabled, clock data
L
L
↓
l
L
Z
transparent
H
H
X
H
H
H
transparent
H
H
X
L
L
L
latch data and display
H
↓
X
h
H
H
latch data and display
H
↓
X
l
L
L
clock data and display
H
L
↓
h
H
H
clock data and display
H
L
↓
l
L
L
hold data and display
H
L
H or L
X
H
H
hold data and display
H
L
H or L
X
L
L
[1]
H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the enable or clock transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the enable or clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
↓ = HIGH-to-LOW enable or clock transition.
74LVT16500A_3
Product data sheet
Internal
register
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
6 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
−0.5
+4.6
V
VI
input voltage
[1]
−0.5
+7.0
V
VO
output voltage
output in OFF-state or HIGH-state
[1]
−0.5
+7.0
V
IIK
input clamping current
VI < 0 V
-
−50
mA
IOK
output clamping current VO < 0 V
-
−50
mA
IO
output current
output in LOW-state
-
128
mA
output in HIGH-state
-
−64
mA
−65
+150
°C
-
150
°C
storage temperature
Tstg
[2]
junction temperature
Tj
[1]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
[2]
The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Min
Typ
Max Unit
VCC
Symbol Parameter
supply voltage
Conditions
2.7
-
3.6
V
VI
input voltage
0
-
5.5
V
VIH
HIGH-level input voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
IOH
HIGH-level output current
-
-
−32
mA
IOL
LOW-level output current none
-
-
32
mA
current duty cycle ≤ 50 %;
fi ≥ 1 kHz
-
-
64
mA
∆t/∆V
input transition rise and
fall rate
outputs enabled
-
-
10
ns/V
Tamb
ambient temperature
in free air
−40
-
+85
°C
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
7 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = −40 °C to 85
Conditions
Min
Typ
−0.85
Max
Unit
°C[1]
VIK
input clamping voltage
VCC = 2.7 V; IIK = −18 mA
-
−1.2
V
VOH
HIGH-level output voltage
VCC = 2.7 V to 3.6 V; IOH = −100 µA
VCC − 0.2 VCC
-
V
VCC = 2.7 V; IOH = −8 mA
2.4
2.55
-
V
VCC = 3.0 V; IOH = −32 mA
2.0
2.3
-
V
IOL = 100 µA
-
0.07
0.2
V
IOL = 24 mA
-
0.3
0.5
V
IOL = 16 mA
-
0.25
0.4
V
IOL = 32 mA
-
0.3
0.5
V
-
0.36
0.55
V
-
0.1
0.55
V
-
0.1
±1
µA
-
0.1
10
µA
VI = 5.5 V
-
1.0
20
µA
VI = VCC
-
0.1
10
µA
VI = 0 V
-
+0.1
−5
µA
-
1.0
±100
µA
VI = 0.8 V
75
130
-
µA
VI = 2.0 V
−75
−130
-
µA
VI = 0 V to 3.6 V; VCC = 3.6 V
±500
-
-
µA
-
50
125
µA
-
40
±100
µA
-
0.07
0.12
mA
-
4
6
mA
-
0.07
0.12
mA
VOL
LOW-level output voltage
VCC = 2.7 V
VCC = 3.0 V
IOL = 64 mA
VRST
power-up output low voltage VCC = 3.6 V; IO = 1 mA; VI = VCC or GND
ILI
input leakage current
control pins
[2]
VCC = 3.6 V; VI = VCC or GND
VCC = 0 V or 3.6 V; VI = 5.5 V
I/O data pins
IOFF
IHOLD
power-off leakage current
bus hold current data input
VCC = 3.6 V
[3]
VCC = 0 V; VI or VO = 0 V to 4.5 V
[4]
VCC = 3 V
IEX
external current into output
output in the HIGH-state when VO > VCC;
VO = 5.5 V; VCC = 3.0 V
IO(pu/pd)
power-up/power-down
output current
VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND
or VCC; OEAB or OEBA don’t care
ICC
quiescent supply current
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
[5]
outputs HIGH-state
outputs LOW-state
outputs disabled
74LVT16500A_3
Product data sheet
[6]
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
8 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
-
0.1
0.2
mA
∆ICC
additional quiescent supply
current
Ci
input capacitance
control pins; VI = 0 V or 3.0 V
-
3
-
pF
Cio
input/output capacitance
I/O pins; VI/O = 0 V or 3.0 V
-
9
-
pF
per input pin; VCC = 3 V to 3.6 V; one input
at VCC − 0.6 V; other inputs at VCC or GND
[7]
[1]
Typical values are at VCC = 3.3 V and Tamb = 25 °C.
[2]
For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3]
Unused pins at VCC or GND.
[4]
This is the bus hold overdrive current required to force the input to the opposite logic state.
[5]
This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.0 V ± 0.3 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
[6]
ICC is measured with outputs pulled to VCC or GND.
[7]
This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
An to Bn or Bn to An
see Figure 5
-
-
5.4
ns
CPAB to Bn or CPBA to An
see Figure 6
-
-
6.4
ns
LEAB to Bn or LEBA to An
see Figure 7
-
-
6.4
ns
An to Bn or Bn to An
see Figure 5
-
-
5.4
ns
CPAB to Bn or CPBA to An
see Figure 6
-
-
6.4
ns
LEAB to Bn or LEBA to An
see Figure 7
-
-
6.4
ns
VCC = 2.7 V; Tamb = −40 °C to 85 °C
tPLH
tPHL
propagation delay
propagation delay
tPZH
output enable time to HIGH-level
see Figure 8
-
-
5.5
ns
tPZL
output enable time to LOW-level
see Figure 9
-
-
5.2
ns
tPHZ
output disable time from HIGH-level see Figure 8
-
-
6.3
ns
tPLZ
output disable time from LOW-level
see Figure 9
-
-
5.6
ns
tsu(H)
setup time HIGH
An to CPAB or Bn to CPBA
see Figure 10
2.5
-
-
ns
An to LEAB with CPAB LOW or
Bn to LEBA with CPBA LOW
see Figure 10
2.2
-
-
ns
An to LEAB with CPAB HIGH or
Bn to LEBA with CPBA HIGH
see Figure 10
2.7
-
-
ns
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
9 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol
Parameter
tsu(L)
setup time LOW
th(H)
th(L)
tWH
tWL
Conditions
Min
Typ
Max
Unit
An to CPAB or Bn to CPBA
see Figure 10
2.5
-
-
ns
An to LEAB with CPAB LOW or
Bn to LEBA with CPBA LOW
see Figure 10
2.2
-
-
ns
An to LEAB with CPAB HIGH or
Bn to LEBA with CPBA HIGH
see Figure 10
2.7
-
-
ns
An to CPAB or Bn to CPBA
see Figure 10
0
-
-
ns
An to LEAB or Bn to LEBA
see Figure 10
0
-
-
ns
An to CPAB or Bn to CPBA
see Figure 10
0
-
-
ns
An to LEAB or Bn to LEBA
see Figure 10
0
-
-
ns
CPAB or CPBA
see Figure 6
1.5
-
-
ns
LEAB or LEBA
see Figure 7
1.5
-
-
ns
see Figure 6
1.5
-
-
ns
An to Bn or Bn to An
see Figure 5
0.5
1.9
4.2
ns
CPAB to Bn or CPBA to An
see Figure 6
1.0
3.2
5.4
ns
LEAB to Bn or LEBA to An
see Figure 7
1.0
2.4
5.4
ns
An to Bn or Bn to An
see Figure 5
0.5
1.9
4.2
ns
CPAB to Bn or CPBA to An
see Figure 6
1.0
3.2
5.4
ns
LEAB to Bn or LEBA to An
see Figure 7
1.0
2.9
5.4
ns
hold time HIGH
hold time LOW
pulse width HIGH
pulse width LOW
CPAB or CPBA
VCC = 3.0 V ± 0.3 V; Tamb = −40 °C to 85
tPLH
tPHL
°C[1]
propagation delay
propagation delay
tPZH
output enable time to HIGH-level
see Figure 8
1.0
2.4
4.8
ns
tPZL
output enable time to LOW-level
see Figure 9
1.0
2.2
4.8
ns
tPHZ
output disable time from HIGH-level see Figure 8
1.0
2.8
5.8
ns
tPLZ
output disable time from LOW-level
see Figure 9
1.0
3.2
5.2
ns
tsu(H)
setup time HIGH
An to CPAB or Bn to CPBA
see Figure 10
2.4
1.0
-
ns
An to LEAB with CPAB LOW or
Bn to LEBA with CPBA LOW
see Figure 10
2.3
0.9
-
ns
An to LEAB with CPAB HIGH or
Bn to LEBA with CPBA HIGH
see Figure 10
2.4
0.9
-
ns
An to CPAB or Bn to CPBA
see Figure 10
2.4
0.7
-
ns
An to LEAB with CPAB LOW or
Bn to LEBA with CPBA LOW
see Figure 10
2.3
0.9
-
ns
An to LEAB with CPAB HIGH or
Bn to LEBA with CPBA HIGH
see Figure 10
2.4
0.8
-
ns
tsu(L)
setup time LOW
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
10 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
th(H)
hold time HIGH
An to CPAB or Bn to CPBA
see Figure 10
0
0
-
ns
An to LEAB or Bn to LEBA
see Figure 10
0
0
-
ns
An to CPAB or Bn to CPBA
see Figure 10
0
0
-
ns
An to LEAB or Bn to LEBA
see Figure 10
0
0
-
ns
CPAB or CPBA
see Figure 6
1.2
0.8
-
ns
LEAB or LEBA
see Figure 7
1.2
0.8
-
ns
see Figure 6
1.2
0.8
-
ns
see Figure 6
150
350
-
MHz
hold time LOW
th(L)
pulse width HIGH
tWH
tWL
pulse width LOW
fmax
maximum input clock frequency
CPAB or CPBA
[1]
All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
11. Waveforms
VI
input
An or Bn
VM
VM
0V
t PLH
t PHL
VOH
output
Bn or An
VM
VM
VOL
001aad308
Measurements points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 5. Propagation delay input (An, Bn) to output (Bn, An) in transparent mode
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
11 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
1/fmax
VI
input CPBA
or CPAB
VM
VM
0V
t WL
t WH
t PHL
t PLH
VOH
VM
output An or Bn
VM
VOL
001aaf037
Measurements points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 6. Propagation delay clock (CPAB, CPBA) to output (An, Bn), clock (CPAB, CPBA)
pulse width and maximum clock frequency (CPAB, CPBA)
VI
input LEAB
or LEBA
VM
VM
VM
0V
t WH
t PHL
t PLH
VOH
output
An or Bn
VM
VM
VOL
001aad310
Measurements points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 7. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) and latch enable
(LEAB, LEBA) pulse width
OEBA
VI
VM
input
OEAB
VM
0V
t PZH
t PHZ
VOH
output
An or Bn
VY
VM
0V
001aad344
Measurements points are given in Table 8.
VOH is typical voltage output drop that occur with the output load.
Fig 8. 3-state output enable time to HIGH-level and output disable time from HIGH-level
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
12 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
VI
OEBA
VM
input
VM
0V
OEAB
t PZL
t PLZ
3.0 V or VCC
output
An or Bn
VM
VX
VOL
001aad346
Measurements points are given in Table 8.
VOL is typical voltage output drop that occur with the output load.
Fig 9. 3-state output enable time to LOW-level and output disable time from LOW-level
CPAB or CPBA
VM
VM
input
LEAB or LEBA
0V
t su(H)
input An, Bn
3.0 V or VCC
whichever is
less
t h(H)
VM
VM
t su(L)
VM
t h(L)
VM
3.0 V or VCC
whichever is
less
0V
001aaf036
Measurements points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 10. Data setup and hold times
Table 8.
Measurement points
Supply voltage
Input
Output
VM
VM
VX
VY
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
3.3 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
13 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
PULSE
GENERATOR
VI
RL
VO
DUT
RT
CL
RL
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 11. Load circuitry for switching times
Table 9.
Test data
Input
Load
VI
fi
tW
2.7 V
≤ 10 MHz 500 ns
CL
RL
tPHZ, tPZH tPLZ, tPZL tPLH, tPHL
≤ 2.5 ns
50 pF
500 Ω
GND
74LVT16500A_3
Product data sheet
VEXT
tr, tf
6V
open
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
14 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
12. Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
HE
y
v M A
Z
56
29
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
detail X
28
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.5
0.1
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT364-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 12. Package outline SOT364-1 (TSSOP56)
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
15 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
D
E
A
X
c
y
HE
v M A
Z
29
56
Q
A2
A1
A
(A 3)
θ
pin 1 index
Lp
L
28
1
bp
e
0
detail X
w M
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.8
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22
0.13
18.55
18.30
7.6
7.4
0.635
10.4
10.1
1.4
1.0
0.6
1.2
1.0
0.25
0.18
0.1
0.85
0.40
8
o
0
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT371-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-118
Fig 13. Package outline SOT371-1 (SSOP56)
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
16 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
BiCMOS
Bipolar Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVT16500A_3
20060529
Product data sheet
-
74LVT16500A_2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors
•
•
•
Section 2 “Features”: replaced JEDEC JC40.2 Std 17 with JESD78
Figure 3 “Logic diagram”: corrected clock names and pin names
Table 7 “Dynamic characteristics”: splitting up tsu(H) and tsu(L) parameter ‘An to LEAB or Bn
to LEBA’ in 2 parameters with clock conditions and new values
74LVT16500A_2
(9397 750 03556)
19980219
Product specification
-
74LVT16500A_1
74LVT16500A_1
19970612
Product specification
-
74LVT16500A
74LVT16500A
19950320
Product specification
-
-
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
17 of 19
74LVT16500A
Philips Semiconductors
3.3 V 18-bit universal bus transceiver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.semiconductors.philips.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Philips Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Philips Semiconductors
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, Philips Semiconductors does not give any representations
or warranties, expressed or implied, as to the accuracy or completeness of
such information and shall have no liability for the consequences of use of
such information.
Right to make changes — Philips Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — Philips Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a Philips Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Philips Semiconductors accepts no liability for inclusion and/or use
of Philips Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is for the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Philips Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — Philips Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.semiconductors.philips.com/profile/terms, including those
pertaining to warranty, intellectual property rights infringement and limitation
of liability, unless explicitly otherwise agreed to in writing by Philips
Semiconductors. In case of any inconsistency or conflict between information
in this document and such terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: [email protected]
74LVT16500A_3
Product data sheet
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 03 — 29 May 2006
18 of 19
Philips Semiconductors
74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© Koninklijke Philips Electronics N.V. 2006.
All rights reserved.
For more information, please visit: http://www.semiconductors.philips.com.
For sales office addresses, email to: [email protected].
Date of release: 29 May 2006
Document identifier: 74LVT16500A_3