Revised January 2000 74LVTH16652 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs General Description Features The LVTH16652 consists of sixteen bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function (see Functional Description). ■ Input and output interface capability to systems at 5V VCC The LVTH16652 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. ■ Latch-up performance exceeds 500 mA ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink −32 mA/+64 mA ■ Functionally compatible with the 74 series 16652 The transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16652 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Ordering Code: Order Number Package Number 74LVTH16652MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Description 74LVTH16652MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation DS012024 www.fairchildsemi.com 74LVTH16652 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs January 2000 74LVTH16652 Connection Diagram Pin Descriptions Pin Names A0–A15 Description Data Register A Inputs/ 3-STATE Outputs B0–B15 Data Register B Inputs/ 3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs SABn, SBAn Select Inputs OEABn, OEBAn Output Enable Inputs Truth Table (Note 1) Inputs Inputs/Outputs OEAB1 OEBA1 CPAB1 CPBA1 SAB1 L H L H X H H H L X L L H or L H or L SBA1 X X X X H or L X A0 thru A7 Operating Mode B0 thru B7 Input Input Isolation X Input Not Specified Store A, Hold B X X Input Output X X Not Specified Input Hold A, Store B Store A and B Data H or L L X X Output Input Store B in Both Registers L X X X L Output Input Real-Time B Data to A Bus Input Output Output Output L L X H or L X H H H X X L X H H H or L X H X H L H or L H or L H H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Store A in Both Registers Store B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus = LOW-to-HIGH Clock Transition Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. This also applies to data I/O (A and B: 8–15) and #2 control pins www.fairchildsemi.com 2 74LVTH16652 Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LVTH16652 Functional Description Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inputs (CPABn, CPBAn) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEABn and OEBAn. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples below demonstrate the four fundamental bus-management functions that can be performed with the LVTH16652. Real-Time Transfer Bus B to Bus A Storage L L X X X L X H L X L H Real-Time Transfer Bus A to Bus B H www.fairchildsemi.com X X X X X X X X X X Transfer Storage Data to A or B OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 H OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 L OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 X H 4 L H or L H or L H H Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE −0.5 to +7.0 Output in HIGH or LOW State (Note 3) V V V IIK DC Input Diode Current −50 VI < GND mA IOK DC Output Diode Current −50 VO < GND mA IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage IOH HIGH-Level Output Current IOL LOW-Level Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Units 2.7 3.6 V 0 5.5 V −32 mA 64 mA −40 85 °C 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. 5 www.fairchildsemi.com 74LVTH16652 Absolute Maximum Ratings(Note 2) 74LVTH16652 DC Electrical Characteristics T A = −40°C to +85°C Symbol Parameter VCC Min Max Units Conditions (V) −1.2 VIK Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 2.7 2.4 3.0 2.0 VOL II(HOLD) 2.7 Output LOW Voltage Bushold Input Minimum Drive 2.0 0.8 IOH = −8 mA IOH = −32 mA IOL = 100 µA 2.7 0.5 IOL = 24 mA 3.0 0.4 3.0 0.5 3.0 0.55 75 3.0 V 500 IOL = 64 mA µA Power Off Leakage Current IPU/PD Power up/down 3-STATE VI = 0.8V VI = 2.0V (Note 4) (Note 5) VI = 5.5V 3.6 10 Control Pins 3.6 ±1 Data Pins 3.6 −5 0 ±100 µA 0V ≤ VI or VO ≤ 5.5V 0–1.5V ±100 µA VO = 0.5V to 3.0V −5 µA VO = 0.0V VO = 3.6V µA VI = 0V or VCC VI = 0V VI = VCC 1 IOFF IOL = 16 mA IOL = 32 mA µA −500 Input Current V 0.2 Current to Change State II V 2.7 3.0 Bushold Input Over-Drive II = −18 mA VO ≤ 0.1V or VO ≥ VCC − 0.1V IOH = −100 µA −75 II(OD) V V VI = GND or VCC Output Current IOZL 3-STATE Output Leakage Current 3.6 IOZH 3-STATE Output Leakage Current 3.6 5 µA IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < VO ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA VCC ≤ VO ≤ 5.5V, ∆ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC − 0.6V Outputs Disabled (Note 6) Other Inputs at VCC or GND Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 7) TA = 25°C VCC (V) Min Typ Max Units Conditions CL = 50 pF RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 8) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 8) Note 7: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. www.fairchildsemi.com 6 TA = −40°C to +85°C Symbol CL = 50 pF, RL = 500Ω Parameter VCC = 3.3V ± 0.3V Min Max VCC = 2.7V Min Max fMAX Maximum Clock Frequency 150 tPHL Propagation Delay 1.3 4.8 1.3 5.4 150 MHz tPLH CPAB or CPBA to A or B 1.3 5.1 1.3 5.6 tPHL Propagation Delay 1.0 4.5 1.0 5.1 tPLH Data to A or B 1.0 4.4 1.0 4.7 tPHL Propagation Delay 1.0 4.9 1.0 5.5 tPLH SBA or SAB to A or B 1.0 4.8 1.0 5.4 tPZL Output Enable Time 1.0 4.9 1.0 5.8 tPZH OE to A 1.0 4.8 1.0 5.8 tPLZ Output Disable Time 1.6 5.6 1.6 6.1 tPHZ OE to A 2.0 5.4 2.0 6.1 tPZL Output Enable Time 1.3 5.0 1.3 5.4 tPZH OE to B 1.3 4.8 1.3 5.4 tPLZ Output Disable Time 1.3 5.5 1.3 6.2 tPHZ OE to B 1.3 5.6 1.3 6.3 tS Setup Time Hold Time tH A or B before CPAB or CPBA, Data HIGH 1.2 1.5 A or B before CPAB or CPBA, Data LOW 2.0 2.8 A or B before CPAB or CPBA, Data HIGH 0.5 0.0 A or B before CPAB or CPBA, Data LOW 0.5 0.5 CPAB or CPBA HIGH or LOW 3.3 tW Pulse Width tOSHL Output to Output Skew (Note 9) tOSLH Units ns ns ns ns ns ns ns ns ns 3.3 ns 1.0 1.0 1.0 1.0 ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 10) Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC Conditions 4 pF CI/O Input/Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 7 www.fairchildsemi.com 74LVTH16652 AC Electrical Characteristics 74LVTH16652 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A www.fairchildsemi.com 8 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com 74LVTH16652 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)