Revised September 2000 74ACT652 Transceiver/Register General Description Features The ACT652 consists of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. ■ Independent registers for A and B buses ■ Multiplexed real-time and stored data ■ Outputs source/sink 24 mA ■ TTL-compatible inputs Ordering Code: Order Number 74ACT652SC Package Number M24B 74ACT652MTC MTC24 74ACT652SPC N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description A0–A7, B0–B7 A and B Inputs/3-STATE Outputs CPAB, CPBA Clock Inputs SAB, SBA Select Inputs OEAB, OEBA Output Enable Inputs FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS500310 www.fairchildsemi.com 74ACT652 Transceiver/Register August 1999 74ACT652 Function Table Inputs Inputs/Outputs (Note 1) Operating Mode OEAB OEBA CPAB CPBA SAB SBA L H H or L H or L X X L H X X X X Input Not Specified X X Input Output Store A in Both Registers X X Not Specified Input Hold A, Store B X X Output Input Store B in Both Registers Output Input X H H H L X L L L L X X X L L L X H or L X H H H X X L X H H H or L X H X H L H or L H or L H H H or L H or L A0 thru A7 Input B0 thru B7 Input Isolation Store A and B Data Store A, Hold B Real-Time B Data to A Bus Store B Data to A Bus Input Output Real-Time A Data to B Bus Stored A Data to B Bus Output Output Stored A Data to B Bus and Stored B Data to A Bus H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Data on the A or B data bus, or both can be stored in the internal D-type flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the Octal bus transceivers and receivers. Note A: Real-Time Note B: Real-Time Transfer Bus B to Bus A Transfer Bus A to Bus B OEAB OEBA CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA L L X X X L H H X X L X Note C: Storage Note D: Transfer Storage Data to A or B OEAB OEBA X H L X L H CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA X H L H or L H or L H H X X X X X X X FIGURE 1. 3 www.fairchildsemi.com 74ACT652 Functional Description 74ACT652 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) 0V to VCC Output Voltage (VO) −0.5V to VCC + 0.5V 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 4.5V to 5.5V Input Voltage (VI) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to VCC + 0.5V 125 mV/ns DC Output Source ± 50 mA or Sink Current (IO) DC VCC or Ground Current ± 50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150°C DC Latch-Up Source ± 300 mA or Sink Current Junction Temperature (TJ) 140°C PDIP DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = +25°C VCC TA = −40°C to +85°C (V) Typ Guaranteed Limits Minimum HIGH Level 4.5 1.5 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 2.0 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 Units V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH VOL 4.5 3.86 3.76 5.5 4.86 4.76 V IOH = −24 mA IOH = −24 mA (Note 3) Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.1 ± 1.0 µA 5.5 ± 0.6 ± 6.0 µA 1.5 mA VI = VCC − 2.1V V IOUT = 50 µA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZT Maximum I/O Leakage Current IOL = 24 mA IOL = 24 mA (Note 3) VI = VCC, GND VI = VIL, VIH VO = VCC, GND ICCT Maximum ICC/Input 5.5 IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 4) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 80.0 µA VIN = VCC or GND Supply Current 0.6 V 5.5 8.0 Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. www.fairchildsemi.com 4 Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 5) fMAX Max. Clock Frequency tPLH Propagation Delay tPHL Clock to Bus tPLH Propagation Delay tPHL Bus to Bus tPLH Propagation Delay tPHL SBA or SAB to A or B tPZH Enable Time tPZL OEBA to A (Note 5) tPHZ Disable Time tPLZ OEBA to A (Note 5) tPZH Enable Time tPZL OEAB to B tPHZ Disable Time tPLZ OEAB to B ts(H) Setup Time, HIGH or ts(L) LOW, Bus to Clock th(H) Hold Time, HIGH or th(L) LOW, Bus to Clock tw(H) Clock Pulse Width tw(L) HIGH or LOW Min Typ TA = −40°C to +85°C CL = 50 pF Max Min Units Max 5.0 MHz 5.0 2.0 7.0 9.5 2.0 10.0 ns 5.0 2.0 6.5 9.0 2.0 9.5 ns 5.0 2.5 6.5 10.0 2.5 10.5 ns 5.0 2.0 7.0 10.5 2.0 11.0 5.0 1.0 5.0 8.0 1.0 8.5 5.0 2.0 7.0 10.5 2.0 11.0 5.0 1.0 5.0 8.0 1.0 8.5 5.0 3.0 3.0 ns 5.0 1.5 1.5 ns 5.0 4.0 4.0 ns ns ns Note 5: Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 54 pF VCC = 5.0V 5 Conditions www.fairchildsemi.com 74ACT652 AC Electrical Characteristics 74ACT652 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B www.fairchildsemi.com 6 74ACT652 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 7 www.fairchildsemi.com 74ACT652 Transceiver/Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8