MAXIM MAX5864ETM

19-2915; Rev 1; 10/03
KIT
ATION
EVALU
E
L
B
AVAILA
Ultra-Low-Power, High-DynamicPerformance, 22Msps Analog Front End
Applications
Features
♦ Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs
♦ Ultra-Low Power
42mW at fCLK = 22MHz (Transceiver Mode)
34mW at fCLK = 15.36MHz (Transceiver Mode)
Low-Current Idle and Shutdown Modes
♦ Excellent Dynamic Performance
48.5dB SINAD at fIN = 5.5MHz (ADC)
71.7dB SFDR at fOUT = 2.2MHz (DAC)
♦ Excellent Gain/Phase Match
±0.1° Phase, ±0.03dB Gain at fIN = 5.5MHz (ADC)
♦ Internal/External Reference Option
♦ +1.8V to +3.3V Digital Output Level (TTL/CMOS
Compatible)
♦ Multiplexed Parallel Digital Input/Output for
ADCs/DACs
♦ Miniature 48-Pin Thin QFN Package (7mm ✕ 7mm)
♦ Evaluation Kit Available (Order MAX5865EVKIT)
Functional Diagram
IA+
ADC
IA-
ADC
OUTPUT
MUX
QA+
QA-
Narrowband/Wideband CDMA Handsets
and PDAs
ID+
Fixed/Mobile Broadband Wireless Modems
ID-
ADC
CLK
DAC
DAC
INPUT
MUX
3G Wireless Terminals
QD+
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX5864ETM
-40°C to +85°C
48 Thin QFN-EP*
(7mm x 7mm)
MAX5864E/D
-40°C to +85°C
Dice**
*EP = Exposed paddle.
**Contact factory for dice specifications.
DA0–DA7
DD0–DD9
DAC
QDREFP
COM
REFN
REFIN
REF AND
BIAS
SERIAL
INTERFACE
AND SYSTEM
CONTROL
DIN
SCLK
CS
MAX5864
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5864
General Description
The MAX5864 ultra-low-power, highly integrated analog
front end is ideal for portable communication equipment
such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5864 integrates dual 8-bit receive ADCs
and dual 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs’
analog I-Q input amplifiers are fully differential and
accept 1VP-P full-scale signals. Typical I-Q channel
phase matching is ±0.1° and amplitude matching is
±0.03dB. The ADCs feature 48.5dB SINAD and 69dBc
spurious-free dynamic range (SFDR) at fIN = 5.5MHz and
fCLK = 22Msps. The DACs’ analog I-Q outputs are fully
differential with ±400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase match is
±0.15° and amplitude match is ±0.05dB. The DACs also
feature dual 10-bit resolution with 71.7dBc SFDR, and
57dB SNR at fOUT = 2.2MHz and fCLK = 22MHz.
The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface
controls power-down and transceiver modes of operation. The typical operating power is 42mW at fCLK =
22Msps with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5864 features an
internal 1.024V voltage reference that is stable over the
entire operating power-supply range and temperature
range. The MAX5864 operates on a +2.7V to +3.3V analog power supply and a +1.8V to +3.3V digital I/O power
supply for logic compatibility. The quiescent current is
5.6mA in idle mode and 1µA in shutdown mode. The
MAX5864 is specified for the extended (-40°C to +85°C)
temperature range and is available in a 48-pin thin QFN
package.
MAX5864
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
ABSOLUTE MAXIMUM RATINGS
VDD to GND, OVDD to OGND................................-0.3V to +3.3V
GND to OGND.......................................................-0.3V to +0.3V
IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN,
REFIN, COM to GND ..............................-0.3V to (VDD + 0.3V)
DD0–DD9, SCLK, DIN, CS, CLK,
DA0–DA7 to OGND .............................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
48-Pin Thin QFN (derate 26.3mW/°C above +70°C) ..........2.1W
Thermal Resistance θJA .................................................+38°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.7
3.0
3.3
V
VDD
V
POWER REQUIREMENTS
Analog Supply Voltage
VDD
Output Supply Voltage
OVDD
1.8
ADC operating mode, fIN = 5.5MHz, fCLK =
22MHz, DAC operating mode, fOUT = 2.2MHz
VDD Supply Current
ADC operating mode, fIN = 5.5MHz, fCLK =
15.36MHz, DAC operating mode, fOUT =
2.2MHz
11.4
ADC operating mode (Rx), fIN = 5.5MHz,
fCLK = 15.36MHz, DAC off, DAC digital
inputs at zero or DVDD
8.25
DAC operating mode (Tx), fOUT = 2.2MHz,
fCLK = 15.36MHz, ADC off
2
16.5
mA
8
Standby mode, DAC digital inputs and CLK
at zero or OVDD
2.0
Idle mode, DAC digital inputs at zero or
OVDD, fCLK = 22MHz
6.7
Shutdown mode, digital inputs and CLK at
zero or OVDD, CS = OVDD
OVDD Supply Current
14
1
µA
ADC operating mode, fIN = 5.5MHz, fCLK =
22MHz, DAC operating mode, fOUT = 2.2MHz
2.3
mA
Idle mode, DAC digital inputs at zero or
OVDD, fCLK = 22MHz
20.6
Shutdown mode, DAC digital inputs and
CLK at zero or OVDD, CS = OVDD
1
µA
_______________________________________________________________________________________
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC DC ACCURACY
Resolution
8
Bits
±0.15
LSB
No missing codes over temperature
±0.15
LSB
Offset Error
Residual DC offset error
±0.24
±5
%FS
Gain Error
Includes reference error
±0.77
±5
%FS
±0.03
±0.25
dB
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
DC Gain Matching
Offset Matching
±3
LSB
Gain Temperature Coefficient
±59
ppm/°C
Power-Supply Rejection
PSRR
Offset error (VDD ±5%)
±0.2
Gain error (VDD ±5%)
±0.07
Differential or single-ended inputs
±0.512
V
VDD / 2
V
245
kΩ
5
pF
LSB
ADC ANALOG INPUT
Input Differential Range
VID
Input Common-Mode Voltage
Range
RIN
Input Impedance
Switched capacitor load
CIN
ADC CONVERSION RATE
Maximum Clock Frequency
fCLK
Data Latency
(Note 2)
22
Channel I
5
Channel Q
5.5
MHz
Clock
cycles
ADC DYNAMIC CHARACTERISTICS (Note 3)
Signal-to-Noise Ratio
SNR
fIN = 5.5MHz
47
fIN = 11MHz
fIN = 5.5MHz
48.6
dB
48.6
46.5
48.5
Signal-to-Noise and Distortion
Ratio
SINAD
Spurious-Free Dynamic Range
SFDR
Third-Harmonic Distortion
HD3
Intermodulation Distortion
IMD
f1 = 2MHz, -7dBFS; f2 = 2.01MHz, -7dBFS
-64
dBc
Third-Order Intermodulation
Distortion
IM3
f1 = 2MHz, -7dBFS; f2 = 2.01MHz, -7dBFS
-67
dBc
Total Harmonic Distortion
THD
fIN = 11MHz
fIN = 5.5MHz
dB
48.5
58
69
fIN = 11MHz
71.5
fIN = 5.5MHz
-70.3
fIN = 11MHz
-75.5
fIN = 5.5MHz
-68.2
fIN = 11MHz
-68
dBc
dBc
-57
dBc
_______________________________________________________________________________________
3
MAX5864
ELECTRICAL CHARACTERISTICS (continued)
MAX5864
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Small-Signal Bandwidth
SSBW
AIN = -20dBFS
440
MHz
Large-Signal Bandwidth
FBW
AIN = -0.5dBFS
440
MHz
Aperture Delay
3.3
ns
Aperture Jitter
2.7
psRMS
2
ns
-75
dB
1.5 × full-scale input
Overdrive Recovery Time
ADC INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
fINX = 5.5MHz at -0.5dBFS, fINY = 0.3MHz at
-0.5dBFS (Note 5)
Amplitude Matching
fIN = 5.5MHz at -0.5dBFS (Note 6)
±0.03
dB
Phase Matching
fIN = 5.5MHz at -0.5dBFS (Note 6)
±0.1
Degrees
DAC DC ACCURACY
Resolution
N
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
10
Guaranteed monotonic
Zero-Scale Error
Residual DC offset
Full-Scale Error
Include Reference Error
Bits
±1
LSB
±0.5
LSB
±3
LSB
-35
+35
LSB
22
Msps
DAC DYNAMIC PERFORMANCE
DAC Conversion Rate
Noise over Nyquist
Output-of-Band Noise Power
Density
Adjacent Channel Power Ratio
(Note 2)
ND
fOUT = 2.2MHz, fCLK = 22MHz
-128.4
dBc/Hz
NO
fOUT = 1.2MHz, fCLK = 15.36MHz, offset =
10MHz
-131.5
dBc/Hz
57
dB
10
pVs
ACPR
WCDMA at offset = 5MHz, fCLK =
15.36Msps
Glitch Impulse
Spurious-Free Dynamic Range
SFDR
Total Harmonic Distortion
(to Nyquist)
Signal-to-Noise Ratio
(to Nyquist)
fCLK = 22MHz
fOUT = 2.2MHz
60
71.7
dBc
fCLK = 15.36MHz fOUT = 200kHz
72.5
THD
fCLK = 22MHz, fOUT = 2.2MHz
-70
SNR
fCLK = 22MHz, fOUT = 2.2MHz
57
dB
DAC-to-DAC Output Isolation
fOUTX, Y = 2.2MHz, fOUTX, Y = 2.0MHz
80
dB
Gain Mismatch Between DAC
Outputs
fOUT = 2.2MHz, fCLK = 22MHz
±0.05
dB
Phase Mismatch Between DAC
Outputs
fOUT = 2.2MHz, fCLK = 22MHz
±0.15
Degrees
-59
dB
DAC INTERCHANNEL CHARACTERISTICS
4
_______________________________________________________________________________________
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC ANALOG OUTPUT
Full-Scale Output Voltage
±400
VFS
Output Common-Mode Range
1.29
mV
1. 5
V
ADC-DAC INTERCHANNEL CHARACTERISTICS
ADC-DAC Isolation
ADC fINI = fINQ = 5.5MHz, DAC fOUTI =
fOUTQ = 2.2MHz, fCLK = 22MHz
75
dB
ADC-DAC TIMING CHARACTERISTICS
CLK Rise to I-ADC Channel-I
Output Data Valid
tDOI
Figure 3 (Note 4)
7.4
9
ns
CLK Fall to Q-ADC Channel-Q
Output Data Valid
tDOQ
Figure 3 (Note 4)
6.9
9
ns
I-DAC Data to CLK Fall Setup
Time
tDSI
Figure 4 (Note 4)
10
ns
Q-DAC Data to CLK Rise Setup
Time
tDSQ
Figure 4 (Note 4)
10
ns
CLK Fall to I-DAC Data Hold Time
tDHI
Figure 4 (Note 4)
0
ns
CLK Rise to Q-DAC Data Hold Time
tDHQ
Figure 4 (Note 4)
0
Clock Duty Cycle
ns
50
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
20% to 80%
%
±15
%
2.6
ns
SERIAL INTERFACE TIMING CHARACTERISTICS
Falling Edge of CS to Rising Edge
of First SCLK Time
tCSS
Figure 5 (Note 4)
10
ns
DIN to SCLK Setup Time
tDS
Figure 5 (Note 4)
10
ns
DIN to SCLK Hold Time
tDH
Figure 5 (Note 4)
0
ns
SCLK Pulse Width High
tCH
Figure 5 (Note 4)
25
ns
SCLK Pulse Width Low
tCL
Figure 5 (Note 4)
25
ns
SCLK Period
tCP
Figure 5 (Note 4)
50
ns
SCLK to CS Setup Time
tCS
Figure 5 (Note 4)
0
ns
tCSW
Figure 5 (Note 4)
80
ns
CS High Pulse Width
MODE RECOVERY TIMING CHARACTERISTICS
Shutdown Wake-Up Time
tWAKE,SD
From shutdown to Rx mode, Figure 6, ADC
settles to within 1dB
20
From shutdown to Tx mode, Figure 6, DAC
settles to within 1 LSB error
40
µs
_______________________________________________________________________________________
5
MAX5864
ELECTRICAL CHARACTERISTICS (continued)
MAX5864
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
From idle to Rx mode with CLK present
during idle, Figure 6, ADC settles to within
1dB SINAD
Idle Wake-Up Time (with CLK)
Standby Wake-Up Time
TYP
MAX
10
µs
tWAKE,ST
tWAKE,St1
UNITS
From idle to Tx mode with CLK present
during idle, Figure 6, DAC settles to 10 LSB
error
10
From standby to Rx mode, Figure 6, ADC
settles to within 1dB SINAD
10
From standby to Tx mode, Figure 6, DAC
settles to 10 LSB error
40
µs
Enable Time from Xcvr or Tx to Rx
tENABLE, Rx ADC settles to within 1dB SINAD
10
µs
Enable Time from Xcvr or Rx to Tx
tENABLE, Tx DAC settles to 1 LSB error
10
µs
0.256
V
-0.256
V
VDD / 2
V /2
VDD / 2 DD
- 0.15
+ 0.15
V
INTERNAL REFERENCE (REFIN = VDD. VREFP, VREFN, and VCOM are generated internally)
Positive Reference
VREFP - VCOM
Negative Reference
VREFN - VCOM
Common-Mode Output Voltage
VCOM
Differential Reference Output
VREF
Differential Reference
Temperature Coefficient
VREFP - VREFN
+0.49
+0.512 +0.534
V
REFTC
±30
ppm/°C
Maximum REFP/REFN/COM
Source Current
ISOURCE
2
mA
Maximum REFP/REFN/COM
Sink Current
ISINK
2
mA
1.024
V
0.512
V
BUFFERED EXTERNAL REFERENCE (REFIN = 1.024V. VREFP, VREFN, and VCOM are generated internally)
Reference Input
VREFIN
Differential Reference Output
VDIFF
Common-Mode Output Voltage
VREFP - VREFN
VCOM
VDD / 2
V
Maximum REFP/REFN/COM
Source Current
ISOURCE
2
mA
Maximum REFP/REFN/COM
Sink Current
ISINK
2
mA
>500
kΩ
-0.7
µA
REFIN Input Resistance
REFIN Input Current
DIGITAL INPUTS (CLK, SCLK, DIN, CS, DD0–DD9)
Input High Threshold
6
VINH
DD0–DD9, CLK, SCLK, DIN, CS
0.7 x
OVDD
_______________________________________________________________________________________
V
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.3 x
OVDD
Input Low Threshold
VINL
DD0–DD9, CLK, SCLK, DIN, CS
Input Leakage
DIIN
DD0–DD9, CLK, SCLK, DIN, CS = OGND or
OVDD
Input Capacitance
DCIN
±5
UNITS
V
µA
5
pF
DIGITAL OUTPUTS (DA0–DA7)
0.2 x
OVDD
Output Voltage Low
VOL
ISINK = 200µA
Output Voltage High
VOH
ISOURCE = 200µA
Tri-State Leakage Current
ILEAK
Tri-State Output Capacitance
COUT
0.8 x
OVDD
V
V
±5
µA
5
pF
Note 1: Specifications from TA = +25°C to +85°C are guaranteed by product tests. Specifications from TA = +25°C to -40°C are
guaranteed by design and characterization.
Note 2: The minimum clock frequency for the MAX5864 is 7.5MHz.
Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 4: Guaranteed by design and characterization.
Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tone bins.
Note 6: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
Typical Operating Characteristics
(VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz 50% duty cycle, ADC
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN =
CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
-40
-50
HD3
-60
HD2
QA
-70
-30
-40
-50
-60
-80
-90
-100
-100
-110
-110
2
3
4
5
6
7
FREQUENCY (MHz)
8
9 10 11
HD3
HD2
IA
-70
-90
1
QA
-20
-30
F1
fCLK = 22MHz
f1 = 1.8MHz
f2 = 2.2MHz
AIA = -7dBFS PER TONE
8192-POINT
DATA RECORD
F2
-40
-50
MAX5864 toc03
-20
-80
0
fCLK = 22MHz
fIA = 5.50885MHz
fQA = 7.9787MHz
AIA = AQA = -0.5dBFS
8192-POINT
DATA RECORD
-10
ADC CHANNEL-IA TWO-TONE FFT PLOT
0
-10
AMPLITUDE (dBFS)
-30
IA
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-20
MAX5864 toc01
fCLK = 22MHz
fIA = 5.50885MHz
fQA = 7.9787MHz
AIA = AQA = -0.5dBFS
8192-POINT
DATA RECORD
-10
ADC CHANNEL-QA FFT PLOT
0
MAX5864 toc02
ADC CHANNEL-IA FFT PLOT
0
-60
-70
-80
-90
-100
-110
-120
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
8
9 10 11
0
1
2
3
4
5
6
7
8
9 10 11
FREQUENCY (MHz)
_______________________________________________________________________________________
7
MAX5864
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz 50% duty cycle, ADC
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN =
CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
-40
-60
IA
49
48
48
-50
MAX5864 toc06
F2
IA
QA
47
SINAD (dB)
F1
-30
49
50
MAX5864 toc05
fCLK = 22MHz
f1 = 1.8MHz
f2 = 2.2MHz
AIA = -7dBFS PER TONE
8192-POINT
DATA RECORD
SNR (dB)
AMPLITUDE (dBFS)
-20
50
MAX5864 toc04
0
-10
ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT FREQUENCY
ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
ADC CHANNEL-QA TWO-TONE FFT PLOT
46
QA
47
46
-70
45
45
-80
44
44
43
43
-90
-100
-110
42
42
1
2
3
4
5
6
7
8
9 10 11
0
25
50
75
100
0
125
25
50
75
100
125
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
80
MAX5864 toc07
-50
-55
80
75
MAX5864 toc09
FREQUENCY (MHz)
MAX5864 toc08
0
SINGLE ENDED
75
70
SFDR (dBc)
THD (dB)
-65
SFDR (dBc)
70
-60
65
-70
60
-75
55
-80
50
65
60
55
50
25
50
75
100
45
40
0
125
25
50
75
100
125
0
25
50
75
100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ADC SIGNAL-TO-NOISE-RATIO
vs. ANALOG INPUT POWER
ADC SIGNAL-TO-NOISE-RATIO AND
DISTORTION vs. ANALOG INPUT POWER
ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
50
fIN = 5.50885
50
QA
30
IA
fIN = 5.50885
-35
-40
QA
40
SINAD (dB)
40
-30
-45
30
THD (dB)
fIN = 5.50885
125
MAX5864 toc12
60
MAX5864 toc10
60
MAX5864 toc11
0
SNR (dB)
MAX5864
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
IA
-50
-55
-60
20
20
10
10
0
0
-65
-70
-75
-24
-20
-16
-12
-8
ANALOG INPUT POWER (dBFS)
8
-4
0
-80
-24
-20
-16
-12
-8
ANALOG INPUT POWER (dBFS)
-4
0
-24
-20
-16
-12
-8
ANALOG INPUT POWER (dBFS)
_______________________________________________________________________________________
-4
0
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
ADC SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE
70
QA
49
50
MAX5864 toc14
fIN = 5.50885
75
50
MAX5864 toc13
80
ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. SAMPLING RATE
MAX5864 toc15
ADC SPURIOUS -FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
QA
49
55
50
SINAD (dB)
60
SNR (dB)
SFDR (dBc)
65
IA
48
47
IA
48
47
45
40
46
46
35
fIN = 5.50885
30
-20
-16
-12
-8
-4
45
7
0
10
13
16
19
22
7
13
16
19
SAMPLING RATE (MHz)
SAMPLING RATE (MHz)
ADC TOTAL HARMONIC DISTORTION
vs. SAMPLING RATE
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
ADC SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
fIN = 5.50885
-55
fIN = 5.50885
75
22
50
fIN = 5.50885
MAX5864 toc18
80
MAX5864 toc16
-50
IA
49
SFDR (dBc)
-65
SNR (dB)
70
-60
65
65
-75
55
10
13
16
19
QA
46
50
7
48
47
-70
-80
45
7
22
10
13
16
19
22
35
40
45
50
55
60
65
SAMPLING RATE (MHz)
SAMPLING RATE (MHz)
CLOCK DUTY CYCLE (%)
ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. CLOCK DUTY CYCLE
ADC TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLE
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLE
-60
49
80
-62
-64
75
-66
QA
47
70
SFDR (dBc)
THD (dB)
48
-68
-70
-72
-76
55
-78
45
35
40
45
50
55
CLOCK DUTY CYCLE (%)
60
65
65
60
-74
46
MAX5864 toc21
IA
MAX5864 toc20
fIN = 5.50885
MAX5864 toc19
50
SINAD (dB)
10
ANALOG INPUT POWER (dBFS)
MAX5864 toc17
-24
THD (dB)
fIN = 5.50885
45
fIN = 5.050885
fIN = 5.050885
-80
50
35
40
45
50
55
CLOCK DUTY CYCLE (%)
60
65
35
40
45
50
55
60
65
CLOCK DUTY CYCLE (%)
_______________________________________________________________________________________
9
MAX5864
Typical Operating Characteristics (continued)
(VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz 50% duty cycle, ADC
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN =
CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz 50% duty cycle, ADC
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN =
CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
-0.4
-0.5
-0.6
-0.7
-0.8
Rx MODE ONLY
10
SUPPLY CURRENT (mA)
1.5
GAIN ERROR (% FS)
-0.3
12
MAX5864 toc23
-0.2
OFFSET ERROR (% FS)
2.0
MAX5864 toc22
0
-0.1
SUPPLY CURRENT
vs. SAMPLING RATE
ADC GAIN ERROR vs. TEMPERATURE
QA
1.0
0.5
IA
0
MAX5864 toc24
ADC OFFSET ERROR vs. TEMPERATURE
8
IVDD
6
4
IOVDD
2
-0.5
-0.9
-15
10
35
60
85
-15
10
35
7
85
60
10
13
16
19
22
TEMPERATURE (°C)
SAMPLING RATE (MHz)
DAC SPRURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
DAC SPRURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
DAC SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT POWER
85
fOUT = 2MHz
70
80
75
60
SFDR (dBc)
SFDR (dBc)
80
75
50
70
70
40
65
65
30
20
60
60
10
13
16
19
2
4
6
8
-30
10
-20
-15
-10
OUTPUT POWER (dBFS)
DAC CHANNEL-ID SPECTRAL PLOT
DAC CHANNEL-QD SPECTRAL PLOT
DAC CHANNEL-ID TWO TONE
SPECTRAL PLOT
MAX5864 toc28
0
-20
AMPLITUDE (dB)
-30
-40
-50
-60
0
-30
-40
-50
-60
-20
-30
-60
-70
-80
-80
-80
-90
-90
-90
-100
-100
-100
5
7
9
11
1
3
5
7
FREQUENCY (MHz)
9
11
f2
-50
-70
FREQUENCY (MHz)
f1
-40
-70
3
f1 = 2.0MHz, f2 = 2.2MHz, -7dBFS
-10
AMPLITUDE (dB)
-20
fQD = 2.2MHz
-10
0
-5
FREQUENCY (MHz)
fID = 2.2MHz
1
-25
SAMPLING RATE (MHz)
0
-10
0
22
MAX5864 toc29
7
MAX5864 toc27
85
80
MAX5864 toc26
90
MAX5864 toc25
fOUT = fCLK/10
SFDR (dBc)
-40
TEMPERATURE (°C)
90
10
0
-1.0
-40
MAX5864 toc30
-1.0
AMPLITUDE (dB)
MAX5864
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
1
3
5
7
FREQUENCY (MHz)
______________________________________________________________________________________
9
11
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
f1
f2
-40
-40
-50
-60
-70
Xcrv MODE
14
SUPPLY CURRENT (mA)
-30
OUTPUT POWER (dBm)
AMPLITUDE (dB)
-20
fCLK = 15.36Msps
WCDMA
-30
16
MAX5864 toc32
f1 = 2.0MHz, f2 = 2.2MHz, -7dBFS
-10
SUPPLY CURRENT vs. SAMPLING RATE
DAC ACPR SPECTRAL PLOT
-20
MAX5864 toc31
0
-50
-60
-70
-80
-90
-80
-100
-90
-110
-100
3
5
7
9
12
IVDD
10
8
6
4
IOVDD
2
0
-120
1
11
7
CENTER = 4MHz, SPAN = 7MHz
10
FREQUENCY (MHz)
ADC DIFFERENTIAL NONLINEARITY
0.4
0.3
0.8
0.6
0.1
0.2
0
-0.1
DNL (LSB)
0.4
0.1
DNL (LSB)
0.2
0
-0.1
0
-0.2
-0.2
-0.2
-0.4
-0.3
-0.3
-0.6
-0.4
-0.4
-0.8
-0.5
-0.5
128 160 192 224 256
-1.0
0
32
64
96
128 160 192 224 256
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
0.4
0.3
MAX5864 toc38
0.520
MAX5864 toc37
0.5
DIGITAL INPUT CODE
REFERENCE OUTPUT VOLTAGE
vs.TEMPERATURE
DAC DIFFERENTIAL NONLINEARITY
0.515
VREFP - VREFN (V)
0.2
DNL (LSB)
22
DAC INTEGRAL NONLINEARITY
0.2
96
19
1.0
MAX5864 toc35
0.3
INL (LSB)
0.5
MAX5864 toc34
0.4
64
16
MAX5864 toc36
ADC INTEGRAL NONLINEARITY
32
13
SAMPLING RATE (MHz)
0.5
0
MAX5864 toc33
DAC CHANNEL-QD TWO-TONE
SPECTRAL PLOT
0.1
0
-0.1
0.510
-0.2
0.505
-0.3
-0.4
-0.5
0.500
0
128 256 384 512 640 768 896 1024
DIGITAL INPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (°C)
______________________________________________________________________________________
11
MAX5864
Typical Operating Characteristics (continued)
(VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz 50% duty cycle, ADC
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN =
CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
MAX5864
Pin Description
PIN
NAME
1
REFP
2, 8, 43
VDD
Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a
0.1µF capacitor.
3
IA+
Channel IA Positive Analog Input. For single-ended operation, connect signal source to IA+.
4
IA-
Channel IA Negative Analog Input. For single-ended operation, connect IA- to COM.
5, 7, 12, 37,
42
GND
Analog Ground. Connect all pins to GND ground plane.
6
CLK
Conversion Clock Input. Clock signal for both ADCs and DACs.
9
QA-
Channel QA Negative Analog Input. For single-ended operation, connect QA- to COM.
10
QA+
Channel QA Positive Analog Input. For single-ended operation, connect signal source to QA+.
11, 33, 39
VDD
Analog Supply Voltage. Connect to VDD power plane as close to the device as possible.
13–16, 19–22
DA0–DA7
17
OGND
Output Driver Ground
18
OVDD
Output Driver Power Supply. Supply range from +1.8V to VDD to accommodate most logic levels.
Bypass OVDD to OGND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.
23–32
DD0–DD9
34
DIN
35
SCLK
36
CS
38
N.C.
40, 41
QD+, QD-
DAC Channel-QD Differential Voltage Output
44, 45
ID-, ID+
DAC Channel-ID Differential Voltage Output
46
REFIN
Reference Input. Connect to VDD for internal reference.
47
COM
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.
48
REFN
Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.33µF
capacitor.
—
EP
12
FUNCTION
Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible.
ADC Tri-State Digital Output Bits. DA7 is the most significant bit (MSB), and DA0 is the least
significant bit (LSB).
DAC Digital Input Bits. DD9 is the MSB, and DD0 is the LSB.
3-Wire Serial Interface Data Input. Data is latched on the rising edge of the SCLK.
3-Wire Serial Interface Clock Input
3-Wire Serial Interface Chip Select Input. Apply logic low enables the serial interface.
No Connection
Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
______________________________________________________________________________________
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
The MAX5864 integrates dual 8-bit receive ADCs and
dual 10-bit transmit DACs while providing ultra-low
power and highest dynamic performance at a conversion rate of 22Msps. The ADCs’ analog input amplifiers
are fully differential and accept 1VP-P full-scale signals.
The DACs’ analog outputs are fully differential with
±400mV full-scale output range at 1.4V common mode.
The MAX5864 includes a 3-wire serial interface to control operating modes and power management. The serial interface is SPI™ and MICROWIRE™ compatible.
The MAX5864 serial interface selects shutdown, idle,
standby, transmit, receive, and transceiver modes.
INTERNAL
BIAS
COM
S5a
S2a
C1a
S3a
S4a
IA+
OUT
C2a
S4c
S1
OUT
IAS4b
C1b
C2b
S3b
S5b
S2b
INTERNAL
BIAS
COM
INTERNAL
BIAS
COM
HOLD
CLK
HOLD
TRACK
TRACK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
S5a
S2a
C1a
S3a
S4a
QA+
OUT
C2a
S4c
S1
MAX5864
OUT
QAS4b
C1b
C2b
S3b
S2b
INTERNAL
BIAS
S5b
COM
Figure 1. MAX5864 ADC Internal T/H Circuits
SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
______________________________________________________________________________________
13
MAX5864
The MAX5864 can operate in FDD or TDD applications
by configuring the device for transmit, receive, or transceiver modes through a 3-wire serial interface. In TDD
mode, the digital bus for receive ADC and transmit
DAC can be shared to reduce the digital I/O to a single
10-bit parallel multiplexed bus. In FDD mode, the
MAX5864 digital I/O can be configured for an 18-bit,
parallel multiplexed bus to match the dual 8-bit ADC
and dual 10-bit DAC.
The MAX5864 features an internal precision 1.024V
bandgap reference is stable over the entire power-supply
and temperature ranges.
Detailed Description
MAX5864
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
Dual 8-Bit ADC
The ADC uses a seven-stage, fully differential,
pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples
taken at the inputs move progressively through the
pipeline stages every half-clock cycle. Including the
delay through the output latch, the total clock-cycle
latency is 5 clock cycles for channel IA and 5.5 clock
cycles for channel QA. The ADC’s full-scale analog
input range is ±VREF with a common-mode input range
of VDD/2 ±0.2V. VREF is the difference between VREFP
and VREFN. See the Reference Configurations section
for details.
Input Track-and-Hold (T/H) Circuits
Figure 1 displays a simplified functional diagram of the
ADC’s input T/H circuitry. In track mode, switches S1,
S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully
differential circuits sample the input signals onto the
two capacitors (C2a and C2b) through switches S4a
and S4b. S2a and S2b set the common mode for the
amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and
S5b are then opened before switches S3a and S3b
connect capacitors C1a and C1b to the output of the
amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b.
The amplifiers charge capacitors C1a and C1b to the
same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and
isolate the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the ADC to
track and sample/hold analog inputs of high frequencies (> Nyquist). Both ADC inputs (IA+, QA+, IA-, and
QA-) can be driven either differentially or single ended.
Match the impedance of IA+ and IA-, as well as QA+
and QA-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance.
ADC Digital Output Data (DA0–DA7)
DA0–DA7 are the ADCs’ digital logic outputs. The logic
level is set by OVDD from 1.8V to VDD. The digital output coding is offset binary (Table 1, Figure 2). The
capacitive load on digital outputs DA0–DA7 should be
kept as low as possible (<15pF) to avoid large digital
currents feeding back into the analog portion of the
MAX5864 and degrading its dynamic performance.
Buffers on the digital outputs isolate them from heavy
capacitive loads. Adding 100Ω resistors in series with
the digital outputs close to the MAX5864 helps improve
ADC performance. Refer to the MAX5865 EV kit
schematic for an example of the digital outputs driving
a digital buffer through 100Ω series resistors.
Table 1. Output Codes vs. Input Voltage
DIFFERENTIAL
INPUT VOLTAGE
14
DIFFERENTIAL INPUT
(LSB)
OFFSET BINARY
(DA7–DA0)
OUTPUT DECIMAL
CODE
VREF ×
127
128
127
(+full scale - 1LSB)
1111 1111
255
VREF ×
126
128
126
(+full scale - 2LSB)
1111 1110
254
VREF ×
1
128
+1
1000 0001
129
VREF ×
0
128
0
(bipolar zero)
1000 0000
128
− VREF ×
1
128
-1
0111 1111
127
− VREF ×
127
128
-127
(-full scale + 1LSB)
0000 0001
1
− VREF ×
128
128
-128
(-full scale)
0000 0000
0
______________________________________________________________________________________
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
1 LSB =
2 x VREF
256
VREF = VREFP - VREFN
VREF
VREF
1000 0001
1000 0000
0111 1111
(COM)
VREF
OFFSET BINARY OUTPUT CODE (LSB)
VREF
1111 1111
1111 1110
1111 1101
0000 0011
0000 0010
0000 0001
0000 0000
-128 -127 -126 -125
-1
0
+1
+125 +126 +127 +128
(COM)
INPUT VOLTAGE (LSB)
puts. CHI data is updated on the rising edge and CHQ
data is updated on the falling edge of the CLK.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for CHI and 5.5
clock cycles for CHQ.
Dual 10-Bit DAC
The 10-bit DACs are capable of operating with clock
speeds up to 22MHz. The DAC’s digital inputs,
DD0–DD9, are multiplexed on a single 10-bit bus. The
voltage reference determines the data converters’ fullscale output voltages. See the Reference Configurations
section for setting reference voltage. The DACs utilize a
current-array technique with a 1mA (with 1.024V reference) full-scale output current driving a 400Ω internal
resistor resulting in a ±400mV full-scale differential output voltage. The MAX5864 is designed for differential
output only and is not intended for single-ended application. The analog outputs are biased at 1.4V common
mode and designed to drive a differential input stage
with input impedance ≥70kΩ. This simplifies the analog
interface between RF quadrature upconverters and the
MAX5864. RF upconverters require a 1.3V to 1.5V common-mode bias. The internal DC common-mode bias
eliminates discrete level setting resistors and code-generated level-shifting while preserving the full dynamic
range of each transmit DAC. Table 2 shows the output
voltage vs. input code.
Figure 2. ADC Transfer Function
5 CLOCK-CYCLE LATENCY (CHI), 5.5 CLOCK-CYCLE LATENCY (CHQ)
CHI
CHQ
CLK
tDOQ
DA0–DA7
tDOI
D0Q
D1I
D1Q
D2I
D2Q
D3I
D3Q
D4I
D4Q
D5I
D5Q
D6I
D6Q
Figure 3. ADC System Timing Diagram
______________________________________________________________________________________
15
MAX5864
ADC System Timing Requirements
Figure 3 shows the relationship between the clock, analog inputs, and the resulting output data. Channel IA
(CHI) and channel QA (CHQ) are simultaneously sampled on the rising edge of the clock signal (CLK) and
the resulting data is multiplexed at the DA0–DA7 out-
MAX5864
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC =
1.024V, External Reference Mode VREFDAC = VREFIN)
DIFFERENTIAL OUTPUT VOLTAGE
OFFSET BINARY
(DD0–DD9)
INPUT DECIMAL CODE
VREFDAC 1023
×
2.56
1023
11 1111 1111
1023
VREFDAC 1021
×
2.56
1023
11 1111 1110
1022
VREFDAC
3
×
2.56
1023
10 0000 0001
513
1
VREFDAC
×
2.56
1023
10 0000 0000
512
− VREFDAC
2.56
− VREFDAC
2.56
− VREFDAC
2.56
×
1
1023
01 1111 1111
511
×
1021
1023
00 0000 0001
1
×
1023
1023
00 0000 0000
0
CLK
tDHQ
tDSQ
DD0–DD9
Q: N-2
I: N-1
Q: N-1
tDSI
Q: N
I: N
I: N+1
tDHI
ID
N-2
N-1
N
QD
N-2
N-1
N
Figure 4. DAC System Timing Diagram
DAC Timing
Figure 4 shows the relationship between the clock, input
data, and analog outputs. Data for the I channel (ID) is
latched on the falling edge of the clock signal, and Qchannel (QD) data is latched on the rising edge of the
clock signal. Both I and Q outputs are simultaneously
updated on the next rising edge of the clock signal.
16
3-Wire Serial Interface and
Operation Modes
The 3-wire serial interface controls the MAX5864 operation modes. Upon power-up, the MAX5864 must be
programmed to operate in the desired mode. Use the
3-wire serial interface to program the device for the shutdown, idle, standby, Rx, Tx, or Xcvr mode. An 8-bit data
register sets the operation modes as shown in Table 3.
The serial interface remains active in all six modes.
______________________________________________________________________________________
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
MAX5864
Table 3. MAX5864 Operation Modes
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
Shutdown
Device shutdown. REF is off, ADCs are
off, and the ADC bus is tri-stated; DACs
are off and the DAC input bus must be
set to zero or OVDD.
X
X
X
X
X
0
0
0
Idle
REF and CLK are on, ADCs are off,
and the ADC bus is tri-stated; DACs
are off and the DAC input bus must be
set to zero or OVDD.
X
X
X
X
X
0
0
1
Rx
REF is on, ADCs are on; DACs are off,
and the DAC input bus must be set to
zero or OVDD.
X
X
X
X
X
0
1
0
Tx
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are on.
X
X
X
X
X
0
1
1
REF is on, ADCs and DACs are on.
X
X
X
X
X
1
0
0
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are off and the
DAC input bus must be set to zero or
OVDD.
X
X
X
X
X
1
0
1
FUNCTION
Xcvr
Standby
DESCRIPTION
X = Don’t care.
Shutdown mode offers the most dramatic power savings
by shutting down all the analog sections of the MAX5864
and placing the ADCs’ digital outputs in tri-state mode.
When the ADCs’ outputs transition from tri-state to on,
the last converted word is placed on the digital outputs.
The DACs’ digital bus inputs must be zero or OVDD
because the bus is not internally pulled up. The DACs’
previously stored data is lost when coming out of shutdown mode. The wake-up time from shutdown mode is
dominated by the time required to charge the capacitors
at REFP, REFN, and COM. In internal reference mode
and buffered external reference mode, the wake-up time
is typically 40µs to enter Xcvr moed, 20µs to enter Rx
mode, and 40µs to enter Tx mode.
In idle mode, the reference and clock distribution circuits
are powered, but all other functions are off. The ADCs’
outputs are forced to tri-state. The DACs’ digital bus
inputs must be zero or OVDD, because the bus is not
internally pulled up. The wake-up time from the idle mode
is 10µs required for the ADCs and DACs to be fully operational. When the ADCs’ outputs transition from tri-state to
on, the last converted word is placed on the digital outputs. In the idle mode, the supply current is lowered if the
clock input is set to zero or OVDD; however, the wake-up
time extends to 40µs.
In standby mode, only the ADCs’ reference is powered;
the rest of the device’s functions are off. The pipeline
ADCs are off and DA0 to DA7 are in tri-state mode. The
DACs’ digital bus inputs must be zero or OV DD
because the bus is not internally pulled up. The wakeup time from standby mode to the Xcvr mode is dominated by the 40µs required to activate the pipeline
ADCs and DACs. When the ADC outputs transition from
tri-state to active, the last converted word is placed on
the digital outputs.
The serial digital interface is a standard 3-wire connection compatible with SPI/QSPI™/MICROWIRE/DSP
interfaces. Set CS low to enable the serial data loading
at DIN. Following CS high-to-low transition, data is shifted synchronously, MSB first, on the rising edge of the
serial clock (SCLK). After 8 bits are loaded into the serial input register, data is transferred to the latch. CS
must transition high for a minimum of 80ns before the
next write sequence. The SCLK can idle either high or
low between transitions. Figure 5 shows the detailed
timing diagram of the 3-wire serial interface.
QSPI is a trademark of Motorola, Inc.
______________________________________________________________________________________
17
MAX5864
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
tCSW
CS
tCSS
tCP
tCH
tCL
tCS
SCLK
tDS
DIN
LSB
MSB
tDH
Figure 5. 3-Wire Serial Interface Timing Diagram
CS
SCLK
DIN
8-BIT DATA
tWAKE, SD, ST_ (Rx) OR tENABLE, Rx
DAO–DA7
ID/QD
ADC DIGITAL OUTPUT.
SINAD SETTLES WITHIN 1dB
DAC ANALOG OUTPUT. OUTPUT
SETTLES TO 10 LSB ERROR
tWAKE, SD, ST_ (Tx) OR tENABLE, TX
Figure 6. MAX5864 Mode Recovery Timing Diagram
Mode Recovery Timing
Figure 6 shows the mode recovery timing diagram.
TWAKE is the wake-up time when exiting shutdown, idle,
or standby mode and entering into Rx, Tx, or Xcvr
mode. tENABLE is the recovery time when switching
between any Rx, Tx, or Xcvr mode. tWAKE or tENABLE is
the time for the ADC to settle within 1dB of specified
SINAD performance and DAC settling to 10 LSB error.
tWAKE or tENABLE times are measured after the 8-bit
serial command is latched into the MAX5864 by CS
transition high. tENABLE for Xcvr mode is dominated by
the DAC wake-up time. The recovery time is 10µs to
switch between Xcvr, Tx, or Rx modes. The recovery
time is 40µs to switch from shutdown or standby mode
to Xcvr mode.
18
System Clock Input (CLK)
CLK input is shared by both the ADCs and DACs. It
accepts a CMOS-compatible signal level set by OVDD
from 1.8V to VDD. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). Specifically,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide the lowest possible jitter.
Any significant clock jitter limits the SNR performance
of the on-chip ADCs as follows:


1
SNR = 20 × log 

 2 × π × tIN × t AJ 
where fIN represents the analog input frequency and
tAJ is the time of the clock jitter.
______________________________________________________________________________________
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
Reference Configurations
The MAX5864 features an internal precision 1.024V
bandgap reference is stable over the entire power supply and temperature range. The REFIN input provides
two modes of reference operation. The voltage at REFIN
(VREFIN) sets reference operation mode (Table 4).
In internal reference mode, connect REFIN to V DD.
VREF is an internally generated 0.512V. COM, REFP,
and REFN are low-impedance outputs with VCOM =
VDD/2, VREFP = VDD/2 + VREF/2, and VREFN = VDD/2 VREF/2. Bypass REFP, REFN, and COM each with a
0.33µF capacitor. Bypass REFIN to GND with a 0.1µF
capacitor.
In buffered external reference mode, apply 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with VCOM = VDD/2, VREFP
= VDD/2 + VREFIN/4, and VREFN = VDD/2 - VREFIN/4.
Bypass REFP, REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a 0.1µF capacitor. In this mode, the DAC’s full-scale output voltage
and common-mode voltage are proportional to the
external reference. For example, if the V REFIN is
increased by 10% (max), the DACs’ full-scale output
voltage is also increased by 10% or ±440mV, and the
common-mode voltage increases by 10%.
Applications Information
Using Balun Transformer AC-Coupling
An RF transformer (Figure 7) provides an excellent
solution to convert a single-ended signal source to a
fully differential signal for optimum ADC performance.
Connecting the center tap of the transformer to COM
provides a VDD/2 DC level shift to the input. A 1:1 transformer can be used, or a step-up transformer can be
selected to reduce the drive requirements. In general,
the MAX5864 provides better SFDR and THD with fully
differential input signals than single-ended signals,
especially for high-input frequencies. In differential
mode, even-order harmonics are lower as both inputs
(IA+, IA-, QA+, QA-) are balanced, and each of the
ADC inputs only requires half the signal swing compared to single-ended mode. Figure 8 shows an RF
transformer converting the MAX5864 DACs’ differential
analog outputs to single ended.
25Ω
IA+
0.1µF
22pF
VIN
COM
0.33µF
0.1µF
IA25Ω 22pF
MAX5864
25Ω
QA+
Table 4. Reference Modes
VREFIN
REFERENCE MODE
>0.8 x VDD
Internal reference mode. VREF is internally
generated to be 0.512V. Bypass REFP,
REFN, and COM each with a 0.33µF
capacitor.
1.024V ±10%
Buffered external reference mode. An
external 1.024V ±10% reference voltage
is applied to REFIN. VREF is internally
generated to be VREFIN/2. Bypass REFP,
REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a
0.1µF capacitor.
0.1µF
22pF
VIN
0.33µF
0.1µF
QA25Ω 22pF
Figure 7. Balun-Transformer Coupled Single-Ended to
Differential Input Drive for ADCs
______________________________________________________________________________________
19
MAX5864
Clock jitter is especially critical for undersampling
applications. Consider the clock input as an analog
input and route away from any analog input or other
digital signal lines. The MAX5864 clock input operates
with an OVDD/2 voltage threshold and accepts a 50%
±15% duty cycle.
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
MAX5864
Using Op-Amp Coupling
ID+
VOUT
MAX5864
ID-
QD+
VOUT
QD-
Figure 8. Balun-Transformer Coupled Differential to SingleEnded Output Drive for DACs
REFP
1kΩ
VIN
0.1µF
RISO
50Ω
INA+
100Ω
CIN
22pF
1kΩ
COM
REFN
0.1µF
RISO
50Ω
INA-
100Ω
CIN
22pF
REFP
VIN
0.1µF
1kΩ
MAX5864
RISO
50Ω
INB+
100Ω
1kΩ
REFN
CIN
22pF
0.1µF
RISO
50Ω
100Ω
INBCIN
22pF
Drive the MAX5864 ADCs with op amps when a balun
transformer is not available. Figures 9 and 10 show the
ADCs being driven by op amps for AC-coupled singleended, and DC-coupled differential applications.
Amplifiers such as the MAX4354/MAX4454 provide
high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. Figure 10 can
also be used to interface with the DAC differential analog outputs to provide gain or buffering. The DAC differential analog outputs cannot be used in singleended mode because of the internally generated
1.4VDC common-mode level. Also, the DAC analog
outputs are designed to drive a differential input stage
with input impedance ≥70kΩ. If single-ended outputs
are desired, use an amplifier to provide differential to
single-ended conversion and select an amplifier with
proper input common-mode voltage range.
FDD and TDD Modes
The MAX5864 can be used in diverse applications
operating FDD or TDD modes. The MAX5864 operates
in Xcvr mode for FDD applications such as WCDMA3GPP (FDD) and 4G technologies. Also, the MAX5864
can switch between Tx and Rx modes for TDD applications like TD-SCDMA, WCDMA-3GPP (TDD),
IEEE802.11a/b/g, and IEEE802.16.
In FDD mode, the ADC and DAC operate simultaneously. The ADC bus and DAC bus are dedicated and must
be connected in 18-bit parallel (8-bit ADC and 10-bit
DAC) to the digital baseband processor. Select Xcvr
mode through the 3-wire serial interface and use the
conversion clock to latch data. In FDD mode, the
MAX5864 uses 34mW power at fCLK = 15.36MHz. This
is the total power of the ADC and DAC operating simultaneously.
In TDD mode, the ADC and DAC operate independently. The ADC and DAC bus are shared and can be connected together, forming a single 10-bit parallel bus to
the digital baseband processor. Using the 3-wire serial
interface, select between Rx mode to enable the ADC
and Tx mode to enable the DAC. When operating in Rx
mode, the DAC does not transmit because the core is
disabled and in Tx mode, the ADC bus is tri-state. This
eliminates any unwanted spurious emissions and prevents bus contention. In TDD mode, the MAX5864 uses
24.7mW power in Rx mode at fCLK = 15.36MHz, and
the DAC uses 24mW in Tx mode.
Figure 9. Single-Ended Drive for ADCs
20
______________________________________________________________________________________
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
MAX5864
R4
600Ω
R5
600Ω
MAX5864
RISO
22Ω
R1
600Ω
INACIN
5pF
R2
600Ω
R6
600Ω
R7
600Ω
R8
600Ω
R9
600Ω
COM
R3
600Ω
RISO
22Ω
CIN
5pF
R10
600Ω
INA+
R11
600Ω
Figure 10. ADC DC-Coupled Differential Drive
CLK
ADC
MAX2391
QUADRATURE
DEMODULATOR
ADC
T/R
CLK
MAX2395
QUADRATURE
TRANSMITTER
DAC
DIGITAL BASEBAND
PROCESSOR
ADC
OUTPUT
MUX
DAC
INPUT
MUX
DAC
MAX5864
SERIAL BUS
Figure 11. Typical Application Circuit for TDD
______________________________________________________________________________________________________
21
Figure 11 illustrates the MAX5864 working with the
MAX2391 and MAX2395 in TDD mode to provide a
complete radio front-end solution. Because the
MAX5864 DAC has full differential analog outputs with
a common-mode level of 1.4V, it can interface directly
with RF quadrature modulators while eliminating discrete components and amplifiers used for level-shifting
circuits. Also, the DAC’s full dynamic range is preserved because the internally generated commonmode level eliminates code-generated level shifting or
attenuation due to resistor level shifting. The MAX5864
ADC has 1VP-P full-scale range and accepts input common-mode levels of VDD/2 (±200mV). These features
simplify the analog interface between RF quadrature
demodulator and ADC while eliminating discrete gain
amplifiers and level-shifting components.
Grounding, Bypassing, and
Board Layout
The MAX5864 requires high-speed board layout design
techniques. Refer to the MAX5865 EV kit data sheet for
a board layout reference. Locate all bypass capacitors
as close to the device as possible, preferably on the
same side of the board as the device, using surfacemount devices for minimum inductance. Bypass VDD to
GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF capacitor. Bypass OVDD to OGND with a 0.1µF
ceramic capacitor in parallel with a 2.2µF capacitor.
Bypass REFP, REFN, and COM each to GND with a
0.33µF ceramic capacitor. Bypass REFIN to GND with
a 0.1µF capacitor.
Multilayer boards with separated ground and power
planes yield the highest level of signal integrity. Use a
split ground plane arranged to match the physical location of the analog ground (GND) and the digital output
driver ground (OGND) on the device package. Connect
the MAX5864 exposed backside paddle to the GND
plane. Join the two ground planes at a single point
such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location
for this connection can be determined experimentally at
a point along the gap between the two ground planes.
Make this connection with a low-value, surface-mount
resistor (1Ω to 5Ω), a ferrite bead, or a direct short.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy digital system’s ground plane (e.g.,
downstream output buffer or DSP ground plane).
Route high-speed digital signal traces away from sensitive analog traces. Make sure to isolate the analog
input lines to each respective converter to minimize
channel-to-channel crosstalk. Keep all signal lines short
and free of 90° turns.
7
6
ANALOG OUTPUT VALUE
6
ANALOG OUTPUT VALUE
MAX5864
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
5
4
AT STEP
011 (1/2 LSB )
3
2
AT STEP
001 (1/4 LSB )
1
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
4
3
1 LSB
2
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
1
0
0
000
001
010
011
100
101
DIGITAL INPUT CODE
Figure 12a. Integral Nonlinearity
22
1 LSB
5
110
111
000
001
010
011
100
101
DIGITAL INPUT CODE
Figure 12b. Differential Nonlinearity
___________________________________________________________________________________________________
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
ADC Dynamic Parameter Definitions
ADC and DAC Static Parameter Definitions
Aperture Jitter
Figure 13 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static linearity parameters for the device are measured using
the end-point method (DAC Figure 12a).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes (ADC) and a monotonic transfer function
(ADC and DAC) (DAC Figure 12b).
ADC Offset Error
Ideally, the midscale transition occurs at 0.5 LSB above
midscale. The offset error is the amount of deviation
between the measured transition point and the ideal
transition point.
DAC Offset Error
Offset error (Figure 12a) is the difference between the
ideal and actual offset point. The offset point is the output value when the digital input is midscale. This error
affects all codes by the same amount and usually can
be compensated by trimming.
ADC Gain Error
Ideally, the ADC full-scale transition occurs at 1.5 LSB
below full scale. The gain error is the amount of deviation between the measured transition point and the
ideal transition point with the offset error removed.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 13).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error) and results directly
from the ADC’s resolution (N bits):
SNR(max) = 6.02dB x N + 1.76dB (in dB)
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral
components to the Nyquist frequency excluding the
fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
ENOB = (SINAD - 1. 76) / 6.02
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
CLK
ANALOG
INPUT
 (V22 + V32 + V42 + V52 + V62
THD = 20log 
V1

tAD
tAJ
SAMPLED
DATA (T/H)
T/H
)


where V1 is the fundamental amplitude and V2–V6 are
the amplitudes of the 2nd- through 6th-order harmonics.
TRACK
HOLD
TRACK
Figure 13. T/H Aperture Timing
______________________________________________________________________________________
23
MAX5864
Dynamic Parameter Definitions
VDD
N.C.
GND
37
38
39
40
GND
QDQD+
41
42
43
ID+
IDVDD
45
44
COM
REFIN
46
REFN
REFP
VDD
1
36
2
35
IA+
IAGND
CLK
3
34
4
33
5
32
DIN
VDD
DD9
31
DD8
GND
VDD
QAQA+
VDD
7
30
8
29
DD7
DD6
MAX5864
CS
SCLK
24
DD5
DD4
DD3
DD2
DA7
DD0
DD1
DA5
DA6
23
25
22
26
12
21
11
20
27
19
28
18
9
10
17
GND
6
16
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as the fullpower bandwidth frequency.
TOP VIEW
15
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by 3dB. Note
that the T/H performance is usually the limiting factor
for the small-signal input bandwidth.
Pin Configuration
47
Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
and gain error when the power supply is changed
±5%.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion
component up to the Nyquist frequency excluding DC.
48
3rd-Order Intermodulation (IM3)
IM3 is the power of the worst third-order intermodulation product relative to the input power of either input
tone when two tones, f 1 and f 2 , are present at the
inputs. The 3rd-order intermodulation products are (2 x
f1 ±f2), (2 ✕ f2 ±f1). The individual input tone levels are
at -7dBFS.
 (V22 + V32 + ... + Vn2 ) 

THD = 20log 


V1


where V1 is the fundamental amplitude and V2 through
Vn are the amplitudes of the 2nd through nth harmonic
up to the Nyquist frequency.
14
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation products are (f1 ±f2), (2 ✕ f1), (2 ✕ f2), (2 ✕ f1 ±f2), (2 ✕ f2
±f1). The individual input tone levels are at -7dBFS.
Total Harmonic Distortion
THD is the ratio of the RMS sum of the output harmonics
up to the Nyquist frequency divided by the fundamental:
13
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious
component, excluding DC offset.
DAC Dynamic Parameter Definitions
DA1
DA2
DA3
OGND
OVDD
DA4
Third Harmonic Distortion (HD3)
HD3 is defined as the ratio of the RMS value of the third
harmonic component to the fundamental input signal.
DA0
MAX5864
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
QFN
Chip Information
TRANSISTOR COUNT: 16,765
PROCESS: CMOS
24
______________________________________________________________________________________
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End
32, 44, 48L QFN .EPS
D2
D
CL
D/2
b
D2/2
k
E/2
E2/2
E
CL
(NE-1) X e
E2
k
L
DETAIL A
e
(ND-1) X e
CL
CL
L
L
e
A1
A2
e
A
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0144
REV.
1
B
______________________________________________________________________________________
2
25
MAX5864
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX5864
Ultra-Low-Power, High-DynamicPerformance, 22Msps Analog Front End
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED.
TOTAL NUMBER OF LEADS ARE 44.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0144
REV.
B
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.