19-2094; Rev 0; 7/01 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs Applications High Resolution Imaging I/Q Channel Digitization Multchannel IF Undersampling Instrumentation ♦ Single +3V Operation ♦ Excellent Dynamic Performance: 59dB SNR at fIN = 20MHz 77dB SFDR at fIN = 20MHz ♦ Low Power: 65mA (Normal Operation) 2.8mA (Sleep Mode) 1µA (Shutdown Mode) ♦ 0.02dB Gain and 0.25° Phase Matching (typ) ♦ Wide ±1VP-P Differential Analog Input Voltage Range ♦ 400MHz -3dB Input Bandwidth ♦ On-Chip +2.048V Precision Bandgap Reference ♦ User-Selectable Output Format—Two’s Complement or Offset Binary ♦ 48-Pin TQFP Package with Exposed Pad for Improved Thermal Dissipation ♦ Evaluation Kit Available Ordering Information PART TEMP. RANGE MAX1182ECM PIN-PACKAGE -40°C to +85°C 48 TQFP-EP 37 38 39 40 41 42 43 44 45 46 47 REFN REFP REFIN REFOUT D9A D8A D7A D6A D5A D4A D3A D2A Pin Configuration 48 Pin-compatible higher and lower speed versions of the MAX1182 are also available. Please refer to the MAX1180 datasheet for 105Msps, the MAX1181 datasheet for 80Msps, the MAX1183 datasheet for 40Msps, and the MAX1184 datasheet for 20Msps. In addition to these speed grades, this family includes a 20Msps multiplexed output version (MAX1185), for which digital data is presented time-interleaved on a single, parallel 10-bit output port. Features COM VDD 1 36 2 35 GND INA+ INA- 3 34 4 33 5 32 VDD GND INBINB+ 6 GND VDD CLK 31 MAX1182 7 30 8 29 9 28 10 27 11 26 12 25 D1A D0A OGND OVDD OVDD OGND D0B D1B D2B D3B D4B D5B 24 23 22 21 20 19 18 17 15 16 GND T/B SLEEP PD OE D9B D8B D7B D6B 14 GND VDD VDD 13 Video Application 48 TQFP-EP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1182 General Description The MAX1182 is a +3V, dual 10-bit analog-to-digital converter (ADC) featuring fully-differential wideband track-and-hold (T/H) inputs, driving two pipelined, 9stage ADCs. The MAX1182 is optimized for low-power, high-dynamic performance applications in imaging, instrumentation and digital communication applications. This ADC operates from a single +2.7V to +3.6V supply, consuming only 195mW while delivering a typical signal-to-noise ratio (SNR) of 59dB at an input frequency of 20MHz and a sampling rate of 65Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with single-ended inputs. In addition to low operating power, the MAX1182 features a 2.8mA sleep mode as well as a 1µA power-down mode to conserve power during idle periods. An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of the internal or an externally derived reference, if desired for applications requiring increased accuracy or a different input voltage range. The MAX1182 features parallel, CMOS-compatible three-state outputs. The digital output format is set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of +1.7V to +3.6V for flexible interfacing. The MAX1182 is available in a 7mm x 7mm, 48pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range. MAX1182 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, CLK, COM to GND ..........................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D9A–D0A, D9B–D0B to OGND .............................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 12.5mW/°C above +70°C).......1000mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead temperature (soldering, 10s) ..................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 65MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 10 Bits Integral Nonlinearity INL fIN = 7.47MHz ±0.6 ±1.9 Differential Nonlinearity DNL fIN = 7.47MHz, no missing codes guaranteed ±0.4 ±1.0 LSB Offset Error < ±1 ±1.7 % FS Gain Error 0 ±2 % FS LSB ANALOG INPUT Differential Input Voltage Range VDIFF Common-Mode Input Voltage Range VCM Input Resistance RIN Input Capacitance CIN Differential or single-ended inputs Switched capacitor load ±1.0 V VDD/2 ± 0.5 V 33 kΩ 5 pF 5 Clock Cycles CONVERSION RATE Maximum Clock Frequency fCLK 65 Data Latency MHz DYNAMIC CHARACTERISTICS (fCLK = 65MHz, 4096-point FFT) Signal-to-Noise Ratio SNR fINA or B = 7.47MHz, TA = +25°C 56.8 59.5 fINA or B = 20MHz, TA = +25°C 56.5 59 fINA or B = 39.9MHz (Note 1) Signal-to-Noise and Distortion (up to 5th harmonic) fINA or B = 7.47MHz, TA = +25°C SINAD fINA or B = 20MHz, TA = +25°C 56.5 59 56 58.5 fINA or B = 39.9MHz (Note 1) Spurious-Free Dynamic Range SFDR 2 dB 58.5 fINA or B = 7.47MHz, TA = +25°C 65 76 fINA or B = 20MHz, TA = +25°C 65 77 fINA or B = 39.9MHz, (Note 1) dB 59 75 _______________________________________________________________________________________ dBc Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = +3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 65MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Third-Harmonic Distortion SYMBOL HD3 Intermodulation Distortion (first 5 odd-order IMDs) IMD Total Harmonic Distortion (first 5 harmonics) THD MIN FPBW Aperture Delay tAD Aperture Jitter tAJ Overdrive Recovery Time TYP -83 fINA or B = 20MHz -82 fINA or B = 39.9MHz (Note 1) -77 fINA or B = 19.13042MHz at -6.5dB FS MAX fINA or B = 20MHz, TA = +25°C UNITS dBc -75 fINA or B = 21.2886MHz at -6.5dB FS (Note 2) fINA or B = 7.47MHz, TA = +25°C Small-Signal Bandwidth Full-Power Bandwidth CONDITIONS fINA or B = 7.47MHz dBc -75.5 -64 -76 -63 dBc fINA or B = 39.9MHz, (Note 1) -74 Input at -20dB FS, differential inputs 500 MHz Input at -0.5dB FS, differential inputs 400 MHz 1 ns 2 psRMS 2 ns ±1 % For 1.5 x full-scale input Differential Gain ±0.25 degrees 0.2 LSBRMS REFOUT 2.048 ±3% V TCREF 60 ppm/°C 1.25 mV/mA Differential Phase Output Noise INA+ = INA- = INB+ = INB- = COM INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation BUFFERED EXTERNAL REFERENCE (VREFIN = +2.048V) REFIN Input Voltage VREFIN 2.048 V Positive Reference Output Voltage VREFP 2.012 V Negative Reference Output Voltage VREFN 0.988 V Differential Reference Output Voltage Range ∆VREF REFIN Resistance RREFIN ∆VREF = VREFP - VREFN 0.98 1.024 >50 1.07 V MΩ _______________________________________________________________________________________ 3 MAX1182 ELECTRICAL CHARACTERISTICS (continued) MAX1182 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = +3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 65MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL CONDITIONS MIN TYP MAX UNITS ISOURCE >5 mA ISINK 250 µA ISOURCE 250 µA ISINK >5 mA UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance RREFP, RREFN Measured between REFP and COM, and REFN and COM Differential Reference Input Voltage ∆VREF ∆VREF = VREFP – VREFN COM Input Voltage 4 kΩ 1.024 ±10% V VCOM VDD/2 ± 10% V REFP Input Voltage VREFP VCOM + ∆VREF /2 V REFN Input Voltage VREFN VCOM ∆VREF /2 V DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) Input High Threshold VIH Input Low Threshold VIL Input Hysteresis Input Leakage Input Capacitance CLK 0.8 x VDD PD, OE, SLEEP, T/B 0.8 x OVDD CLK 0.2 x VDD PD, OE, SLEEP, T/B 0.2 x OVDD VHYST 0.1 VIH = OVDD or VDD (CLK) ±5 IIL VIL = 0 ±5 CIN 5 ISINK = 200µA Output Voltage High VOH ISOURCE = 200µA Three-State Leakage Current ILEAK OE = OVDD Three-State Output Capacitance COUT OE = OVDD V V IIH DIGITAL OUTPUTS (D9A–D0A, D9B–D0B) Output Voltage Low VOL 4 V µA pF 0.2 V ±10 µA OVDD - 0.2 V 5 _______________________________________________________________________________________ pF Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = +3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 65MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Analog Supply Voltage Range VDD 2.7 3.0 3.6 V Output Supply Voltage Range OVDD 1.7 2.5 3.6 V Operating, fINA or B = 20MHz at -0.5dB FS 65 80 Sleep mode 2.8 Analog Supply Current Output Supply Current IVDD IOVDD Shutdown, clock idle, PD = OE = OVDD 1 Operating, CL = 15pF, fINA or B = 20MHz at -0.5dB FS 11 Sleep mode 100 Shutdown, clock idle, PD = OE = OVDD Power Dissipation PDISS 10 Operating, fINA or B = 20MHz at -0.5dB FS 195 240 Sleep mode 8.4 PSRR 3 µA mA 2 Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection Ratio 15 mA 45 µA mW µW Offset ±0.2 mV/V Gain ±0.1 %/V TIMING CHARACTERISTICS CLK Rise to Output Data Valid tDO Figure 3 (Note 3) 5 8 ns Output Enable Time tENABLE Figure 4 10 Output Disable Time tDISABLE Figure 4 1.5 ns ns CLK Pulse Width High tCH Figure 3, clock period: 15.4ns 7.7 ± 1.5 ns CLK Pulse Width Low tCL Figure 3, clock period: 15.4ns 7.7 ± 1.5 ns Wake-Up Time tWAKE Wakeup from Sleep mode (Note 4) 0.42 Wakeup from Shutdown (Note 4) 1.5 µs CHANNEL-TO-CHANNEL MATCHING Crosstalk fINA or B = 20MHz at -0.5dB FS -70 Gain Matching fINA or B = 20MHz at -0.5dB FS 0.02 Phase Matching fINA or B = 20MHz at -0.5dB FS 0.25 dB ±0.2 dB degrees Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB or better, if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH, VIL. Parameter guaranteed by design. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Note 5: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL. _______________________________________________________________________________________ 5 MAX1182 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = +3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 65MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) -50 -60 -30 0 -40 -50 -60 -20 -30 -40 -50 -60 -70 -70 -70 -80 -80 -80 -90 -90 -90 -100 -100 -100 5 10 15 20 25 30 10 15 20 25 30 35 0 -10 -20 0 -40 -50 -60 -20 -30 35 -50 -60 -70 -80 -90 -90 -90 -100 -100 -100 20 25 30 35 0 5 TWO-TONE IMD PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT) fIN1 = 19.13042MHz fIN2 = 21.28864MHz fCLK = 65.00057MHz AIN = -6.5dB FS TWO-TONE ENVELOPE = -0.47dB FS 61 MAX1182 toc07 0 fIN1 10 15 20 25 30 35 0 5 10 15 20 25 30 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY DIFFERENTIAL INPUT CONFIGURATION 60 CHB 62 DIFFERENTIAL INPUT CONFIGURATION CHB 35 60 -50 3rd ORDER IMD 2nd ORDER IMD SNR (dB) 59 fIN2 CHA SINAD (dB) 15 MAX1182 toc08 10 ANALOG INPUT FREQUENCY (MHz) CHB -40 -80 5 fINA = 37.31661MHz fINB = 46.99687MHz fCLK = 65.00057MHz AINB = -0.49dB FS -10 AMPLITUDE (dB) -30 CHA -80 -60 30 MAX1182 toc06 fINA = 37.31661MHz fINB = 46.99687MHz fCLK = 65.00057MHz AINB = -0.52dB FS -70 -40 25 MAX1182 toc09 0 MAX1182 toc05 CHB -70 -30 20 FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) -60 -20 15 FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) -50 -10 10 FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) -40 0 5 ANALOG INPUT FREQUENCY (MHz) AMPLITUDE (dB) -30 5 ANALOG INPUT FREQUENCY (MHz) fINA = 20.08257MHz fINB = 25.09727MHz fCLK = 65.00057MHz AINB = -0.52dB FS -20 0 ANALOG INPUT FREQUENCY (MHz) 0 -10 35 CHA fINA = 20.08257MHz fINB = 25.09727MHz fCLK = 65.00057MHz AINB = -0.52dB FS -10 AMPLITUDE (dB) -40 0 AMPLITUDE (dB) -20 AMPLITUDE (dB) -30 MAX1182 toc04 AMPLITUDE (dB) -20 fINA = 6.0065MHz fINB = 7.51410MHz fCLK = 65.00057MHz AINB = -0.56dB FS CHB -10 FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1182 toc02 fINA = 6.0065MHz fINB = 7.51410MHz fCLK = 65.00057MHz AINA = -0.55dB FS CHA 0 MAX1182 toc01 0 -10 FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1182 toc03 FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) AMPLITUDE (dB) MAX1182 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs 58 CHA 58 57 -70 -80 56 56 -90 0 5 10 15 20 25 30 ANALOG INPUT FREQUENCY (MHz) 6 54 55 -100 35 1 10 ANALOG INPUT FREQUENCY (MHz) 100 1 10 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 100 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs DIFFERENTIAL INPUT CONFIGURATION -68 83 CHA CHA GAIN (dB) SFDR (dB) -71 -77 75 CHB 10 -2 -6 -8 63 1 0 -4 67 -80 1 100 10 1 100 10 100 1000 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 20.085279MHz) SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 20.085279MHz) 4 60 2 65 60 -2 -4 -6 -8 1 10 100 55 SINAD (dB) SNR (dB) 55 0 50 50 45 45 40 40 35 -20 1000 MAX1182 toc15 AIN = 100mVP-P MAX1182 toc14 65 MAX1182 toc13 6 -16 -12 -8 -4 35 -20 0 -16 -12 -8 -4 ANALOG INPUT FREQUENCY (MHz) INPUT POWER (dB FS) INPUT POWER (dB FS) TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 20.085279MHz) SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 20.085279MHz) INTEGRAL NONLINEARITY (BEST-ENDPOINT FIT) SFDR (dB) -65 76 -70 0.5 72 INL (LSB) -60 1.0 0 MAX1182 toc18 80 MAX1182 toc16 -55 MAX1182 toc17 GAIN (dB) 4 2 71 THD (dB) 6 79 CHB THD (dB) DIFFERENTIAL INPUT CONFIGURATION MAX1182 toc11 87 MAX1182 toc10 -65 -74 FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY MAX1182 toc12 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY 68 0 -0.5 -75 64 -80 60 -20 -16 -12 -8 INPUT POWER (dB FS) -4 0 -1.0 -20 -16 -12 -8 INPUT POWER (dB FS) -4 0 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE _______________________________________________________________________________________ 7 MAX1182 Typical Operating Characteristics (continued) (VDD = +3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 65MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 65MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) CHB GAIN ERROR (% FS) 0.1 0 -0.1 -0.2 0 -0.5 -1.0 -1.5 CHA CHB 0.05 0 -0.05 CHA -2.0 -0.3 -0.10 -2.5 -0.4 -0.5 -3.0 128 256 384 512 640 768 896 1024 -0.15 -40 -15 10 35 60 85 -40 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs. TEMPERATURE ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY 85 MAX1182 toc22 80 0.30 OE = PD = OVDD 0.24 60 50 IVDD (µA) 75 IVDD (mA) 70 65 40 0.18 0.06 0 45 2.85 3.00 3.15 3.30 3.45 3.60 -40 VDD (V) -15 10 35 TEMPERATURE (°C) 60 3.00 3.15 3.30 3.45 VDD (V) 2.040 VREFOUT (V) SFDR 70 THD 60 SINAD MAX1182 toc26 2.045 MAX1182 toc25 SFDR, SNR, THD, SINAD (dB) fIN = 25.097265MHz 50 2.85 INTERNAL REFERENCE VOLTAGE vs. ANALOG POWER VOLTAGE 90 SNR 2.70 85 SFDR, SNR, THD, SINAD vs. CLOCK DUTY CYCLE 80 2.035 2.030 2.025 2.020 40 30 35 40 45 50 55 60 CLOCK DUTY CYCLE (%) 85 0.12 55 2.70 -15 DIGITAL OUTPUT CODE MAX1182 toc24 0 8 0.10 MAX1182 toc23 DNL (LSB) 0.2 MAX1182 toc21 0.5 OFFSET ERROR (% FS) 0.3 0.15 MAX1182 toc20 1.0 MAX1182 toc19 0.4 OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = +2.048V) GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = +2.048V) DIFFERENTIAL NONLINEARITY 0.5 IVDD (mA) MAX1182 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs 65 70 2.70 2.85 3.00 3.15 3.30 VDD (V) _______________________________________________________________________________________ 3.45 3.60 3.60 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE OUTPUT NOISE HISTOGRAM (DC INPUT) 2.05 140000 MAX1182 toc28 160000 MAX1182 toc27 2.06 129421 2.04 COUNTS VREFOUT (V) 120000 2.03 100000 80000 60000 2.02 40000 2.01 20000 0 2.00 -40 -15 10 35 60 85 TEMPERATURE (°C) 0 926 N-2 N-1 N 725 0 N+1 N+2 DIGITAL OUTPUT CODE Pin Description PIN NAME 1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥0.1µF capacitor. FUNCTION 2, 6, 11, 14, 15 VDD Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. 3, 7, 10, 13, 16 GND Analog Ground 4 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+. 5 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM. 8 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM. 9 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+. 12 CLK Converter Clock Input 17 T/B T/B selects the ADC digital output format. High: Two’s complement. Low: Straight offset binary. 18 SLEEP 19 PD Power-Down Input. High: Power-down mode Low: Normal operation 20 OE Output Enable Input. High: Digital outputs disabled Low: Digital outputs enabled Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation. _______________________________________________________________________________________ 9 MAX1182 Typical Operating Characteristics (continued) (VDD = +3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 65MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1182 Pin Description (continued) 10 PIN NAME 21 D9B Three-State Digital Output, Bit 9 (MSB), Channel B FUNCTION 22 D8B Three-State Digital Output, Bit 8, Channel B 23 D7B Three-State Digital Output, Bit 7, Channel B 24 D6B Three-State Digital Output, Bit 6, Channel B 25 D5B Three-State Digital Output, Bit 5, Channel B 26 D4B Three-State Digital Output, Bit 4, Channel B 27 D3B Three-State Digital Output, Bit 3, Channel B 28 D2B Three-State Digital Output, Bit 2, Channel B 29 D1B Three-State Digital Output, Bit 1, Channel B 30 D0B Three-State Digital Output, Bit 0 (LSB), Channel B 31, 34 OGND Output Driver Ground 32, 33 OVDD Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with 0.1µF. 35 D0A Three-State Digital Output, Bit 0 (LSB), Channel A 36 D1A Three-State Digital Output, Bit 1, Channel A 37 D2A Three-State Digital Output, Bit 2, Channel A 38 D3A Three-State Digital Output, Bit 3, Channel A 39 D4A Three-State Digital Output, Bit 4, Channel A 40 D5A Three-State Digital Output, Bit 5, Channel A 41 D6A Three-State Digital Output, Bit 6, Channel A 42 D7A Three-State Digital Output, Bit 7, Channel A 43 D8A Three-State Digital Output, Bit 8, Channel A 44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor divider. 45 REFOUT 46 REFIN Reference Input. VREFIN = 2 ✕ (VREFP - VREFN). Bypass to GND with a >1nF capacitor. 47 REFP Positive Reference Input/Output. Conversion range is ± (VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. 48 REFN Negative Reference Input/Output. Conversion range is ± (VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. ______________________________________________________________________________________ Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs The MAX1182 uses a 9-stage, fully-differential pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Counting the delay through the output latch, the clockcycle latency is five clock cycles. 1.5-bit (2-comparator) flash ADCs convert the heldinput voltages into a digital code. The digital-to-analog converters (DACs) convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes. Input Track-and-Hold (T/H) Circuits Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track and VIN Σ T/H FLASH ADC x2 VIN VOUT Σ T/H FLASH ADC DAC 1.5 BITS x2 VOUT DAC 1.5 BITS 2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 8 2-BIT FLASH ADC STAGE 9 STAGE 1 DIGITAL CORRECTION LOGIC T/H VINA 10 D9A–D0A STAGE 2 STAGE 8 STAGE 9 DIGITAL CORRECTION LOGIC T/H VINB 10 D9B–D0B VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED) VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED) Figure 1. Pipelined Architecture—Stage Blocks ______________________________________________________________________________________ 11 MAX1182 hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a and S5b are closed. The fully-differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b, connect capacitors C1a and C1b to the output of the amplifier, and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1182 to trackand-sample/hold analog inputs of high frequencies (> Nyquist). The ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single-ended. Match the impedance of INA+ and INA- as well as INB+ and INB- and set the common-mode voltage to mid-supply (VDD/2) for optimum performance. Detailed Description MAX1182 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs INTERNAL BIAS COM S5a S2a C1a S3a S4a INA+ OUT C2a S4c S1 OUT INAS4b C2b C1b S3b S5b S2b INTERNAL BIAS COM HOLD INTERNAL BIAS TRACK COM CLK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS S5a S2a C1a S3a S4a INB+ OUT C2a S4c S1 OUT INBS4b MAX1182 C2b C1b S3b S2b INTERNAL BIAS S5b COM Figure 2. MAX1182 T/H Amplifiers 12 ______________________________________________________________________________________ Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs ered as an analog input and routed away from any analog input or other digital signal lines. The full-scale range of the MAX1182 is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. The MAX1182 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the Electrical Characteristics. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered low-impedance outputs. The MAX1182 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10kΩ) or resistor divider, if an application requires a reduced full-scale range. For stability and noise filtering purposes bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN become outputs. REFOUT may be left open or connected to REFIN through a >10kΩ resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high impedance and may be driven through separate external reference sources. Clock Input (CLK) The MAX1182’s CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: SNRdB = 20 ✕ log10 (1 / [2π x fIN x tAJ]), where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be consid- System Timing Requirements Figure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1182 samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 4 also determines the relationship between the input clock parameters and the valid output data on channels A and B. Digital Output Data, Output Data Format Selection (T/B), Output Enable (/OE) All digital outputs, D0A–D9A (Channel A) and D0B–D9B (Channel B), are TTL/CMOS logic-compatible. There is a 5-clock-cycle latency between any particular sample and its corresponding output data. The output coding can be chosen to be either straight offset binary or two’s complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two’s complement output coding. The capacitive load on the digital outputs D0A–D9A and D0B–D9B should be kept as low as possible (<15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1182, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1182 small-series resistors (e.g., 100Ω) maybe added to the digital output paths, close to the MAX1182. Figure 4 displays the timing relationship between output enable and data output valid as well as power down/wake-up and data output valid. Power-Down (PD) and Sleep (SLEEP) Modes The MAX1182 offers two power-save modes—sleep and full power-down mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 2.8mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power down. Pulling OE high forces the digital outputs into a high impedance state. ______________________________________________________________________________________ 13 MAX1182 Analog Inputs and Reference Configurations MAX1182 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs 5 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 ANALOG INPUT CLOCK INPUT tD0 tCH tCL DATA OUTPUT D9A–D0A N-6 N-5 N-4 N-3 N-2 N-1 N N+1 DATA OUTPUT D9B–D0B N-6 N-5 N-4 N-3 N-2 N-1 N N+1 Figure 3. System Timing Diagram amplifiers. The user may select the RISO and CIN values to optimize the filter performance, to suit a particular application. For the application in Figure 5, a RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor. OE tENABLE OUTPUT D9A–D0A HIGH-Z OUTPUT D9B–D0B HIGH-Z tDISABLE VALID DATA HIGH-Z Using Transformer Coupling Applications Information A RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1182 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the overall distortion. Figure 5 depicts a typical application circuit containing two single-ended to differential converters. The internal reference provides a V DD/2 output voltage for level shifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per ADC suppresses some of the wideband noise associated with high-speed operational amplifiers, follows the In general, the MAX1182 provides better SFDR and THD with fully-differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode. VALID DATA HIGH-Z Figure 4. Output Timing Diagram 14 ______________________________________________________________________________________ Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1182 Table 1. MAX1182 Output Codes For Differential Inputs STRAIGHT OFFSET BINARY T/B = 0 DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT VREF x 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111 VREF x 1/512 + 1 LSB 10 0000 0001 00 0000 0001 0 Bipolar Zero 10 0000 0000 00 0000 0000 - VREF x 1/512 - 1 LSB 01 1111 1111 11 1111 1111 -VREF x 511/512 - FULL SCALE + 1 LSB 00 0000 0001 10 0000 0001 - FULL SCALE 00 0000 0000 10 0000 0000 -VREF x 512/512 *VREF = VREFP - VREFN Single-Ended AC-Coupled Input Signal Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high-speed, high-bandwidth, low noise, and low distortion to maintain the integrity of the input signal. Typical QAM Demodulation Application The most frequently used modulation technique for digital communications applications is probably the Quadrature Amplitude Modulation (QAM). Typically found in spread-spectrum based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent up-conversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90 degree phase-shifted with respect to the inphase component. At the receiver, the QAM signal is divided down into it’s I and Q components, essentially representing the modulation process reversed. Figure 8 displays the demodulation process performed in the analog domain, using the dual matched +3V, 10-bit ADC MAX1182 and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1182, the mixed-down signal components may be filtered by matched analog filters, such as Nyquist or pulse-shaping filters which remove any unwanted images from the mixing process, thereby enhancing the overall signalto-noise (SNR) performance and minimizing inter-symbol interference. TWO’S COMPLEMENT T/B = 1 Grounding, Bypassing, and Board Layout The MAX1182 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADCs package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channelto-channel crosstalk. Keep all signal lines short and free of 90 degree turns. ______________________________________________________________________________________ 15 MAX1182 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs +5V 0.1µF LOWPASS FILTER INA+ MAX4108 RIS0 50Ω 0.1µF 300Ω CIN 22pF 0.1µF -5V 600Ω 600Ω 300Ω COM 0.1µF +5V +5V 0.1µF 600Ω INPUT 0.1µF LOWPASS FILTER MAX4108 300Ω -5V 0.1µF INA- MAX4108 RIS0 50Ω 300Ω CIN 22pF 0.1µF -5V 300Ω 300Ω +5V 600Ω MAX1182 0.1µF LOWPASS FILTER INB+ MAX4108 RIS0 50Ω 0.1µF 300Ω CIN 22pF 0.1µF -5V 600Ω 600Ω 300Ω 0.1µF +5V +5V 0.1µF 600Ω INPUT 0.1µF LOWPASS FILTER MAX4108 300Ω -5V 0.1µF INB- MAX4108 RIS0 50Ω 300Ω CIN 22pF 0.1µF -5V 300Ω 300Ω 600Ω Figure 5. Typical Application for Single-Ended to Differential Conversion 16 ______________________________________________________________________________________ Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1182 25Ω INA+ 22pF 0.1µF 1 VIN N.C. T1 6 5 2 3 4 COM 2.2µF 0.1µF MINICIRCUITS TT1–6 25Ω INA22pF MAX1182 25Ω INB+ 22pF 0.1µF 1 VIN N.C. T1 6 2 5 3 4 2.2µF 0.1µF MINICIRCUITS TT1–6 25Ω INB22pF Figure 6. Transformer-Coupled Input Drive Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1182 are measured using the best straight-line fit method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Dynamic Parameter Definitions Aperture Jitter Figure 9 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 9). ______________________________________________________________________________________ 17 MAX1182 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs REFP VIN 0.1µF 1kΩ RISO 50Ω INA+ MAX4108 100Ω CIN 22pF 1kΩ COM REFN 0.1µF RISO 50Ω INA- 100Ω CIN 22pF REFP VIN 0.1µF MAX1182 1kΩ RISO 50Ω INB+ MAX4108 100Ω CIN 22pF 1kΩ REFN 0.1µF RISO 50Ω INB- 100Ω CIN 22pF Figure 7: Using an Op Amp for Single-Ended, AC-Coupled Input Drive Signal-to-Noise Ratio (SNR) Signal-to-Noise Plus Distortion (SINAD) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N-Bits): SNRdB[max] = 6.02dB x N + 1.76dB SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. In reality, there are other noise sources besides quantization noise e.g. thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. 18 Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB is computed from: ENOB = SINADdB − 1.76dB 6.02dB ______________________________________________________________________________________ Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs INA+ INA0° 90° MAX1182 DSP POST PROCESSING INB+ INBDOWNCONVERTER ÷8 Figure 8. Typical QAM Application, Using the MAX1182 Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: CLK V2 2 + V3 2 + V4 2 + V5 2 THD = 20 × log10 V1 ANALOG INPUT tAD where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. tAJ SAMPLED DATA (T/H) Spurious-Free Dynamic Range (SFDR) T/H TRACK HOLD TRACK SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) Figure 9. T/H Aperture Timing The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale and their envelope is at -0.5dB full scale. Chip Information TRANSISTOR COUNT: 10,811 PROCESS: CMOS ______________________________________________________________________________________ 19 MAX1182 MAX2451 Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1182 Functional Diagram VDD OGND OVDD GND INA+ PIPELINE ADC T/H 10 DEC OUTPUT DRIVERS 10 D9A–D0A INA- CONTROL CLK OE INB+ T/H PIPELINE ADC 10 DEC OUTPUT DRIVERS 10 D9B–D0B INB- REFERENCE MAX1182 REFOUT REFN COM REFP 20 REFIN ______________________________________________________________________________________ T/B PD SLEEP Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs 48L,TQFP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1182 Package Information This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.