19-2794; Rev 1; 9/03 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC Applications ♦ Ultra-Low Power 57mW (Normal Operation: 45Msps) 0.3µW (Shutdown Mode) ♦ Excellent Dynamic Performance 48.5dB/48.3dB SNR at fIN = 5.5MHz/100MHz 70dBc/68dBc SFDR at fIN = 5.5MHz/100MHz ♦ 2.7V to 3.6V Single Analog Supply ♦ 1.8V to 3.6V TTL/CMOS-Compatible Digital Outputs ♦ Fully Differential or Single-Ended Analog Inputs ♦ Internal/External Reference Option ♦ Multiplexed CMOS-Compatible Tri-State Outputs ♦ 28-Pin Thin QFN Package ♦ Evaluation Kit Available (Order MAX1193EVKIT) Ordering Information PART MAX1193ETI-T TEMP RANGE PIN-PACKAGE -40°C to +85°C 28 Thin QFN-EP* (5mm x 5mm) *EP = Exposed paddle. Pin Configuration VDD REFP REFN COM REFIN PD0 PD1 27 26 25 24 23 22 TOP VIEW 28 For higher sampling frequency applications, refer to the MAX1195–MAX1198 dual 8-bit ADCs. Pin-compatible versions of the MAX1193 are also available. Refer to the MAX1191 data sheet for 7.5Msps, and the MAX1192 data sheet for 22Msps. Features INA- 1 21 D0 Ultrasound and Medical Imaging INA+ 2 20 D1 IQ Baseband Sampling GND 3 19 D2 CLK 4 18 D3 GND 5 17 A/B INB+ 6 16 D4 15 D5 Battery-Powered Portable Instruments Low-Power Video MAX1193 WLAN, Mobile DSL, WLL Receiver 9 10 11 12 13 14 GND OGND OVDD D7 D6 VDD VDD 7 8 INB- EXPOSED PADDLE 5mm x 5mm THIN QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1193 General Description The MAX1193 is an ultra-low-power, dual, 8-bit, 45Msps analog-to-digital converter (ADC). The device features two fully differential wideband track-and-hold (T/H) inputs. These inputs have a 440MHz bandwidth and accept fully differential or single-ended signals. The MAX1193 delivers a typical signal-to-noise and distortion (SINAD) of 48.5dB at an input frequency of 5.5MHz and a sampling rate of 45Msps while consuming only 57mW. This ADC operates from a 2.7V to 3.6V analog power supply. A separate 1.8V to 3.6V supply powers the digital output driver. In addition to ultra-low operating power, the MAX1193 features three powerdown modes to conserve power during idle periods. Excellent dynamic performance, ultra-low power, and small size make the MAX1193 ideal for applications in imaging, instrumentation, and digital communications. An internal 1.024V precision bandgap reference sets the full-scale range of the ADC to ±0.512V. A flexible reference structure allows the MAX1193 to use its internal reference or accept an externally applied reference for applications requiring increased accuracy. The MAX1193 features parallel, multiplexed, CMOScompatible tri-state outputs. The digital output format is offset binary. A separate digital power input accepts a voltage from 1.8V to 3.6V for flexible interfacing to different logic levels. The MAX1193 is available in a 5mm × 5mm, 28-pin thin QFN package, and is specified for the extended industrial (-40°C to +85°C) temperature range. MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND .................-0.3V to (VDD + 0.3V) CLK, REFIN, REFP, REFN, COM to GND ...-0.3V to (VDD + 0.3V) PD0, PD1 to OGND .................................-0.3V to (OVDD + 0.3V) Digital Outputs to OGND .........................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 28-Pin Thin QFN (derated 20.8mW/°C above +70°C) ..1667mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 45MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.16 ±1.00 LSB ±0.15 ±1.00 LSB DC ACCURACY Resolution 8 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error Gain Error No missing codes over temperature Bits ≥ +25°C ±4 < +25°C ±6 Excludes REFP - REFN error ±2 DC Gain Matching ±0.01 Gain Temperature Coefficient ±30 Power-Supply Rejection ±0.2 %FS %FS dB ppm/°C Offset (VDD ±5%) ±0.2 Gain (VDD ±5%) ±0.05 Differential or single-ended inputs ±0.512 V VDD / 2 V 120 kΩ 5 pF LSB ANALOG INPUT Differential Input Voltage Range VDIFF Common-Mode Input Voltage Range VCOM Input Resistance RIN Input Capacitance CIN Switched capacitor load CONVERSION RATE Maximum Clock Frequency fCLK Data Latency 45 MHz Channel A 5.0 Channel B 5.5 Clock cycles DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) Signal-to-Noise Ratio (Note 2) Signal-to-Noise and Distortion (Note 2) fIN = 3.75MHz SNR SINAD fIN = 5.5MHz 47 48.5 fIN = 22.5MHz 48.4 fIN = 3.75MHz 48.5 fIN = 5.5MHz fIN = 22.5MHz 2 48.5 47 48.5 48.4 _______________________________________________________________________________________ dB dB Ultra-Low-Power, 45Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 45MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Spurious-Free Dynamic Range (Note 2) Third-Harmonic Distortion (Note 2) SYMBOL CONDITIONS MIN fIN = 3.75MHz SFDR HD3 TYP MAX UNITS 70.7 fIN = 5.5MHz 60.0 70.0 fIN = 22.5MHz 71.5 fIN = 3.75MHz -79.6 fIN = 5.5MHz -79.0 fIN = 22.5MHz 76.1 dBc dBc Intermodulation Distortion IMD fIN1 = 1MHz at -7dB FS, fIN2 = 1.01MHz at -7dB FS -66 dBc Third-Order Intermodulation IM3 fIN1 = 1MHz at -7dB FS, fIN2 = 1.01MHz at -7dB FS -70 dBc Total Harmonic Distortion (Note 2) THD fIN = 3.75MHz -70.8 fIN = 5.5MHz -70.0 fIN = 22.5MHz -70.1 -57.0 dBc Small-Signal Bandwidth SSBW Input at -20dB FS 440 MHz Full-Power Bandwidth FPBW Input at -0.5dB FS 440 MHz Aperture Delay tAD 1.5 ns Aperture Jitter tAJ 2 psRMS 2 ns 1.5 × full-scale input Overdrive Recovery Time INTERNAL REFERENCE (REFIN = VDD; VREFP, VREFN, and VCOM are generated internally) REFP Output Voltage VREFP - VCOM 0.256 V REFN Output Voltage VREFN - VCOM -0.256 V COM Output Voltage VCOM Differential Reference Output VREF Differential Reference Output Temperature Coefficient Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current VDD / 2 - 0.15 VREFP - VREFN VDD / 2 VDD / 2 + 0.15 V 0.512 V VREFTC ±30 ppm/°C ISOURCE 2 mA ISINK 2 mA BUFFERED EXTERNAL REFERENCE (VREFIN = 1.024V, VREFP, VREFN, and VCOM are generated internally) REFIN Input Voltage VREFIN COM Output Voltage VCOM Differential Reference Output VREF Maximum REFP/REFN/COM Source Current ISOURCE 1.024 VDD / 2 - 0.15 VREFP - VREFN VDD / 2 V VDD / 2 + 0.15 V 0.512 V 2 mA _______________________________________________________________________________________ 3 MAX1193 ELECTRICAL CHARACTERISTICS (continued) MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 45MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Maximum REFP/REFN/COM Sink Current SYMBOL CONDITIONS MIN ISINK TYP MAX UNITS 2 mA REFIN Input Resistance >500 kΩ REFIN Input Current -0.7 µA UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFP, VREFN, and VCOM are applied externally) REFP Input Voltage VREFP - VCOM REFN Input Voltage VREFN - VCOM 0.256 V -0.256 V VDD / 2 V 0.512 V Measured between REFP and COM 4 kΩ Measured between REFN and COM 4 kΩ COM Input Voltage VCOM Differential Reference Input Voltage VREF VREFP - VREFN REFP Input Resistance RREFP REFN Input Resistance RREFN DIGITAL INPUTS (CLK, PD0, PD1) Input High Threshold Input Low Threshold Input Hysteresis CLK 0.7 x VDD PD0, PD1 0.7 x OVDD VIH V CLK 0.3 x VDD PD0, PD1 0.3 x OVDD VIL VHYST Digital Input Leakage Current DIIN Digital Input Capacitance DCIN 0.1 V V CLK at GND or VDD ±5 PD0 and PD1 at OGND or OVDD ±5 5 µA pF DIGITAL OUTPUTS (D7–D0, A/B) Output Voltage Low VOL ISINK = 200µA Output Voltage High VOH ISOURCE = 200µA Tri-State Leakage Current ILEAK Tri-State Output Capacitance COUT 0.2 x OVDD 0.8 x OVDD V V ±5 5 µA pF POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage 4 VDD 2.7 OVDD 1.8 3.0 _______________________________________________________________________________________ 3.6 V VDD V Ultra-Low-Power, 45Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 45MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Analog Supply Current Digital Output Supply Current (Note 3) SYMBOL IDD IODD TYP MAX Normal operating mode, fIN = 5.5MHz at -0.5dB FS, CLK input from GND to VDD CONDITIONS MIN 19 22.5 Idle mode (tri-state), fIN = 5.5MHz at -0.5dB FS, CLK input from GND to VDD 19 Standby mode, CLK input from GND to VDD 8.5 Shutdown mode, CLK = GND or VDD, PD0 = PD1 = OGND 0.1 Normal operating mode, fIN = 5.5MHz at -0.5dB FS, CL ≈ 10pF 5 UNITS mA 5.0 µA mA Idle mode (tri-state), DC input, CLK = GND or VDD, PD0 = OVDD, PD1 = OGND 0.1 Standby mode, DC input, CLK = GND or VDD, PD0 = OGND, PD1 = OVDD 0.1 Shutdown mode, CLK = GND or VDD, PD0 = PD1 = OGND 0.1 5.0 5.0 µA TIMING CHARACTERISTICS CLK Rise to CHA Output Data Valid tDOA 50% of CLK to 50% of data), Figure 5 (Note 4) 1 6 8.5 ns CLK Fall to CHB Output Data Valid tDOB 50% of CLK to 50% of data, Figure 5 (Note 4) 1 6 8.5 ns CLK Rise/Fall to A/B Rise/Fall Time tDA/B 50% of CLK to 50% of A/B, Figure 5 (Note 4) 1 6 8.5 ns PD1 Rise to Output Enable tEN PD0 = OVDD PD1 Fall to Output Disable tDIS PD0 = OVDD CLK Duty Cycle CLK Duty-Cycle Variation 5 ns 5 ns 50 % ±10 % Wake-Up Time from Shutdown Mode tWAKE, SD (Note 5) 20 µs Wake-Up Time from Standby Mode tWAKE, ST (Note 5) 2.6 µs 2 ns -75 dB Digital Output Rise/Fall Time 20% to 80% INTERCHANNEL CHARACTERISTICS fIN,X = 11MHz at -0.5dB FS, fIN,Y = 0.3MHz at -0.5dB FS (Note 6) Crosstalk Rejection Amplitude Matching fIN = 11MHz at -0.5dB FS (Note 7) ±0.05 dB Phase Matching fIN = 11MHz at -0.5dB FS (Note 7) ±0.2 Degrees _______________________________________________________________________________________ 5 MAX1193 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 45MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA=+25°C.) (Note 1) Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dB FS referenced to the amplitude of the digital output. SNR and THD are calculated using HD2 through HD6. Note 3: The power consumption of the output driver is proportional to the load capacitance (CL). Note 4: Guaranteed by design and characterization. Not production tested. Note 5: SINAD settles to within 0.5dB of its typical value. Note 6: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as power ratio of the first and second channel FFT test tone bins. Note 7: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and phase of the fundamental bin on the calculated FFT. Typical Operating Characteristics (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 45.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) AMPLITUDE (dB) -40 fINB HD3 HD2 -60 0 -20 -40 HD3 -50 HD2 fINA -60 -40 -70 -80 -80 -90 10 15 25 20 5 10 15 25 20 0 ANALOG INPUT FREQUENCY (MHz) -30 -40 HD2 -50 fINA HD3 -60 15 0 -20 fIN2 -30 20 fIN1 -40 -50 -60 -70 -70 -80 -80 -90 fCLK = 45.005678MHz fIN1 = 1.8MHz fIN2 = 2.3MHz AIN = 7dB FS -10 AMPLITUDE (dB) AMPLITUDE (dB) -20 10 TWO-TONE IMD PLOT (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) MAX1193 toc04 fCLK = 45.005678MHz fINA = 21.005678MHz fINB = 12.531448MHz AINA = AINB = -0.5dB FS 5 ANALOG INPUT FREQUENCY (MHz) FFT PLOT CHANNEL B (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) 0 fINB -90 0 ANALOG INPUT FREQUENCY (MHz) -10 HD2 -60 -80 5 HD3 -50 -70 0 -90 0 5 10 15 20 ANALOG INPUT FREQUENCY (MHz) 6 -30 -70 -90 fCLK = 45.005678MHz fINA = 21.005678MHz fINB = 12.531448MHz AINA = AINB = -0.5dB FS -10 -30 MAX1193 toc03 -10 -20 -30 -50 fCLK = 45.005678MHz fINA = 12.531448MHz fINB = 21.005678MHz AINA = AINB = -0.5dB FS AMPLITUDE (dB) -20 fCLK = 45.005678MHz fINA = 12.531448MHz fINB = 21.005678MHz AINA = AINB = -0.5dB FS FFT PLOT CHANNEL A (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) MAX1193 toc02 -10 0 MAX1193 toc01 0 FFT PLOT CHANNEL B (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) MAX1193 toc05 FFT PLOT CHANNEL A (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) AMPLITUDE (dB) MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC 25 0 5 10 15 20 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 25 25 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 45.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY CHANNEL A 48.5 48.0 CHANNEL B 47.5 48.5 48.0 CHANNEL B 47.5 47.0 47.0 46.5 46.5 46.0 46.0 25 50 75 100 125 0 25 50 75 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY 85 MAX1193 toc08 -45 -50 80 -55 125 MAX1193 toc09 0 CHANNEL B 75 CHANNEL A -60 SFDR (dBc) THD (dBc) CHANNEL A 49.0 SINAD (dB) SNR (dB) 49.0 49.5 MAX1193 toc07 49.5 50.0 MAX1193 toc06 50.0 SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY -65 -70 70 65 CHANNEL A 60 CHANNEL B -75 55 -80 50 -85 45 0 25 50 75 100 ANALOG INPUT FREQUENCY (MHz) 125 0 25 50 75 100 125 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX1193 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 45.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER fIN = 11.531606MHz 50 fIN = 11.531606MHz 50 40 SINAD (dB) 30 30 20 20 10 10 0 0 -30 -25 -20 -15 -10 -5 0 -30 -20 0 -10 ANALOG INPUT POWER (dB FS) ANALOG INPUT POWER (dB FS) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER 80 MAX1193 toc12 -30 fIN = 11.531606MHz fIN = 11.531606MHz 70 SFDR (dBc) -40 -50 -60 -70 MAX1193 toc13 SNR (dB) 40 60 50 40 -80 30 -30 -25 -20 -15 -10 -5 ANALOG INPUT POWER (dB FS) 8 MAX1193 toc11 60 MAX1193 toc10 60 THD (dBc) MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC 0 -30 -25 -20 -15 -10 -5 ANALOG INPUT POWER (dB FS) _______________________________________________________________________________________ 0 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 45.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE PLUS DISTORTION vs. SAMPLING RATE SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE fIN = 11.531606MHz 49 SINAD (dB) 49 48 47 48 47 46 46 45 45 10 20 30 40 0 50 10 20 30 40 fCLK (MHz) fCLK (MHz) TOTAL HARMONIC DISTORTION vs. SAMPLING RATE SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE 80 MAX1193 toc16 -50 fIN = 11.531606MHz -55 fIN = 11.531606MHz 75 70 SFDR (dBc) -60 50 MAX1193 toc17 0 THD (dBc) MAX1193 toc15 fIN = 11.531606MHz SNR (dB) 50 MAX1193 toc14 50 -65 65 -70 60 -75 55 -80 50 0 10 20 30 fCLK (MHz) 40 50 0 10 20 30 40 50 fCLK (MHz) _______________________________________________________________________________________ 9 MAX1193 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 45.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE 50 fIN = 11.531606MHz 49 SINAD (dB) 49 48 47 46 48 47 46 45 45 40 42 44 46 48 50 52 54 56 58 60 45 50 55 CLOCK DUTY CYCLE (%) TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE -64 fIN = 11.531606MHz 78 76 -66 60 MAX1193 toc21 80 MAX1193 toc20 fIN = 11.531606MHz -62 40 CLOCK DUTY CYCLE (%) -60 SFDR (dBc) 74 -68 -70 -72 72 70 68 -74 66 -76 64 -78 62 -80 60 40 45 50 55 CLOCK DUTY CYCLE (%) 10 MAX1193 toc19 fIN = 11.531606MHz SNR (dB) SIGNAL-TO-NOISE PLUS DISTORTION vs. CLOCK DUTY CYCLE MAX1193 toc18 50 THD (dBc) MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC 60 40 45 50 55 CLOCK DUTY CYCLE (%) ______________________________________________________________________________________ 60 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 45.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY 0.3 0.2 0.1 0.1 DNL (LSB) 0.2 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 0 32 64 96 MAX1193 toc23 0.4 128 160 192 224 256 0 32 64 96 128 160 192 224 256 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE OFFSET ERROR vs. TEMPERATURE GAIN ERROR vs. TEMPERATURE -0.60 VREFIN = 1.024V -0.65 0.30 MAX1193 toc24 INL (LSB) 0.3 VREFIN = 1.024V 0.25 MAX1193 toc25 0.4 0.20 CHANNEL B GAIN ERROR (% FS) OFFSET ERROR (% FS) 0.5 MAX1193 toc22 0.5 -0.70 CHANNEL A CHANNEL B 0.15 0.10 CHANNEL A 0.05 -0.75 0 -0.80 -0.10 -0.05 -15 10 35 60 85 -40 -15 TEMPERATURE (°C) INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY 0 -2 FULL-POWER BANDWIDTH -0.5dB FS -4 85 0.5130 MAX1193 toc27 VDD = VREFIN 0.5125 60 REFERENCE VOLTAGE vs. TEMPERATURE 0.5120 VDD = VREFIN 0.5125 VREFP - VREFN (V) GAIN (dB) 2 0.5130 VREFP - VREFN (V) SMALL-SIGNAL BANDWIDTH -20dB FS 4 35 REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1193 toc26 6 10 TEMPERATURE (°C) 0.5115 0.5110 MAX1193 toc28 -40 0.5120 0.5115 0.5110 -6 0.5105 -8 -10 1 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 0.5105 0.5100 0.5100 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VDD (V) -40 -15 10 35 60 85 TEMPERATURE (°C) ______________________________________________________________________________________ 11 MAX1193 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 45.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SAMPLING RATE SUPPLY CURRENT vs. INPUT FREQUENCY 5 21.5 4 21.0 ANALOG SUPPLY CURRENT 3 20.5 2 20.0 MAX1193 toc30 22.0 DIGITAL SUPPLY CURRENT fIN = 11.531606MHz 20 SUPPLY CURRENT (mA) 6 25 22.5 ANALOG SUPPLY CURRENT (mA) MAX1193 toc29 7 DIGITAL SUPPLY CURRENT (mA) MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC A 15 B 10 C 5 19.5 1 0 0 19.0 0 5 10 15 20 0 25 10 20 30 40 50 fCLK (MHz) fIN (MHz) A: ANALOG SUPPLY CURRENT (IDD) - INTERNAL AND BUFFERED EXTERNAL REFERENCE MODES B: ANALOG SUPPLY CURRENT (IDD) - UNBUFFERED EXTERNAL REFERENCE MODE C: DIGITAL SUPPLY CURRENT (IODD) - ALL REFERENCE MODES Pin Description 12 PIN NAME 1 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM. FUNCTION 2 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+. 3, 5, 10 GND Analog Ground. Connect all GND pins together. 4 CLK Converter Clock Input 6 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+. 7 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM. 8, 9, 28 VDD Converter Power Input. Connect to a 2.7V to 3.6V power supply. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 11 OGND Output Driver Ground 12 OVDD Output Driver Power Input. Connect to a 1.8V to VDD power supply. Bypass OVDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 13 D7 Tri-State Digital Output. D7 is the most significant bit (MSB). 14 D6 Tri-State Digital Output 15 D5 Tri-State Digital Output 16 D4 Tri-State Digital Output 17 A/B Channel Data Indicator. This digital output indicates channel A data (A/B = 1) or channel B data (A/B = 0) is present on the output. 18 D3 Tri-State Digital Output 19 D2 Tri-State Digital Output 20 D1 Tri-State Digital Output 21 D0 Tri-State Digital Output. D0 is the least significant bit (LSB). 22 PD1 Power-Down Digital Input 1. See Table 3. ______________________________________________________________________________________ Ultra-Low-Power, 45Msps, Dual 8-Bit ADC PIN NAME 23 PD0 FUNCTION 24 REFIN Reference Input. Internally pulled up to VDD. 25 COM Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor. 26 REFN Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.33µF capacitor. 27 REFP Positive Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFP to GND with a 0.33µF capacitor. — EP Power-Down Digital Input 0. See Table 3. Exposed Paddle. Internally connected to pin 3. Externally connect EP to GND. Detailed Description ∑ x2 DAC 1.5 BITS INA+ STAGE 1 T/H STAGE 2 STAGE 7 INA- DIGITAL ERROR CORRECTION / D0–D7 Figure 1. Pipeline Architecture—Stage Blocks INA+ T/H INA- REFIN REFP PIPELINE ADC A / DEC REFERENCE SYSTEM AND BIAS CIRCUITS COM REFN VDD GND MAX1193 POWER CONTROL PD0 PD1 OVDD D0–D7 MULTIPLEXER OUTPUT DRIVERS A/B OGND INB+ T/H INB- PIPELINE ADC B / DEC / FLASH ADC / T/H The MAX1193 uses a seven-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel A and 5.5 clock cycles for channel B. At each stage, flash ADCs convert the held input voltages into a digital code. The following digital-to-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the originally held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all stages. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX1193 functional diagram. / + TIMING CLK Figure 2. MAX1193 Functional Diagram ______________________________________________________________________________________ 13 MAX1193 Pin Description (continued) MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC INTERNAL BIAS COM S5a S2a C1a S3a S4a INA+ OUT C2a S4c S1 OUT INAS4b C2b C1b S3b S5b S2b INTERNAL BIAS COM HOLD INTERNAL BIAS TRACK COM CLK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS S5a S2a C1a S3a S4a INB+ OUT C2a S4c S1 MAX1193 OUT INBS4b C2b C1b S3b S2b INTERNAL BIAS S5b COM Figure 3. Internal T/H Circuits Input Track-and-Hold (T/H) Circuits Figure 3 displays a simplified functional diagram of the input T/H circuits. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the ampli14 fier input, and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same ______________________________________________________________________________________ Ultra-Low-Power, 45Msps, Dual 8-Bit ADC VREFIN REFERENCE MODE >0.8 x VDD Internal reference mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. 1.024V ±10% Buffered external reference mode. An external 1.024V ±10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN/2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. <0.3V Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference sources. VREF is the difference between the externally applied VREFP and VREFN. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. values originally held on C2a and C2b. These values are then presented to the first stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1193 to track and sample/hold analog inputs of high frequencies (>Nyquist). Both ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or singleended. Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance. Analog Inputs and Reference Configurations The MAX1193 full-scale analog input range is ±VREF with a common-mode input range of VDD/2 ±0.2V. VREF is the difference between V REFP and V REFN . The MAX1193 provides three modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 1). In internal reference mode, connect REFIN to VDD or leave REFIN unconnected. VREF is internally generated to be 0.512V ±3%. COM, REFP, and REFN are lowimpedance outputs with VCOM = VDD/2, VREFP = VDD/2 + VREF/2, and VREFN = VDD/2 - VREF/2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. In buffered external reference mode, apply a 1.024V ±10% at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with VCOM = VDD/2, VREFP = V DD /2 + V REFIN /4, and V REFN = V DD /2 - V REFIN /4. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for COM, REFP, and REFN. With their buffers shut down, these nodes become high-impedance inputs (Figure 4) and can be driven through separate, external reference sources. Drive VCOM to VDD/2 ±10%, drive 62.5µA MAX1193 REFP 1.75V 4kΩ 0µA COM 1.5V 4kΩ 62.5µA REFN 1.25V Figure 4. Unbuffered External Reference Mode Impedance VREFP to (VDD/2 +0.256V) ±10%, and drive VREFN to (VDD/2 - 0.256V) ±10%. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section. Clock Input (CLK) CLK accepts a CMOS-compatible signal level. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to ______________________________________________________________________________________ 15 MAX1193 Table 1. Reference Modes MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC 5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB) CHA CHB tCLK tCL tCH CLK tDOB A/B tDOA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB D0B D1A D1B D2A D2B D3A D3B D4A D4B D5A D5B D6A D6B tDA/B D0–D7 Figure 5. System Timing Diagram provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: System Timing Requirements Figure 5 shows the relationship between the clock, analog inputs, A/B indicator, and the resulting output data. Channel A (CHA) and channel B (CHB) are simultaneously sampled on the rising edge of the clock signal (CLK) and the resulting data is multiplexed at the output. CHA data is updated on the rising edge and CHB data is updated on the falling edge of the CLK. The A/B indicator follows CLK with a typical delay time of 6ns and remains high when CHA data is updated and low when CHB data is updated. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for CHA and 5.5 clock cycles for CHB. 16 VREF = VREFP - VREFN VREF VREF 1000 0001 1000 0000 0111 1111 (COM) VREF where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1193 clock input operates with a VDD/2 voltage threshold and accepts a 50% ±10% duty cycle (see Typical Operating Characteristics). 2 x VREF 256 VREF 1111 1111 1111 1110 1111 1101 OFFSET BINARY OUTPUT CODE (LSB) 1 SNR = 20 × log 2 × π × f IN × t AJ 1LSB = 0000 0011 0000 0010 0000 0001 0000 0000 -128 -127 -126 -125 -1 0 +1 +125 +126 +127 +128 (COM) INPUT VOLTAGE (LSB) Figure 6. Transfer Function Digital Output Data (D0–D7), Channel Data Indicator (A/B) D0–D7 and A/B are TTL/CMOS-logic compatible. The digital output coding is offset binary (Table 2, Figure 6). The capacitive load on the digital outputs D0–D7 should be kept as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX1193 and degrading its dynamic performance. Buffers on the digital outputs isolate them from ______________________________________________________________________________________ Ultra-Low-Power, 45Msps, Dual 8-Bit ADC MAX1193 Table 2. Output Codes vs. Input Voltage DIFFERENTIAL INPUT VOLTAGE (IN+ - IN-) DIFFERENTIAL INPUT (LSB) OFFSET BINARY (D7–D0) OUTPUT DECIMAL CODE 127 128 126 VREF × 128 1 VREF × 128 +127 (+ full scale – 1 LSB) 1111 1111 255 +126 (+ full scale – 2 LSB) 1111 1110 254 +1 1000 0001 129 0 (bipolar zero) 1000 0000 128 -1 0111 1111 127 -127 (- full scale + 1 LSB) 0000 0001 1 -128 (- full scale) 0000 0000 0 VREF × 0 128 1 -VREF × 128 127 -VREF × 128 VREF × -VREF × 128 128 Table 3. Power Logic PD0 PD1 POWER MODE ADC 0 0 Shutdown Off 0 1 Standby Off 1 0 Idle On 1 1 Normal Operating On INTERNAL REFERENCE heavy capacitive loads. To improve the dynamic performance of the MAX1193, add 100Ω resistors in series with the digital outputs close to the MAX1193. Refer to the MAX1193 Evaluation Kit schematic for an example of the digital outputs driving a digital buffer through 100Ω series resistors. Power Modes (PD0, PD1) The MAX1193 has four power modes that are controlled with PD0 and PD1. Four power modes allow the MAX1193 to efficiently use power by transitioning to a low-power state when conversions are not required (Table 3). Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the MAX1193 and placing the outputs in tri-state. The CLOCK DISTRIBUTION OUTPUTS Off Off Tri-state On On Tri-state On On Tri-state On On On wake-up time from shutdown mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 20µs. When operating in the unbuffered external reference mode, the wake-up time is dependent on the external reference drivers. When the outputs transition from tri-state to on, the last converted word is placed on the digital outputs. In standby mode, the reference and clock distribution circuits are powered up, but the pipeline ADCs are unpowered and the outputs are in tri-state. The wakeup time from standby mode is dominated by the 2.6µs required to activate the pipeline ADCs. When the outputs transition from tri-state to on, the last converted word is placed on the digital outputs. ______________________________________________________________________________________ 17 MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC R4 600Ω R5 600Ω RISO 22Ω MAX1193 R1 600Ω VCOM = 1V TO 1.5V VSIG = ±85mVP-P R2 300Ω R3 600Ω INACIN 5pF R6 600Ω R7 600Ω COM AV = 6V/V VCOM = VDD/2 R8 600Ω R9 600Ω RISO 22Ω CIN 5pF R10 600Ω OPERATIONAL AMPLIFIERS CHOOSE EITHER OF THE MAX4452/MAX4453/MAX4454 SINGLE/ DUAL/QUAD +3V, 200MHz OP AMPS FOR USE WITH THIS CIRCUIT. CONNECT THE POSITIVE SUPPLY RAIL (VCC) TO 3V. CONNECT THE NEGATIVE SUPPLY RAIL (VEE) TO GROUND. DECOUPLE VCC WITH A 0.1µF CAPACITOR TO GROUND. INA+ R11 600Ω RESISTOR NETWORKS RESISTOR NETWORKS ENSURE PROPER THERMAL AND TOLERANCE MATCHING. FOR R1, R2, AND R3 USE A NETWORK SUCH AS VISHAY'S 3R MODEL NUMBER 300192. FOR R4–R11, USE A NETWORK SUCH AS VISHAY'S 4R MODEL NUMBER 300197. Figure 7. DC-Coupled Differential Input Driver In idle mode, the pipeline ADCs, reference, and clock distribution circuits are powered, but the outputs are forced to tri-state. The wake-up time from idle mode is dominated by the 5ns required for the output drivers to start from tri-state. When the outputs transition from tristate to on, the last converted word is placed on the digital outputs. In the normal operating mode, all sections of the MAX1193 are powered. 18 Applications Information The circuit of Figure 7 operates from a single 3V supply and accommodates a wide 0.5V to 1.5V input commonmode voltage range for the analog interface between an RF quadrature demodulator (differential, DC-coupled signal source) and a high-speed ADC. Furthermore, the circuit provides required SINAD and SFDR to demodulate a wideband (BW = 3.84MHz), QAM-16 communication link. RISO isolates the op amp output from the ADC capacitive input to prevent ringing and oscillation. CIN filters high-frequency noise. ______________________________________________________________________________________ Ultra-Low-Power, 45Msps, Dual 8-Bit ADC MAX1193 REFP 25Ω INA+ 22pF 1kΩ VIN 0.1µF 0.1µF 1 VIN T1 6 INA+ MAX4108 100Ω 2 5 3 4 N.C. RISO 50Ω CIN 22pF 1kΩ COM 2.2µF COM 0.1µF REFN 0.1µF RISO 50Ω MINICIRCUITS TT1-6-KK81 25Ω INA- 100Ω INA- CIN 22pF 22pF MAX1193 REFP 25Ω MAX1193 INB+ 22pF VIN 0.1µF 1kΩ 0.1µF 1 VIN T1 6 INB+ MAX4108 100Ω N.C. 2 5 3 4 2.2µF RISO 50Ω 1kΩ CIN 22pF 0.1µF REFN 0.1µF RISO 50Ω MINICIRCUITS TT1-6-KK81 25Ω INB22pF Figure 8. Transformer-Coupled Input Drive Using Transformer Coupling An RF transformer (Figure 8) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1193 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. In general, the MAX1193 provides better SFDR and THD with fully differential input signals than singleended drive, especially for high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are bal- 100Ω INBCIN 22pF Figure 9. Using an Op Amp for Single-Ended, AC-Coupled Input Drive anced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode. Single-Ended AC-Coupled Input Signal Figure 9 shows an AC-coupled, single-ended application. Amplifiers such as the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. Buffered External Reference Drives Multiple ADCs The buffered external reference mode allows for more control over the MAX1193 reference voltage and allows multiple converters to use a common reference. To drive one MAX1193 in buffered external reference mode, the external circuit must sink 0.7µA, allowing one reference circuit to easily drive the REFIN of multiple converters to 1.024V ±10%. ______________________________________________________________________________________ 19 MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC 3V 24 0.1µF 1.248V VDD REFIN 0.1µF 1 2 27 MAX6061 3 10Hz LOWPASS FILTER REFP N=1 0.33µF 1% 20kΩ MAX1193 26 REFN 0.33µF 1% 90.9kΩ 1µF 25 3V 3 NOTE: ONE FRONT-END REFERENCE CIRCUIT PROVIDES ±15mA OF OUTPUT DRIVE AND SUPPORTS OVER 1000 MAX1193s. 5 GND 0.1µF 1 4 COM 0.33µF 15Ω 1.023V MAX4250 2 24 VDD REFIN 0.1µF 2.2µF 0.1µF 27 REFP N = 1000 0.33µF MAX1193 26 REFN 0.33µF 25 COM 0.33µF GND Figure 10. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference Figure 10 shows the MAX6061 precision bandgap reference used as a common reference for multiple converters. The 1.248V output of the MAX6061 is divided down to 1.023V as it passes through a one-pole, 10Hz, lowpass filter to the MAX4250. The MAX4250 buffers the 1.023V reference before its output is applied to the MAX1193. The MAX4250 provides a low offset voltage (for high gain accuracy) and a low noise level. 20 Unbuffered External Reference Drives Multiple ADCs The unbuffered external reference mode allows for precise control over the MAX1193 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven directly by a set of external reference sources. ______________________________________________________________________________________ Ultra-Low-Power, 45Msps, Dual 8-Bit ADC MAX1193 3V 2.500V 1 0.1µF 2 27 MAX6066 1% 30.1kΩ 3 3 10µF 6V 6 UNCOMMITTED 0.1µF 1/4 1MΩ 13 14 MAX4254 330µF 6V 1.47kΩ 7 10µF 6V REFIN 24 COM GND 0.1µF 8 27 VDD REFP N = 160 0.33µF 47Ω MAX4254 10µF 6V 2.2µF 1.47kΩ 1.248V 1/4 11 25 0.33µF 330µF 6V 10 9 MAX1193 47Ω MAX4254 1% 10.0kΩ 4 REFN 0.33µF 1.498V 3V 1MΩ 26 47Ω 1% 10.0kΩ 5 1/4 12 1 MAX4254 1µF NOTE: ONE FRONT-END REFERENCE CIRCUIT SUPPORTS UP TO 160 MAX1193. N=1 0.33µF 1.748V 1/4 2 VDD REFP 330µF 6V 1.47kΩ 26 REFN MAX1193 REFIN 24 0.33µF 1% 49.9kΩ 25 0.33µF COM GND Figure 11. External Unbuffered Reference Driving 160 ADCs with MAX4254 and MAX6066 Figure 11 shows the MAX6066 precision bandgap reference used as a common reference for multiple converters. The 2.500V output of the MAX6066 is followed by a 10Hz lowpass filter and precision voltage-divider. The MAX4254 buffers the taps of this divider to provide the 1.75V, 1.5V, and 1.25V sources to drive REFP, REFN, and COM. The MAX4254 provides a low offset voltage and low noise level. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference-voltage and amplifier noise to a level of 3nV/√Hz. The 1.75V and 1.25V reference volt- ages set the differential full-scale range of the associated ADCs at ±0.5V. The common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. With the outputs of the MAX4252 matching better than 0.1%, the buffers and subsequent lowpass filters support as many as 160 MAX1193 ADCs. ______________________________________________________________________________________ 21 MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC A/B MAX2451 INA+ INA0° 90° MAX1193 DSP POSTPROCESSING INB+ INBDOWNCONVERTER ÷8 Figure 12. Typical QAM Receiver Application Typical QAM Demodulation Application Quadrature amplitude modulation (QAM) is frequently used in digital communications. Typically found in spread-spectrum-based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent upconversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90° phase shifted with respect to the in-phase component. At the receiver, the QAM signal is demodulated into analog I and Q components. Figure 12 displays the demodulation process performed in the analog domain using the MAX1193 dual-matched, 3V, 8-bit ADC and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1193, the mixed-down signal components can be filtered by matched analog filters, such as Nyquist or pulse-shaping filters. The filters remove unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference. Grounding, Bypassing, and Board Layout The MAX1193 requires high-speed board layout design techniques. Refer to the MAX1193 Evaluation Kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, prefer- 22 ably on the same side as the ADC, using surfacemount devices for minimum inductance. Bypass VDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF bipolar capacitor. Bypass OVDD to OGND with a 0.1µF ceramic capacitor in parallel with a 2.2µF bipolar capacitor. Bypass REFP, REFN, and COM each to GND with a 0.33µF ceramic capacitor. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Use a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC’s package. Connect the MAX1193 exposed backside paddle to GND. Join the two ground planes at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90° turns. ______________________________________________________________________________________ Ultra-Low-Power, 45Msps, Dual 8-Bit ADC Aperture Jitter CLK Figure 13 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. ANALOG INPUT Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 13). tAD tAJ SAMPLED DATA (T/H) T/H Signal-to-Noise Ratio (SNR) HOLD TRACK TRACK Figure 13. T/H Aperture Timing Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1193 are measured using the end-point method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Offset Error Ideally, the midscale MAX1193 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. Gain Error Ideally, the full-scale MAX1193 transition occurs at 1.5 LSB below full-scale. The gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02 × N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ENOB = SINAD - 1.76 6.02 ______________________________________________________________________________________ 23 MAX1193 Dynamic Parameter Definitions MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC Total Harmonic Distortion (THD) Third-Order Intermodulation (IM3) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: IM3 is the power of the worst third-order intermodulation product relative to the input power of either input tone when two tones, f1 and f2, are present at the inputs. The third-order intermodulation products are (2 x f1 ±f2), (2 x f2 ±f1). The individual input tone levels are at -7dB FS. V2 2 + V3 2 + V4 2 + V5 2 + V6 2 THD = 20 × log V1 where V1 is the fundamental amplitude, and V2–V6 are the amplitudes of the 2nd- through 6th-order harmonics. Third Harmonic Distortion (HD3) HD3 is defined as the ratio of the RMS value of the third harmonic component to the fundamental input signal. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. The intermodulation products are (f1 ±f2), (2 x f1), (2 x f2), (2 x f1 ±f2), (2 x f2 ±f1). The individual input tone levels are at -7dB FS. Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supplies are moved ±5%. Small-Signal Bandwidth A small -20dB FS analog input signal is applied to an ADC in such a way that the signal’s slew rate will not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Note that the track/hold (T/H) performance is usually the limiting factor for the small-signal input bandwidth. Full-Power Bandwidth A large -0.5dB FS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. Chip Information TRANSISTOR COUNT: 7925 PROCESS: CMOS 24 ______________________________________________________________________________________ Ultra-Low-Power, 45Msps, Dual 8-Bit ADC b CL 0.10 M C A B D2/2 D/2 PIN # 1 I.D. QFN THIN.EPS D2 0.15 C A D k 0.15 C B PIN # 1 I.D. 0.35x45 E/2 E2/2 CL (NE-1) X e E E2 k L DETAIL A e (ND-1) X e CL CL L L e e 0.10 C A C 0.08 C A1 A3 PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm APPROVAL DOCUMENT CONTROL NO. REV. 21-0140 C 1 2 ______________________________________________________________________________________ 25 MAX1193 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) COMMON DIMENSIONS EXPOSED PAD VARIATIONS NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. PROPRIETARY INFORMATION 9. DRAWING CONFORMS TO JEDEC MO220. TITLE: PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm 10. WARPAGE SHALL NOT EXCEED 0.10 mm. APPROVAL DOCUMENT CONTROL NO. REV. 21-0140 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.