Agilent HDMP-1685A 1.25 Gbps Four Channel SerDes with 5-pin DDR SSTL_2 Parallel Interface Data Sheet Functional Description This data sheet describes HDMP1685A, a 1.25 Gbps, four-channel, 5-pin per channel parallel interface SERDES device. The HDMP-1685A 5-pin parallel interface device enables a single ASIC to drive twice as many channels using half as many parallel lines. This is accomplished without increasing the clock frequency by utilizing the bandwidth on the parallel interface more efficiently. The HDMP-1685A SERDES is a single silicon bipolar integrated circuit packaged in a 208-pin BGA. This integrated circuit provides a low-cost, small-form-factor physicallayer solution for multi-link 1.25 Gbps cables or optical transceivers. Each IC contains transmit and receive channel circuitry for all four channels. A 125 MHz LVTTL reference clock must be supplied to the reference clock input pin, RFCT. The transmitter section accepts four, 5-bit-wide parallel SSTL_2 data (TX [0:3] [0:4]), a 125 MHz SSTL_2 byte clock (TC) and serializes them into four high-speed serial streams. The parallel data is expected to be “8B/10B” encoded data, or equivalent. TX and TC are source synchronous. New data are accepted on both edges of TC; this is called Double Data Rate (DDR). HDMP-1685A finds a sampling window in between the two edges of TC to latch TX [0:3] [0:4] data into the input register of the transmitter section. This timing scheme assumes that the driving ASIC and HDMP-1685A operate in the same clock domain. 8B/10B encoded data comes in 10-bit characters. This data is latched onto the 5 TX pins of each channel in 5-bit groups. It is expected that the beginning half of each 10-bit character is latched on the rising edge of TC. Features • 5-bit wide Tx, Rx bus pairs • 208-ball, 23 mm TBGA package • Parallel data I/O and clocks compatible with SSTL_2 (EIA/JESD8-9) • 125 MHz TC, RC clocks • One TC clock for 4 channels • Single or paired RC clocks • LVTTL RefClk input • Source synchronous clocking of transmit data • Source centered clocking of receive data • Double data rate (DDR) parallel transfers • Parallel loopback • Differential BLL serial I/O • Single +3.3 V power supply • Copper drive capability Applications • High density fast ports • Fast serial backplanes • Clusters of computers • Clusters of network units • Link aggregation, trunks The transmitter section’s PLL locks to the 125 MHz TC. This clock is then multiplied by 10 to generate the 1250 MHz serial clock for the high-speed serial outputs. The high-speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission. The receiver section accepts four serial electrical data streams at 1250 MBd and recovers the respective original 10-bit-wide data for each channel over a 5-pin parallel interface. The receiver PLL locks onto the incoming serial signal and recovers the high-speed serial clock and data. The serial data is converted back into 10-bit parallel data, optionally recognizing the 8B/10B comma character to establish byte alignment. If comma character detection is enabled by raising the SYNC signal high, the receiver section is able to detect comma characters and indicate their presence on each channel with the appropriate SYN [0:3] signal(s). The recovered parallel data are presented at SSTL_2-compatible outputs RX [0:3] [0:4], and a pair of 125 MHz SSTL_2 clocks, RC [0:3] [1], and RC [0:3] [0], that are 180 degrees out of phase from one another and which represent the remote clock for that channel. Rising edges of RC [0:3] [1] and RC [0:3] [0] may be used to latch RX data at the destination. Alternatively, both edges of either RC [0:3] [1] or RC [0:3] [0] may be used to latch RX data (DDR). When SYNC is high, the beginning half of the comma character shows up at the rising edge of RC [0:3] [1]. The timing of transmit and receive parallel data with respect to TC and RC [0:3] [0:1] is arranged so that the upstream protocol device can generate and latch data very simply. Specifically, in the TX direction, the ASIC drives four sets of 5-pin TX lines and the TC line with the same timing. The 2 TC line is similar to a 6th data line that is always toggling to provide timing information to the SERDES. On the RX side, the SERDES drives four sets of 5-pin RX data centered between the edges of RC [0:3] [1] or RC [0:3] [0]. For test purposes, the transceiver provides for on-chip parallel loopback functionality controlled through an input pin. Additionally, the byte-edge alignment feature via detection of the positive comma (K28.5+) character may be disabled. This may be useful in proprietary applications that use alternative methods to align the parallel data. HDMP-1685A Block Diagram The HDMP-1685A (Figure 2) is designed to transmit and receive 10-bit 8B/10B character data over 5-pin-wide parallel busses via high-speed serial communication lines. The parallel data applied to the transmitter is expected to be encoded per the 8B/10B encoding scheme with special reserve characters for link management purposes. Other encoding schemes will also work as long as they provide dc balance and sufficient number of transitions. In order to accomplish this task, the HDMP-1685A incorporates the following: • SSTL_2 Parallel Data I/O • High-Speed Phase Locked Loops • Parallel-to-Serial Converters • High-Speed Serial Clock and Data Recovery Circuitry • Comma Character Recognition Circuitry (K28.5+) • Byte Alignment Circuitry • Serial-to-Parallel Converter PARALLEL INPUT LATCH For each channel, the transmitter accepts 10-bit characters as two groups of 5-pin single-ended SSTL_2 parallel data at inputs TX [0:3][0:4]. The SSTL_2 TC clock provided by the sender of transmit data is used for all channels as the transmit byte clock. The TX [0:3][0:4] and TC signals must be properly aligned, as shown in Figure 3. TX PLL/CLOCK GENERATOR The transmitter Phase Locked Loop and Clock Generator (TX PLL/CLOCK GENERATOR) block generates all internal clocks needed by the transmitter section to perform its functions. These clocks are based on the transmit byte clock (TC). TC is also used to determine the sampling window for the incoming data latches. Incoming data is synchronous with TC (see Figure 3). FRAME MUX The FRAME MUX accepts the 10-bit-wide parallel data from the INPUT LATCH. Using internally generated high-speed clocks, this parallel data is multiplexed into the 1250 MBd serial data streams. The data bits are transmitted sequentially, from TX [0] to TX [4]. The leftmost bit of K28.5 is on TX [0]. SERIAL OUTPUT SELECT The OUTPUT SELECT block provides a parallel loopback mode for testing purposes. In normal operation, PLUP is set low and the serialized TX [0:3] [0:4] data are placed at SO [0:3] +/-. When parallel wrap-mode is activated by setting PLUP high, the SO [0:3]+/- pins are held static at logic 1 and the serial output signal reflecting TX [0:3] [0:4] data is internally wrapped to the INPUT SELECT block of the receiver section. SERIAL INPUT SELECT The INPUT SELECT block determines whether the signal at SI [0:3]+/- or the internal loopback serial signal is used to drive RX [0:3] [0:4]. In normal operation, PLUP is set low and the serial data is accepted at SI [0:3]+/-. When PLUP is set high, the outgoing high-speed serial signal is internally looped back from the transmitter section to the receiver section. This feature allows parallel loopback testing, exclusive of the transmission medium. RX PLL/CLOCK RECOVERY The RX PLL/CLOCK RECOVERY block is responsible for frequency and phase locking onto the incoming serial data stream and recovering the bit and byte clocks. It does this by continually frequency locking onto the 125 MHz reference clock, and then phase locking onto the selected input data stream. An internal signal detection circuit monitors the presence of the input, and invokes the phase detection once the minimum differential input signal level is supplied (AC Electrical Specifications). Once bit locked, the receiver generates the high-speed sampling clock at 1250 MHz for the input sampler. 3 SERIAL INPUT SAMPLER The INPUT SAMPLER converts the serial input signal into a retimed bit stream. In order to accomplish this, it uses the highspeed serial clock recovered from the RX PLL/CLOCK RECOVERY block. This serial bit stream is sent to the FRAME DEMUX AND BYTE SYNC block. FRAME DEMUX, BYTE SYNC The FRAME DEMUX AND BYTE SYNC block is responsible for restoring the 10-bit character from the high-speed serial bit stream. This block is also responsible for recognizing the comma character (K28.5+) of positive disparity (0011111xxx). When recognized, the FRAME DEMUX AND BYTE SYNC block works with the RX PLL/CLOCK RECOVERY block to properly select the parallel data edge out of the bit stream so that the comma character starts at RX[0:3][0]. When a comma character is detected and realignment of the receiver byte clock RC[0:3][0:1] is necessary, this clock is stretched, not slivered, to the next possible correct alignment position. This clock will be fully aligned by the start of the second 2-byte or 4-byte ordered set. The second comma character received will be aligned with the rising edge of RC[0:3][1]. Comma characters of positive disparity must not be transmitted in consecutive bytes to allow the receiver byte clocks to maintain their proper recovered frequencies. PARALLEL OUTPUT DRIVERS The OUTPUT DRIVERS present the recovered 10-bit character in two groups onto the 5-pin RX bus, properly aligned to the receive byte clock RC [0:3] [0:1] as shown in Figure 5. These output data buffers provide single-ended SSTL_2 compatible signals. Unlike the TX, where all four channels are driven with the same transmit byte clock (TC), each receive channel provides its own clock aligned with its own data, so the recovered clocks may not be phase aligned. SSTL_2 COMPATIBILITY HDMP-1685A works with protocol devices whose VDDQ voltage is nominally set at 2.5 Volts. RX [0:3][0:4], RC [0:3][0:1] pins generate output voltages that are compatible with the SSTL_2 standard (EIA/JESD8-9). In addition, these devices provide a VREFR output pin allowing the receiving device to differentially detect a high or a low. The devices receive inputs on their TX [0:3][0:4] and TC pins that are also SSTL_2 compatible. The VREFT input pin is driven by a voltage divider whose supply voltage is at the same level as the VDDQ supply of the protocol device. This allows differential detection of a high or a low at TX parallel inputs. RFCT RX3 RC31/0 TX3 RX2 TX2 RC21/0 TC RX1 RC11/0 TX1 RX0 RC01/0 TX0 4-CHANNEL ASIC SI3 SO3 SI2 SO2 SI1 SO1 SI0 SO0 HDMP-1685A TX(0:3)[0:4] INPUT LATCH Figure 1. Typical application of the four channel SERDES. FRAME MUX OUTPUT SELECT SO[0:3]± PLUP TX PLL CLOCK GENERATOR TC CAP0 CAP1 OUTPUT DRIVER FRAME DEMUX AND BYTE SYNC Figure 2. Block diagram of HDMP-1685A. 4 INPUT SELECT RX PLL CLOCK RECOVERY RFCT RC(0:3)[0:1] SYNC SYN(0:3) RX(0:3)[0:4] TX CLOCKS RX CLOCKS INPUT SAMPLER Sl[0:3]± HDMP-1685A Timing Characteristics – Transmitter Sections TA = 0°C to T C = 85°C, VCC = 3.15 V to 3.45 V Symbol Parameter Units tTXCT[2] tTXCV[2] TX [0:3][0:4] Input Data and TC Clock Transition Range ps TX [0:3][0:4] Input Data and TC Clock Valid Time ps t_txlat[1] Transmitter Latency ns bits Min. Typ. Max. 1600 2400 4 5 Note: 1. The transmitter latency, as shown in Figure 4, is defined as the time between the leading edge of the first half of a parallel 10-bit word and the leading edge of the first transmitted serial output bit of that 10-bit word. 2. Agilent‘s HDMP-1685A internally generates another clock which is 90 degrees out of phase with the TC clock supplied. This clock, which will have its edges at the center of the data valid eye, is used to clock in the TX[0:4] data. Setup and hold times are taken care of by the HDMP-1685A provided the specifications indicated are met. 8 ns TXCT TX[0:3][0:4] TXCV TXCV TC Figure 3. Transmitter section parallel input timing. 10-BIT CHAR A 10-BIT CHAR B SO[0:3]± TX[0] TXLAT TX[0:3][0:4] CHAR B[4:0] CHAR B[9:5] TC Figure 4. Transmitter section latency. TX[0] is first on serial wire. 5 TX[9] HDMP-1685A Timing Characteristics – Receiver Sections – Rising Edge Clocking TA = 0°C to TC = 85°C, VCC = 3.15 V to 3.45 V Symbol Parameter Units f_lock Frequency Lock at Powerup µs 500 B_sync[1,2] Bit Sync Time bits 2500 tRXS RX [0:3][0:4] Setup Time (Data Valid Before Clock) ps 1200 tRXH RX [0:3][0:4] Hold Time (Data Valid After Clock) ps 800 RC [0:3][1] to RC [0:3][0] Skew ns 3.5 4.5 RC [0:3][1] and RC [0:3][0] Duty Cycle % 40 60 Receiver Latency ns bits t_rxlat[3] Min. Typ. Max. 16 20 Notes: 1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3. 2. Tested using CPLL = 0.1 µF. 3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC [0:1]). 8 ns RC[0:3][1] RC[0:3][0] RXS RXS RXH RXH RX[0:3][0:4] Figure 5a. Receiver section parallel output timing using rising edge of both RC[0:3][0] and RC[0:3][1]. 6 HDMP-1685A Timing Characteristics – Receiver Sections – Rising and Falling Edge Clocking TA = 0°C to T C = 85°C, VCC = 3.15 V to 3.45 V Symbol Parameter Units f_lock Frequency Lock at Powerup µs 500 B_sync[1,2] Bit Sync Time bits 2500 tRXS RX [0:3][0:4] Setup Time (Data Valid Before Clock) ps 1000 tRXH RX [0:3][0:4] Hold Time (Data Valid After Clock) ps 800 RC [0:3][1] and RC [0:3][0] Duty Cycle % 40 Receiver Latency ns bits t_rxlat[3] Min. Typ. Max. 60 16 20 Notes: 1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3. 2. Tested using CPLL = 0.1 µF. 3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC [0:1]). 8 ns RC[0:3][0] or RC[0:3][1] RXS RXS RXH RXH RX[0:3][0:4] Figure 5b. Receiver section parallel output timing using rising and falling edge of either RC[0:3][0] or RC[0:3][1]. 10-BIT CHAR B 10-BIT CHAR C SI[0:3]± RX[0] RX[9] RXLAT RX[0:3][0:4] CHAR A[4:0] RC[0:3][1] RC[0:3][0] Figure 6. Receiver section latency. First bit on serial wire drives RX[0:3][0]. 7 CHAR A[9:5] CHAR B[4:0] HDMP-1685A Absolute Maximum Ratings TA = 25°C, except as specified. Sustained operation at or beyond any of these conditions may result in long-term reliability degradation or permanent damage, and is not recommended. Symbol Parameter Units Min. Max. VCC Supply Voltage V –0.5 5.0 VIN,LVTTL RFCT LVTTL Input Voltage V –0.7 VCC + 2.8 VIN,SSTL SSTL Input Voltage V –0.7 VCC + 0.7 VIN,HS_IN HS_IN Input Voltage (Differential) V Tstg Storage Temperature °C –65 +150 Tj Junction Temperature °C 0 +125 TC Case Temperature °C 0 95 2.2 HDMP-1685A Guaranteed Operating Rates TA = 0°C to TC = 85°C, VCC = 3.15 V to 3.45 V Parallel Clock Rate (MHz) Min. Max. Serial Baud Rate (MBaud) Min. Max. 124.0 1240 126.0 1260 HDMP-1685A Reference Clock and Transmit Byte Clock Requirements TA = 0°C to TC = 85°C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Min. Typ. Max. f Nominal Frequency MHz Ftol Frequency Tolerance ppm –100 +100 SymmRFC Symmetry (Duty Cycle) Reference Clock % 40 60 SymmTC Symmetry (Duty Cycle) Transmit Byte Clock % 40 60 125 HDMP-1685A LVTTL I/O DC Electrical Specifications TA = 0°C to TC = 85°C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Min. VIH,LVTTL LVTTL Input High Voltage Level, Guaranteed High Signal for All Inputs V 2 5.5 VIL,LVTTL LVTTL Input Low Voltage Level, Guaranteed Low Signal for All Inputs V 0 0.8 VOH,LVTTL LVTTL Output High Voltage Level, IOH = –400 µA V 2.2 VCC VOL,LVTTL LVTTL Output Low Voltage Level, IOL = 1 mA V 0 0.5 IIH,LVTTL Input High Current, VIN = 2.4 V, VCC = 3.45 V µA 40 IIL,LVTTL Input Low Current, VIN = 0.4 V, VCC = 3.45 V µA –600 8 Typ. Max. HDMP-1685A SSTL_2 I/O DC Electrical Parameters TA = 0°C to T C = 85°C, VCC = 3.15 V to 3.45 V, VDDQ = 2.30 V to 2.70 V. VDDQ is the FC-1/MAC device I/O supply voltage. SSTL-2 inputs can receive LVTTL signals successfully. SSTL-2 outputs do not output LVTTL compliant levels. Symbol Parameter Units Min. Typ. Max. VREFT SSTL_2 Input Reference Voltage V 1.15 1.25 1.35 VIH Input High Voltage V VREFT +0.18 VDDQ +0.30 VIL Input Low Voltage V –0.30 VREFT –0.18 VREFR SSTL_2 Output Reference Voltage V 1.15 VOH Output High Voltage V VREFR +0.38 VDDQ VOL Output Low Voltage V GND VREFR –0.38 1.25 1.35 HDMP-1685A AC Electrical Specifications (TRx) TA = 0°C to T C = 85°C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Min. Typ. Max. tr,RFCT RFCT LVTTL Input Rise Time, 0.8 to 2.0 Volts ns 0 2.4 tf,RFCT RFCT LVTTL Input Fall Time, 2.0 to 0.8 Volts ns 0 2.4 tr,SSTLo SSTL Output Rise Time, 1.0 V to 1.6 V ns 0.4 1.5 tf,SSTLo SSTL Output Fall Time, 1.6 V to 1.0 V ns 0.28 1.5 trs, HS_OUT HS_OUT Single-Ended (SO[0:3]±) Rise Time (20% - 80%) ps 85 205 300 tfs, HS_OUT HS_OUT Single-Ended (SO[0:3]±) Fall Time (20% - 80%) ps 85 180 300 trd, HS_OUT HS_OUT Differential Rise Time ps 85 300 tfd, HS_OUT HS_OUT Differential Fall Time ps 85 300 VIP,HS_IN HS_IN (SI[0:3]±) Input Peak-To-Peak Differential Voltage mV 200 1200 2000 VOP,HS_OUT [1] HS_OUT Output Pk-Pk Diff. Voltage (Z0=50 Ohms, Fig.10) mV 1000 1300 1800 Note: 1. Output Peak-to-Peak Differential Voltage specified as SO[0:3]+ minus SO[0:3]–. The amplitude will be 25% higher when terminating into 75 Ω loads. X1 WAVEFORM MATH f1 = 3 – 4 f2 = 1 – 2 X2 FUNCTION f1 f2 DEFINE FUNCTION... DISPLAY off on VERTICAL SCALE auto 120.0 ps/div 130.3664 ns Y 1 (f2) = –637.00 mV 2 (f2) = 636.00 mV ∆ = 9 Y SCALE X 130.549 ns 131.349 ns 800 ps 1.27300 V 1/∆X = 1.250 GHz Figure 7. Eye diagram of a high speed differential output. manual 250 mV/div Y OFFSET 0.0 V HDMP-1685A Output Jitter Characteristics – Transmitter Section TA = 0°C to TC = 85°C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Typ. RJ[1] Random Jitter at DOUT, the High Speed Electrical Data Port, specified as 1 sigma deviation of the 50% crossing point (RMS) ps 11 DJ[1] Deterministic Jitter at DOUT, the High Speed Electrical Data Port (pk-pk) ps 26 Note: 1. Defined by Fibre Channel Specification X3.230-1994 FC-PH Standard, Annex A, Section A.4 and tested using measurement method shown in Figure 8. A 70841B PATTERN GENERATOR A 70311A CLOCK SOURCE +K28.5, -K28.5 A 70841 PATTERN GENERATOR + DATA - DATA 1.25 GHz A 83480A OSCILLOSCOPE A 83480A OSCILLOSCOPE 1000001111 + DATA - DATA 125 MHz TRIGGER CH1 CH2 DIVIDE BY 10 CIRCUIT DIVIDE BY 2 TRIGGER CH1 CH2 A 70311A CLOCK SOURCE SOi+ BIAS TEE SOi– HDMP-1685 SOi+ VARIABLE DELAY TXi[0:4] 125 MHz SYNC PLUP TC TXi[0:4] 1.4 V SIi– SIi+ HDMP-1685A HDMP-1685 PLUP TC SOi– RXi[0:4] 0011111000 (STATIC K28.7) A. BLOCK DIAGRAM OF RJ MEASUREMENT METHOD B. BLOCK DIAGRAM OF DJ MEASUREMENT METHOD Figure 8. Transmitter jitter measurement method. HDMP-1685A Thermal and Power Temperature Characteristics (TRx) TA = 0°C to TC = 85°C, VCC = 3.15 V to 3.45 V Symbol Parameter Units Typ. Max. ICC,TRx Transceiver VCC Supply Current, TA = 25°C mA 900 PD, TRx [1] Transceiver Power Dissipation, Outputs Connected per Recommended Bias Terminations with 27–1 PRBS Pattern W 2.97 Θjc[1] Thermal Resistance, Junction to Case °C/W 7.8 Tj Junction Temperature (absolute maximum) °C 0 +125 TC Case Temperature (absolute maximum) °C 0 +95 3.5 Note: 1. Based on independent package testing by Agilent. Θja for these devices is 36°C/W for the HDMP-1685A. Θja is measured on a standard 3x3" FR4 PCB in a still air environment. To determine the actual junction temperature in a given application, use the following: Tj = Tc + (Θjc x PD), where Tc is the case temperature measured on the top center of the package and PD is the power being dissipated. 10 HDMP-1685A I/O Type Definitions I/O Type Definition I-LVTTL Input LVTTL, floats high when left open I-SSTL2 Input SSTL_2, floats low when left open O-SSTL2 Output SSTL_2 HS_OUT 50 Ω matched Output Driver. Will drive AC coupled 50 Ω loads. PECL level compatible (Figure 10). HS_IN PECL level compatible. Must be AC coupled (Figure 10). C External Circuit Node S Power Supply or Ground HDMP-1685A Pin Input Capacitance (TRx) Symbol Parameter Units Typ. CINPUT Input Capacitance on SSTL input pins pF 1.6 I_TTL VCC VCC VBB 1.4 V GND ESD PROTECTION GND Figure 9. LVTTL input simplified circuit schematic (for RFCT). HS_OUT HS_IN VCC VCCP Zo + – VCC Zo + – VCC SO[0:3]+ SI[0:3]+ Zo = 50 Ω 0.01 µF 2 * Zo = 100 Ω SO[0:3]– Zo = 50 Ω 0.01 µF GND SI[0:3]– GND ESD ESD PROTECTION PROTECTION GND GND NOTES: 1. HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. 2. CAPACITORS MAY BE PLACED AT THE SENDING END OR THE RECEIVING END. Figure 10. HS_OUT and HS_IN simplified circuit schematic. 11 Max. VCC (SERDES) = 3.3 V VCC (SERDES) = 3.3 V VCC (MAC) VDDQ (MAC) R1 VCC VCC 0.1 µF VDDQ R2 VREFR VREFT RS = 50 Ω UNTERMINATED RX[0:3][0:4] RC[0:3][0:1] DATAIN RS = 50 Ω USE TERMINATION, IF NECESSARY, TO DELIVER PROPER VOLTAGE SWINGS AT TX[0:4] TX[0:3][0:4] DATAOUT TC VDDQ (MAC) R1 VREFT 0.1 µF R2 HDMP-1685 MAC NOTE: VREFR ON EACH DEVICE MAY BE USED TO DRIVE VREFT ON THE OTHER DEVICE INSTEAD OF USING THE CONFIGURATION ABOVE. VREFR SHOULD BE BYPASSED WITH 0.1 µF IN THIS CASE. IF USED, R1 AND R2 SHOULD BE 500-1000 Ω. 1% RESISTORS SHOULD BE USED FOR R1 AND R2. WHEN USING THE CONFIGURATION ABOVE, VREFT TO THE MAC SHOULD BE SET TO 1.25 V NOMINAL. USING THIS VALUE CENTERS VREFR RELATIVE TO THE RX[0:3][0:4] OUTPUT SWINGS PROVIDED BY THE HDMP-1685A. Figure 11. O-SSTL_2 and I-SSTL_2 simplified circuit schematic. A 01 02 GND VCC 03 04 05 06 07 08 GND SYN1 RC10 RX10 RX14 B 09 10 VCR1 VCC 11 12 13 14 GND RX21 VCR2 15 16 17 GND VCR2 GND GND RC11 RX11 VCR1 GND SYN2 RX20 RX22 SYN3 RC30 RC31 C RX04 VCR0 VCR1 RX12 GND RC20 VCR2 RX23 VCC VCR3 GND RX30 D RX00 RX01 VCR0 GND GND RX13 VRFR RC21 GND RX24 RX31 RX32 RX33 RX34 E RC00 RC01 RX02 RX03 F SYN0 VCR0 GND G GND VCR3 GND GND VCC GND TX22 TX21 TX20 VCR3 H TX14 GNDA J TX10 TX11 TX12 TX13 VCCP VCC K GND GND VCC GND GND L GND VCCA TX33 TX32 TX31 TX30 VCC TX04 N TX00 TX01 TX02 TX03 P VRFT R RFCT U TC TX34 PLUP VCC GND SO0— GND SO1— GND CAP0 GND SO2+ GND SO3+ GND GND VCC SO0+ GND SO1+ GNDA CAP1 GND SO2— GND SO3— VCC GND VCC VCC VCP0 GND VCP1 GND VCCA GND VCP2 GND VCP3 VCC GND GND GND GND SIO— SI0+ VCC Figure 12. Pinout of HDMP-1685A (top view). 12 VCC VCR M T TX24 TX23 VCC SYNC SI1— SI1+ GND GND SI2— SI2+ GND SI3— SI3+ GND GND GND + VCC 10 µF * Filtering Schematic C5 D3 0.1 µF F3 G4 A16 A13 A10 VCR VCR VCR 0.1 µF VCR VCR VCR VCR VCC VCR VCR VCR VCC L4 VCR VCC B7 A2 VCC C4 A9 0.1 µF 0.1 µF HDMP-1685A GUIDELINES FOR DECOUPLING CAPACITOR PLACEMENTS/CONNECTIONS VCR C11 C14 0.1 µF C15 E14 G17 VCC VCC J14 VCC N15 0.1 µF K16 VCC 0.1 µF 0.1 µF 0.1 µF R4 0.1 µF VCC 02 03 04 10 µF 05 06 GND VCC C 07 08 09 VCR VCR VCR GND GND F VCR GND G GND VCC E VCC VCC T14 R14 VCP 10 11 12 13 14 16 17 GND VCR GND VCC VCR GND VCR GND 10 µF* VCC 15 0.1 µF GND VCR GND VCR VCR PLACEMENT NOT CRITICAL. INDICATES THE NEED FOR ADDITIONAL LOW FREQUENCY CAPACITIVE DECOUPLING. + OPTIONAL – PROVIDES INCREASED LOW FREQUENCY DECOUPLING. GND GND D T13 T11 0.1 µF 0.1 µF B R16 0.1 µF * + 10 µF + 0.1 µF A 0.1 µF 1 µH + 0.1 µF 01 VCP VCCA T9 VCP T7 T5 U5 T3 T4 VCP VCC VCC VCC VCC VCC GND VCR GND 0.1 µF 0.1 µF GND VCR 0.1 µF * 10 µF PLACEMENT NOT CRITICAL – INDICATES NEED FOR LOW-FREQUENCY BYPASS CAPACITANCE H VCC J GND GND L GND VCC 0.1 µF K HDMP-1685A GND GND VCC M 0.1 µF N GND GND GND GND GND VCC GND GND GND GND GND T U GND GND VCC VCC VCP VCC 0.1 µF GND VCP GND VCCA GND GND GND 0.1 µF 10 µF 13 VCP GND GND 0.1 µF VCP VCC GND VCC VCC GND GND GND GND 0.1 µF TO VCCA PI-FILTER (SEE SCHEMATIC) 0.1 µF R VCC GND P GND HDMP-1685A TRx I/O Definition Name Pin Type Signal CAP0 P09 C Loop Filter Capacitor: A loop filter capacitor for the internal PLLs must be connected across the CAP0 and CAP1 pins. (typical value = 0.1 µF) CAP1 R09 PLUP N14 I-SSTL2 Parallel Loopback Enable Input: When set high, a high-speed serial signal from the transmitter section’s serial output select block, reflecting TX data, is driven to the receiver section’s serial input select block. RX data reflects this serial signal. Also when in parallel loopback mode, the SO [0:3]+/- outputs are held static at logic 1. RFCT R01 I-LVTTL LVTTL Reference Clock: RFCT is a 125 MHz clock signal supplied to the IC. RC00 RC01 RC10 RC11 RC20 RC21 RC30 RC31 E01 E02 A05 B05 C10 D10 B16 B17 O-SSTL2 Receiver Byte Clocks: The receiver sections drive 125 MHz receive byte clocks RC [0:3] [0:1]. RX00 RX01 RX02 RX03 RX04 RX10 RX11 RX12 RX13 RX14 RX20 RX21 RX22 RX23 RX24 RX30 RX31 RX32 RX33 RX34 D01 D02 E03 E04 C01 A06 B06 C06 D06 A07 B11 A12 B12 C12 D12 C17 D14 D15 D16 D17 O-SSTL2 Data Outputs: Four 5-pin data busses. RX [0:3] [0] are the first bits received. SI0+ SI0SI1+ SI1SI2+ SI2SI3+ SI3- U04 U03 U07 U06 U11 U10 U14 U13 HS_IN Serial Data Inputs: High-speed inputs. Serial data are accepted from the SI [0:3]+/inputs except when PLUP is high. 14 HDMP-1685A TRx I/O Definition, continued Name Pin Type Signal SO0+ SO0SO1+ SO1SO2+ SO2SO3+ SO3- R05 P05 R07 P07 P11 R11 P13 R13 HS_ OUT Serial Data Outputs: High-speed outputs. These lines are active except when PLUP is high, in which case these outputs are held static at logic 1. SYNC R17 I-SSTL2 Enable Byte Sync Input: When high, turns on the internal byte sync functions to allow clock synchronization to a comma character of positive disparity (0011111XXX). When the line is low, the function is disabled and will not reset registers and clocks, or strobe the SYN [0:3] lines. SYN0 SYN1 SYN2 SYN3 F02 A04 B10 B15 O-SSTL2 Byte Sync Outputs: Active high outputs. Used to indicate detection of a comma character of positive disparity (0011111XXX) when SYNC is enabled. TC K17 I-SSTL2 Transmit Byte Clock: This signal is used to latch transmit data for all channels into the IC. TX00 TX01 TX02 TX03 TX04 TX10 TX11 TX12 TX13 TX14 TX20 TX21 TX22 TX23 TX24 TX30 TX31 TX32 TX33 TX34 N01 N02 N03 N04 M01 J01 J02 J03 J04 H01 G16 G15 G14 H17 H16 L17 L16 L15 L14 M17 I-SSTL2 Data Inputs: Four 5-pin data busses. TX [0:3] [0] are the first bits transmitted. VREFT P01 I-S TX Parallel Interface SSTL_2 Reference Voltage: Voltage reference derived from 2 resistor network with VDDQ (ASIC) as supply, as recommended in Figure 11. VREFR D07 O-S RX Parallel Interface SSTL_2 Reference Voltage: Provided by HDMP-1685A. Drives the VREF input of the ASIC. 15 HDMP-1685A TRx I/O Definition, continued Name Pin Type Signal VCC A02 A10 C14 G04 J14 K16 L04 N15 R04 R14 R16 T03 T04 T14 U05 S Power Supply: Normally 3.3 volts. Used for logic, SSTL inputs, and LVTTL I/O. VCCA T09 S Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for the PLLs and high-speed analog cells. VCR0 C04 D03 F03 A09 B07 C05 A13 A16 C11 C15 E14 G17 S Rx SSTL2 Output Power Supply: Normally 3.3 volts. Used for all SSTL2 receiver output buffer cells. VCP0 VCP1 VCP2 VCP3 T05 T07 T11 T13 S High-Speed Output Supply: Normally 3.3 volts. Used only for the last stage of the high-speed transmitter output cells (HS_OUT) as shown in Figure 10. Due to high current transitions, this VCC should be well bypassed to a ground plane. GNDA R08 S Analog Ground: Normally 0 volts. All GND pads on the chip are connected to one ground slug in the package, which then distributes these to GND balls. VCR1 VCR2 VCR3 16 HDMP-1685A TRx I/O Definition, continued Name Pin Type Signal GND A01 A03 A11 A15 A17 B04 B09 C07 C16 D04 D05 D11 E15 F04 F17 G03 K03 K04 K14 K15 L03 P04 P06 P08 P10 P12 R03 R06 R10 R12 R15 T02 T06 T08 T10 T12 T15 T16 U01 U02 U08 U09 U12 U15 U16 U17 S Logic Ground: Normally 0 volts. All GND pads on the chip are connected to one ground slug in the package, which then distributes these to GND balls. 17 HDMP-1685A TRx I/O Definition, continued Name Pin NC A08 A14 B01 B02 B03 B08 B13 B14 C02 C03 C08 C09 C13 D08 D09 D13 E16 E17 F01 F14 F15 F16 G01 G02 H02 H03 H04 H14 H15 J15 J16 J17 K01 K02 L01 L02 M02 M03 M04 M14 M15 M16 N16 N17 P02 P03 P14 P15 P16 P17 R02 T01 T17 18 Type Signal These pins are connected to an isolated pad and have no functionality. They may be left open, or LVTTL levels may be applied. Package Drawing D1 A2 S A O (4x) e e S E1 E D C B A 1 2 3 4 5 (CAVITY DOWN) (BACKFILL) Nx0b DETAIL A ddd Z ∅ eee M Z X Y [–Z–] SEATING PLANE A1 CORNER [–X–] D [–Y–] A3 [–Z–] SEATING PLANE (BACKFILL) DETAIL A E DIMENSIONS IN MILLIMETERS SYMBOL MIN. NOM. 1.35 1.50 1.65 A1 0.60 0.65 0.70 A2 0.85 0.90 0.95 A3 0.15 D 23.00 ± 0.20 D1 TOLERANCE OF FORM AND POSITION SYMBOL 19 MIN. NOM. MAX. A 20.32 BSC E 23.00 ± 0.20 E1 20.32 BSC MD/ME 17 N 208 N1 4 MAX. O 0.60 ddd 0.15 b 0.60 eee 0.30 e 0.75 1.27 ± 0.10 0.90 A1 www.semiconductor.agilent.com Data subject to change. Copyright © 2001 Agilent Technologies, Inc. May 7, 2001 Obsoletes 5988-1304EN 5988-2143EN