SHARP LH5P832

LH5P832
FEATURES
• 32,768 × 8 bit organization
• Access time: 100/120 ns (MAX.)
• Cycle time: 160/190 ns (MIN.)
• Power consumption:
Operating: 357.5/303 mW
Standby: 16.5 mW
• TTL compatible I/O
• 256 refresh cycle/4 ms
• Auto refresh is executed by internal
counter (controlled by OE/RFSH pin)
• Self refresh is executed by internal timer
• Single +5 V power supply
• Packages:
28-pin, 600-mil DIP
28-pin, 300-mil SK-DIP
28-pin, 450-mil SOP
DESCRIPTION
The LH5P832 is a 256K bit Pseudo-Static RAM organized as 32,768 × 8 bits. It is fabricated using silicon-gate CMOS process technology.
The LH5P832 uses convenient on-chip refresh circuitry with a DRAM memory cell for pseudo static
operation. This simplifies external clock inputs, while
providing the same simple, non-multiplexed pinout as
industry standard SRAMs. Moreover, due to the functional similarities between PSRAMs and SRAMs, many
32K × 8 SRAM sockets can be filled with the LH5P832
with little or no changes. The advantage is the cost
savings realized with the lower cost PSRAM.
CMOS 256K (32K × 8) Pseudo-Static RAM
The LH5P832 PSRAM has the ability to fill the gap
between DRAM and SRAM by offering low cost, low
standby power, and a simple interface.
Three methods of refresh control are provided for
maximum versatility. A ‘CE-Only’ refresh cycle refreshes the addressed row of memory cells transparently. All 256 rows must be refreshed or accessed every
four milliseconds. ‘Auto Refresh’ automatically cycles
through a different row on every OE/RFSH clock pulse,
accomplishing the row refreshes without the need to
supply row addresses externally. ‘Self Refresh’ further
simplifies the refresh requirements by eliminating the
need for address inputs and clock pulses entirely. An
automatic timer senses time periods when memory
accesses have ceased, and provides full refresh of all
rows of memory without any external assistance.
PIN CONNECTIONS
28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
TOP VIEW
A14
1
28
VCC
A12
2
27
R/W
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE/RFSH
A2
8
21
A10
A1
9
20
CE
A0
10
19
I/O8
I/O1
11
18
I/O7
I/O2
12
17
I/O6
I/O3
13
16
I/O5
GND
14
15
I/O4
5P832-1
Figure 1. Pin Connections for DIP, SK-DIP,
and SOP Packages
1
CMOS 256K (32K × 8) Pseudo-Static RAM
LH5P832
14 GND
28 VCC
VBB BIAS-GENERATOR
A14 1
A13 26
A12 2
A11 23
COLUMN
ADDRESS
BUFFER
A10 21
COLUMN
DECODER
A9 24
A8 25
A7 3
A6 4
ROW
ADDRESS
BUFFER
A5 5
A4 6
A3 7
A2 8
EXT/INT
ADDRESS
MUX
REFRESH
ADDRESS
COUNTER
A1 9
I/O
SELECTOR
SENSE
AMPS
ROW
DECODER
DATA
IN
BUFFER
11 I/O1
12 I/O2
13 I/O3
15 I/O4
16 I/O5
17 I/O6
MEMORY
ARRAY
256 ROWS
128 COLUMNS
18 I/O7
19 I/O8
DATA
OUT
BUFFER
A0 10
CLOCK
GENERATOR
CE 20
AUTO-REFRESH
CONTROLLER
SELF-REFRESH
TIMER
OE/
RFSH
22
R/W 27
5P832-2
Figure 2. LH5P832 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
R/W
OE/RFSH
I/O1 - I/O8
A0 - A7
SIGNAL
Read/Write input
Output Enable/Refresh input
Data inputs and outputs
Row address inputs
A8 - A14
CE
VCC
GND
PIN NAME
Column Address inputs
Chip Enable input
Power supply
Ground
TRUTH TABLE
CE
R/W
OE/RFSH
MODE
I/O1 - I/O 8
ICC
NOTE
L
L
L
H
H
H
L
H
H
X
X
X
X
L
H
L
L
H
Write
Read
CE-Only Refresh
Auto Refresh
Self Refresh
Standby
Data in
Data out
High-Z
High-Z
High-Z
High-Z
Operating (ICC1)
Operating (ICC1)
Operating (ICC1)
Operating (ICC1)
Self Refresh (ICC3)
Standby (ICC2)
1
NOTES:
1. X = H or L
2
2. OE Pulsewidth < 8 µs
3. OE Pulsewidth ≥ 8 µs
1, 2
1, 3
1
CMOS 256K (32K × 8) Pseudo-Static RAM
LH5P832
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Applied voltage on any pin
SYMBOL
RATING
UNIT
NOTE
VT
-1.0 to +7.0
V
1
Output short circuit current
IO
50
mA
Power dissipation
PD
600
mW
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
-55 to +150
°C
NOTE:
1. Referenced to GND
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
Supply voltage
VCC
4.5
5.0
Input voltage
VIH
VIL
2.4
-1.0
MAX.
UNIT
5.5
V
VCC + 0.3
+0.8
V
V
CAPACITANCE (VCC = 5.0 V ±10%, TA = 0 to +70°C, f = 1 MHz)
PARAMETER
Input capacitance
CONDITIONS
SYMBOL
MIN.
MAX.
UNIT
A0 - A14, R/W
CIN1
8
pF
CE, OE/RFSH
CIN2
5
pF
I/O1 - I/O8
COUT1
12
pF
Input/output capacitance
DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Operating current
ICC1
tRC = 160 ns
65
mA
1, 2
Operating current
ICC1
tRC = 190 ns
55
mA
1, 2
Standby current
ICC2
CE = VIH , OE/RFSH = V IH
3
mA
1
Self refresh average current
ICC3
CE = VIH , OE/RFSH = V IL
3
mA
1
CPU internal cycle
average current
ICC4
tRC = 160 ns
65
mA
1, 2
CPU internal cycle
average current
ICC4
tRC = 190 ns
55
mA
1, 2
Input leakage current
ILI
0 V ≤ V IN ≤ 6.5 V
-10
10
µA
Output leakage current
ILO
0 V ≤ V OUT ≤ V CC + 0.3 V
-10
10
µA
Output High voltage
VOH
IOUT = -1 mA
2.4
Output Low voltage
VOL
IOUT = 4 mA
3
V
0.4
V
NOTES:
1. Specified values are with outputs open.
2. I CC1 and ICC4 depend on the cycle time.
3. The output pins are in high-impedance state.
AC TEST CONDITIONS
PARAMETER
MODE
Input voltage amplitude
NOTE
0.6 to 2.4 V
Input rise/fall time
5 ns
Timing reference level
1.5 V
Output load conditions
1TTL gate, CL = 100 pF
1
NOTE:
1. Includes scope and jig capacitance.
3
CMOS 256K (32K × 8) Pseudo-Static RAM
LH5P832
AC CHARACTERISTICS
READ AND WRITE CYCLES 1,2 (VCC = 5.0 V ±10%, TA = 0 to 70°C)
PARAMETER
160 ns
SYMBOL
MIN.
Random read, write cycle time
190 ns
MAX.
MIN.
UNIT
NOTE
MAX.
tRC
160
tRMW
225
tCE
100
CE precharge time
tP
50
60
ns
Address setup time
tAS
0
0
ns
Address hold time
tAH
20
30
ns
Read command hold time
tRCH
0
0
ns
Read command setup time
tRCS
0
CE access time
tCEA
OE access time
tOEA
CE to output in Low-Z
tCLZ
10
10
ns
OE to output in Low-Z
tOLZ
0
0
ns
Output enable from end of write
tWLZ
0
0
ns
Chip disable to output in High-Z
tCHZ
0
30
0
35
ns
2
Output disable to output in High-Z
tOHZ
0
30
0
35
ns
2
Write enable to output in High-Z
tWHZ
0
30
0
35
ns
2
OE setup time
tOES
10
OE hold time
tOEH
OE lead time
tOEL
Write command pulse width
tWCP
Write command setup time
tWCS
Write command hold time
Data setup time from write
Read modify write cycle time
CE pulse width
190
ns
280
10,000
120
ns
10,000
0
100
40
ns
ns
120
ns
3
50
ns
3
10
ns
0
0
ns
10
10
ns
60
85
ns
60
85
ns
tWCH
60
85
ns
tDSW
40
50
ns
Data setup time from CE
tDSC
40
50
ns
Data hold time from write
tDHW
0
0
ns
Data hold time from CE
tDHC
0
tT
3
Transition time (rise and fall)
Refresh time interval
0
35
3
4
tREF
ns
35
ns
4
ms
REFRESH CYCLE
Auto refresh cycle time
tFC
160
190
ns
Refresh delay time from CE
tRFD
50
60
ns
Refresh pulse width (Auto refresh)
tFAP
60
Refresh precharge time
(Auto refresh)
tFP
30
30
ns
CE delay time from refresh active
(Auto refresh)
tFCE
190
225
ns
Refresh pulse width (Self refresh)
tFAS
8,000
8,000
ns
CE delay time from refresh
precharge (Self refresh)
tFRS
190
225
ns
NOTES:
1. At least 200 µs of pause time after power on should be given for
proper device operation.
CE and OE/RFSH must be fixed at VIH for 200 µs from the VDD
reached to the specified voltage level
and followed by at least 8 dummy cycles.
4
8,000
80
8,000
ns
2. AC characteristics are measured at tT = 5 ns.
3. Measured with a load circuit equivalent to 1TTL loads and
100 pF.
CMOS 256K (32K × 8) Pseudo-Static RAM
LH5P832
tRC
tCE
CE
VIH
VIL
tAS
V
A0 - A14 VIH
IL
tAH
ADDRESS
tOEH
RFSH
VIH
VIL
R/W
VIH
VIL
OE/
tP
tOES
tOEL
tRCS
tRCH
tCHZ
tCEA
tOEA
tOHZ
VOH
I/O1 - I/O8 VOL
DATA
OUT
tOLZ
tCLZ
5P832-3
Figure 3. Read Cycle
tRC
tCE
CE
VIH
VIL
tAS
A0 - A14
tP
VIH
VIL
tAH
ADDRESS
tOES
OE/
RFSH
VIH
VIL
tOEH
tWCH
tWCS
tWCP
V
R/W VIH
IL
tDSW
tDSC
I/O1 - I/O8
VIH
VIL
tDHW
tDHC
DATA - IN
5P832-4
Figure 4. Write Cycle
5
CMOS 256K (32K × 8) Pseudo-Static RAM
LH5P832
tRMW
tP
tCE
VIH
VIL
CE
tAS
VIH
VIL
A0 - A14
tAH
ADDRESS
tOEH
tOES
OE/ VIH
RFSH VIL
tWCS
tRCS
tWCP
VIH
VIL
R/W
tDSW
tDSC
VIH
VIL
tDHW
tDHC
DATA - IN
tCEA
I/O1 - I/O8
tWHZ
tOHZ
tOEA
VOH
VOL
tWLZ
tCHZ
DATA OUT
tOLZ
tCLZ
5P832-5
Figure 5. Read/Write Cycle
tRC
tCE
CE
tP
VIH
VIL
tAS
A0 - A7 VIH
VIL
tAH
ADDRESS
tOEH
tOES
OE/ VIH
RFSH VIL
tRCH
tRCS
V
R/W VIH
IL
I/O1 - I/O8 VOH
VOL
HIGH-Z
NOTE: A8 - A14 = Don't Care
5P832-6
Figure 6. CE Only Refresh Cycle
6
CMOS 256K (32K × 8) Pseudo-Static RAM
V
CE VIH
IL
tRFD
LH5P832
tFC
tFAP
tFCE
tFP
tFAP
OE/ VIH
RFSH VIL
HIGH-Z
I/O1 - I/O8 VOH
VOL
NOTE: A0 - A14, R/W = Don't Care
5P832-7
Figure 7. Auto Refresh Cycle
V
CE VIH
IL
tRFD
tFAS
tFRS
OE/ VIH
RFSH VIL
I/O1 - I/O8 VOH
VOL
HIGH-Z
NOTE: A0 - A14, R/W = Don't Care
5P832-8
Figure 8. Self Refresh Cycle
7
CMOS 256K (32K × 8) Pseudo-Static RAM
LH5P832
PACKAGE DIAGRAMS
28DIP (DIP028-P-0600)
28
15
DETAIL
13.45 [0.530]
12.95 [0.510]
1
0° TO 15°
14
0.30 [0.012]
0.20 [0.008]
36.30 [1.429]
35.70 [1.406]
15.24 [0.600]
TYP.
4.50 [0.177]
4.00 [0.157]
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
0.60 [0.024]
0.40 [0.016]
2.54 [0.100]
TYP.
DIMENSIONS IN MM [INCHES]
0.51 [0.020] MIN.
MAXIMUM LIMIT
MINIMUM LIMIT
28DIP-2
28-Pin, 600-mil DIP
28SK-DIP (DIP028-P-0300)
DETAIL
28
15
7.05 [0.278]
6.65 [0.262]
1
0° TO 15°
14
0.35 [0.014]
0.15 [0.006]
35.00 [1.378]
34.40 [1.354]
3.65 [0.144]
3.25 [0.128]
7.62 [0.300]
TYP.
4.40 [0.173]
4.00 [0.157]
3.40 [0.134]
3.00 [0.118]
2.54 [0.100]
TYP.
DIMENSIONS IN MM [INCHES]
0.51 [0.020] MIN.
0.56 [0.022]
0.36 [0.014]
MAXIMUM LIMIT
MINIMUM LIMIT
28DIP-1
28-Pin, 300-mil SK-DIP
8
CMOS 256K (32K × 8) Pseudo-Static RAM
LH5P832
28SOP (SOP028-P-0450)
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
1.70 [0.067]
28
15
8.80 [0.346]
8.40 [0.331]
1
12.40 [0.488]
11.60 [0.457]
10.60 [0.417]
14
1.70 [0.067]
0.20 [0.008]
0.10 [0.004]
18.20 [0.717]
17.80 [0.701]
0.15 [0.006]
1.025 [0.040]
2.40 [0.094]
2.00 [0.079]
0.20 [0.008]
0.00 [0.000]
1.025 [0.040]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28SOP
28-Pin, 450-mil SOP
ORDERING INFORMATION
LH5P832
Device Type
X
Package
- ##
Speed
10 100 Access Time (ns)
12 120
Blank 28-pin, 600-mil DIP (DIP028-P-0600)
D 28-pin, 300-mil SKDIP (SKDIP028-P-0300)
N 28-pin, 450-mil SOP (SOP028-P-0450)
CMOS 256K (32K x 8) Pseudo Static RAM
Example: LH5P832N-12 (CMOS 256K (32K x 8) Pseudo Static RAM, 120 ns, 28-pin, 450-mil SOP)
5P832-9
9