LH5PV8512 CMOS 4M (512K × 8) Pseudo-Static RAM FEATURES DESCRIPTION • 524,288 words × 8 bit organization The LH5PV8512 is a 4M bit Pseudo-Static RAM with a 524,288 word × 8 bit organization. It is fabricated using silicon-gate CMOS process technology. • CE access time (tCEA): 120 ns (MAX.) • Cycle time (tRC): 190 ns (MIN.) • Power supply: +3.0 V ± 0.15 V (Operating) +2.2 V to +3.15 V (Data retention) • Power consumption (MAX.): 126 mW (Operating) 95 µW (Standby = CMOS input level) 221 µW (Self-refresh = CMOS input level) • Available for address refresh, auto-refresh, and self-refresh modes • 2,048 refresh cycles/32 ms • Address non-multiple A PSRAM uses on-chip refresh circuitry with a DRAM memory cell for pseudo-static operation which eliminates external clock inputs, while having the same pinout as industry standard SRAMs. Moreover, due to the functional similarities between PSRAMs and SRAMs, existing 512K × 8 SRAM sockets can be filled with the LH5PV8512N with little or no changes. The advantage is the cost saving realized with the lower cost PSRAM. The LH5PV8512 has the ability to fill the gap between DRAM and SRAM by offering low cost, low power standby and simple interface. PIN CONNECTIONS 32-PIN SOP TOP VIEW A18 Vcc 1 32 A16 2 31 A15 A14 3 30 A17 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 • Package material: Plastic A5 7 26 A9 A4 8 25 • Substrate material: P-type silicon A11 A3 9 24 OE/RFSH • Not designed or rated as radiation hardened • Package: 32-pin, 525-mil SOP • Process: Silicon-gate CMOS • Operating temperature: 0 - 70°C A2 10 23 A10 A1 11 22 CE I/O7 A0 12 21 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 17 I/O3 VSS 16 5PV8512-1 Figure 1. Pin Connections 1 CMOS 4M (512K × 8) Pseudo-Static RAM LH5PV8512 16 VSS 32 VCC VBB GENERATOR A0 12 A1 11 COLUMN ADDRESS BUFFER A2 10 A3 9 A4 8 A5 7 A6 A7 A8 A9 COLUMN DECODER 6 5 27 SENSE AMPS 26 A10 23 I/O SELECTOR DATA IN BUFFER 13 I/O0 14 I/O1 15 I/O2 17 I/O3 ROW ADDRESS BUFFER A11 25 A12 4 A13 28 A14 3 A15 31 REFRESH ADDRESS COUNTER ROW DECODER EXT/INT ADDRESS MUX. DATA OUT BUFFER MEMORY ARRAY 18 I/O4 19 I/O5 20 I/O6 21 I/O7 A16 2 A17 30 A18 1 CE 22 CLOCK GENERATOR REFRESH CONTROLLER OE/ 24 RFSH REFRESH TIMER WE 29 5PV8512-2 Figure 2. LH5PV8512 Block Diagram PIN DESCRIPTION PIN NAME A0 - A18 WE OE/RFSH 2 FUNCTION Address input Write enable input Output enable input Refresh control input PIN NAME CE I/O0 - I/O7 FUNCTION Chip enable input Data input/output VCC Power supply GND Ground CMOS 4M (512K × 8) Pseudo-Static RAM LH5PV8512 TRUTH TABLE CE OE/RFSH WE I/O0 - 7 MODE L L H Output data Read L X L Input data Write L H H High-Z CE only refresh H L X High-Z Auto-refresh H H X High-Z Standby NOTES: 1. X = H or L 2. If RFSH = L, it is necessary to meet tOEH and tOCD. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING Applied voltage on all pins UNIT NOTE VT -0.5 to +4.6 V 1 Operating temperature TOPR 0 to +70 °C Storage temperature TSTG -65 to +150 °C Output short circuit current IO 50 mA Power dissipation PD 600 mW NOTE: 1. The maximum applicable voltage on any pin with respect to VSS. RECOMMENDED DC OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER Supply voltage Input voltage SYMBOL MIN. TYP. MAX. UNIT NOTE VCC 2.85 3.0 3.15 V 1 VSS 0 0 0 V VIH 2.4 4.5 V VIL -0.5 0.6 V NOTE: 1. When the supply voltage falls down under the above recommended supply voltage by temporarily power-down, a wait time longer than 400 ms is necessary at VCC = 0 V before the next power-up. After the supply voltage rises and gets stable, a pause of 100 µs with CE = RFSH = VIH and 8 dummy cycles are also necessary after the rises. PIN CAPACITANCE (TA = +25°C, f = 1 MHz, VCC = 3.0 V) PARAMETER Input capacitance Input/output capacitance CONDITIONS SYMBOL MIN. MAX. UNIT NOTE A0 - A18 CIN1 8 pF 1 WE, OE/RFSH CIN2 8 pF 1 CE CIN3 8 pF 1 I/O0 - I/O7 COUT1 10 pF 1 NOTE: 1. This parameter is sampled and not 100% tested. 3 CMOS 4M (512K × 8) Pseudo-Static RAM LH5PV8512 DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70°C, VCC = 3.0 V ± 0.15 V) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Average supply current in normal operation ICC1 tRC = 190 ns 40 mA 1 Average supply current in standby mode CE, OE, RFSH = VIH 0.5 mA ICC2 CE, OE, RFSH = V CC - 0.2 V 30 mA CE = VIH OE/RFSH = VIL 0.5 mA CE = VCC - 0.2 V, OE, RFSH = 0.2 V 70 mA Average supply current in self-refresh cycle ICC3 Input leakage current ILI 0 V ≤ VIN ≤ VCC + 0.3 V 0 V on all other pins -5 5 µA I/O leakage current ILO 0 V ≤ VOUT ≤ VCC + 0.3 V Input/output pins in High-Z -5 5 µA Output HIGH voltage VOH IOUT = -1 mA 2.4 V Output LOW voltage VOL IOUT = 2.1 mA 0.4 V NOTE: 1. The input/output pins are in high impedance state. I CC1 depends on the cycle time. 4 CMOS 4M (512K × 8) Pseudo-Static RAM LH5PV8512 AC ELECTRICAL CHARACTERISTICS 1, 2, 3, 4, 5 (TA = 0 to +70°C, VCC = 3.0 V ± 0.15 V) PARAMETER Random read, write cycle time Random modify write cycle time CE pulse width CE precharge time Address setup time Address hold time Read command setup time Read command hold time CE access time OE access time CE to output in Low-Z SYMBOL MIN. MAX. UNIT NOTES tRC 190 250 120 70 0 30 0 0 10,000 ns ns ns ns ns ns ns ns ns 6 6 30 ns ns ns ns ns 7 8 8 8 8 30 ns 8 30 ns ns ns ns ns ns ns ns ns ns ns ns ms 10, 13, 14 11, 15 11, 12, 13, 14, 15 tRMW tCE tP tAS tAH tRCS tRCH tCEA 20 0 5 tOEA tCLZ tOLZ tWLZ tCHZ tOHZ OE to output in Low-Z Write disable to output in Low-Z Chip disable to output in High-Z Output disable to output in High-Z WE to output in High-Z OE set up time from CE OE hold time from CE OE setup time from chip disable Write command pulse width Write command setup time Write command hold time tWHZ tOES tOEH tOCD tWP tWCS tWCH Data setup time from write disable Data setup time from chip disable Data hold time from write disable Data hold time from chip disable Transition time (rise and fall) tDSW tDSC tDHW tDHC tT Refresh time interval (2,048 cycle) Auto refresh cycle time tREF tFC Refresh Refresh Refresh Refresh delay time from CE pulse width (Auto refresh) precharge time (Auto refresh) pulse width (Self refresh) CE delay time from refresh precharge (Self refresh) 120 60 0 0 15 0 35 35 120 30 30 0 0 2 10,000 10,000 50 32 tRFD tFAP tFP tFAS 190 70 80 40 8 8,000 ns ns ns ns ms tFRS 600 ns 7 8 9 9 9 9 DATA RETENTION CHARACTERISTICS 12, 13, 14, 15, 16, 17, 18, 19, 20 (TA = 0 to +70°C) PARAMETER SYMBOL MIN. MAX. UNIT NOTES VR 2.2 3.15 V ICCDR 70 µA Refresh setup time tFS 0 ns Recover time from data retention mode tFR 5 ms Data retention voltage Data retention current (VCC = 3.15 V, CE = V CC - 0.2 V, OE/RFSH = 0.2 V) 5 CMOS 4M (512K × 8) Pseudo-Static RAM LH5PV8512 NOTES: 1. AC characteristics are measured at t T = 2 ns. 2. AC characteristics are measured at the following condition: INPUT VOLTAGE OUTPUT VOLTAGE VIH VIL VOH VOL Input level 2.4 V 0.4 V Input reference level 1.4 V 1.4 V 2.0 V 0.8 V Output reference level 3. In order to initialize the circuit, CE and OE/RFSH should be kept VIH for 100 µs after power-up and followed by at least 8 dummy cycles. 4. If input signals of opposite phase to the outputs are applied in write cycle, OE or WE must disable output buffer proir to applying data to the device and data inputs must be floating prior to OE or WE turning on outputs buffer. 5. Because a PSRAM operates dynamically like a DRAM, it is recommended to put bypass capacitors between VCC and GND to absorb power supply noise due to the peak current. 6. Address signals are latched in the memory at the falling edge of CE. 7. Measured with a load equivalent to 50 pF. 8. t CLZ, tOLZ , tWLZ , t CHZ, tOHZ , and tWHZ are sampled, and not 100% tested. tCHZ, tOHZ, and tWHZ define the time at which the output achieves the open circuit condition and they are not referenced to output voltage levels. 9. Input data is latched in the memory at the earlier rising edge of CE and WE. 10. CE only refresh or auto-refresh is needed to be executed 2,048 times within 32 ms. 11. Auto-refresh and self-refresh are defined by OE/RFSH pulse width during CE = VIH. If OE/RFSH pulse width is shorter than t FAP (MAX.), the cycle is an auto-refresh cycle and memory cells are refreshed by an internal address counter. If OE/RFSH pulse width is longer than t FAS (MIN.), the cycle is a self-refresh cycle and memory cells are refreshed by an internal clock generator automatically. 12. If CE only refresh is used during normal read/write cycles, the first address refresh must be started within 15 µs after self-refresh or data retention mode ends, and the CE only refresh must be executed continuously for 2,048 refresh cycles. 13. If distributed auto-refresh is used during normal read/write cycles, the first auto-refresh must be started within 15 µs after self-refresh or data retention mode ends. 14. If burst auto-refresh is used during normal read/write cycles, the first auto-refresh must be started within 15 µs after self-refresh or data retention mode ends, and the auto-refresh must be executed continuously for 2,048 refresh cycles. 15. After 8,000 ns (t FAP (MAX.)) from RFSH falling, the memory resets its internal address counter and enters self-refresh cycle. At the beginning of the self-refresh cycle, it takes longer than 8 ms (t FAS (MIN.)) for all addresses to be refreshed. Therefore, in case that the RFSH = L pulse length is from 8,000 ns to 8 ms, refresh all addresses by external clocks within 32 ms before the self-refresh to keep refresh time interval (t REF ). 16. After self-refresh cycle or data retention mode ends, t FRS (MIN.) is necessary to reset the refresh operation. CE and OE/RFSH should kept VIH for t FRS (MIN.). 17. The data retention period is longer than tFAS (MIN.) like self-refresh cycle. 18. OE/RFSH must be lower than 0.2 V during the data retention period. 19. CE must be higher than VCC - 0.2 V during the data retention period. 20. The transition time of the supply voltage in data retention mode must be slower than 0.05 V/ms. 6 CMOS 4M (512K × 8) Pseudo-Static RAM LH5PV8512 tRC tCE tP CE tAS tAH ADDRESS INPUT A0 - A18 tOES tOEH tOES OE/ RFSH tRCS tRCH WE tOEA tCEA tOLZ tCHZ tCLZ I/O1 - I/O8 tOHZ VALID-DATA OUTPUT 5PV8512-3 Figure 3. Read Cycle 7 CMOS 4M (512K × 8) Pseudo-Static RAM LH5PV8512 tRC tCE tP CE tAS A1 - A18 tAH ADDRESS INPUT tOCD OE/ RFSH tWCH tWCS tWP WE tDSW tWHZ I/O1 - I/O8 tDHW tDSC tDHC DATA INPUT 5PV8512-4 Figure 4. Write Cycle 8 CMOS 4M (512K × 8) Pseudo-Static RAM LH5PV8512 tRMW tCE tP CE tAS tAH ADDRESS INPUT A0 - A18 tOEH tOCD tOES OE/ RFSH tRCS tWCS tWP WE tDSW tDHW tDSC tDHC DATA INPUT tCEA I/O1 - I/O8 tOEA tWHZ tOHZ DATA OUTPUT tOLZ tCLZ 5PV8512-5 Figure 5. Read/Write Cycle 9 CMOS 4M (512K × 8) Pseudo-Static RAM LH5PV8512 tRC tCE tP CE tAS A0 - A10 tAH ADDRESS INPUT tOES tOEH OE/ RFSH tRCS tRCH WE OPEN I/O1 - I/O8 NOTE: A11 - A18 = Don't Care 5PV8512-6 Figure 6. CE Only Refresh Cycle CE tRFD tFP tFC tFAP tFC tFP tFAP OE/ RFSH I/O1 - I/O8 OPEN NOTE: A0 - A18, WE = Don't Care 5PV8512-7 Figure 7. Auto-Refresh Cycle 10 CMOS 4M (512K × 8) Pseudo-Static RAM LH5PV8512 CE tRFD tFP tFAS tFRS OE/ RFSH OPEN I/O1 - I/O8 NOTE: A0 - A18, WE: Don't Care 5PV8512-8 Figure 8. Self-Refresh Cycle DATA RETENTION MODE VCC VCC 2.85 V VR tFAS tFP tFRS tFS tFR OE/RFSH ≤ 0.2 V OE/RFSH tRFD CE 1.5 V CE ≥ VCC - 0.2 V NOTE: A0 - A18, WE = Don't Care 5PV8512-9 Figure 9. Data Retention Mode 11 CMOS 4M (512K × 8) Pseudo-Static RAM LH5PV8512 PACKAGE DIAGRAM 32SOP (SOP32-P-525) 0.15 [0.006] M 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 1.40 [0.055] 32 17 11.50 [0.453] 14.50 [0.571] 11.10 [0.437] 13.70 [0.539] 1 16 12.50 [0.492] SEE DETAIL 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 20.80 [0.819] 20.40 [0.803] 0.15 [0.006] 2.90 [0.114] 2.50 [0.098] 0.10 [0.004] DIMENSIONS IN MM [INCHES] DETAIL 1.27 [0.050] 1.275 [0.050] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0 - 10° 2.00 [0.079] 0.00 [0.000] 0.80 [0.031] MAXIMUM LIMIT MINIMUM LIMIT 32SOP-2 ORDERING INFORMATION LH5PV8512 Device Type N Package - ## Speed 12 120 Access Time (ns) 32-pin, 525-mil SOP (SOP32-P-525) CMOS 4M (512K x 16) Pseudo-Static RAM Example: LH5PV8512N-12 (CMOS 4M (512K x 16) Pseudo-Static RAM, 120 ns, 32-pin, 525-mil SOP) 5PV8512-10 12