LH5PV16256 CMOS 4M (256K × 16) Pseudo-Static RAM FEATURES DESCRIPTION • 262,144 words × 16 bit organization The LH5PV16256 is a 4M bit Pseudo-Static RAM with a 262,144 words × 16 bit organization. • Power supply: +3.0 ± 0.15 V • Access time: 120 ns (MAX.) • Cycle time: 190 ns (MIN.) • Power consumption (MAX.): 126 mW (Operating) 94.5 µW (Standby = CMOS input level) 220.5 µW (Self-refresh = CMOS input level) PIN CONNECTIONS 44-PIN TSOP (Type II) TOP VIEW LWE 1 44 GND UWE 2 43 I/O15 A0 3 42 I/O14 A1 4 41 I/O13 A2 5 40 I/O12 A3 6 39 I/O11 A4 7 38 I/O10 A5 8 37 I/O9 A6 9 36 I/O8 A17 10 35 VCC CS 11 34 VCC A16 12 33 RFSH A15 13 32 I/O7 A14 14 31 I/O6 A13 15 30 I/O5 A12 16 29 I/O4 A11 17 28 I/O3 A10 18 27 I/O2 • Process: Silicon-gate CMOS A9 19 26 I/O1 20 25 • Operating temperature: 0 - 70°C A8 I/O0 A7 21 24 OE CE 22 23 GND • LVTTL compatible I/O • Available for address refresh, auto-refresh, and self-refresh modes • 2,048 refresh cycles/32 ms • Address non-multiple • Available for byte write mode using UWE and LWE pins • Package: 44-pin, TSOP (Type II) • Not designed or rated as radiation hardened 5PV16256S-1 Figure 1. Pin Connections 1 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 23 GND 44 GND UWE 2 LWE 1 35 VCC 34 VCC A7 21 A8 20 VBB GENERATOR A9 19 A10 18 A11 17 A 0 COLUMN A12 16 A6 ADDRESS 15 A13 BUFFER A14 14 A15 13 A16 12 25 I/O0 COLUMN DECODER 26 I/O1 27 I/O2 28 I/O3 SENSE AMPS I/O SELECTOR DATA IN BUFFER 32 I/O7 36 I/O8 A17 10 ROW A6 9 ADDRESS A5 8 A7 - BUFFER A4 7 A17 A3 6 REFRESH A2 5 ADDRESS COUNTER A1 4 29 I/O4 30 I/O5 31 I/O6 EXT/INT ADDRESS MUX. ROW DECODER MEMORY ARRAY 8M DATA OUT BUFFER A0 3 37 I/O9 38 I/O10 39 I/O11 40 I/O12 41 I/O13 42 I/O14 43 I/O15 CS 11 CE 22 CLOCK GENERATOR REFRESH CONTROLLER REFRESH TIMER RFSH 33 OE 24 5PV16256S-2 Figure 2. LH5PV16256 Block Diagram PIN DESCRIPTION PIN NAME PIN NAME Row address input A0 - A6 Column address input I/O8 - I/O15 Upper byte data input/output Upper/lower write enable input I/O0 - I/O7 Lower byte data input/output OE RFSH CE CS FUNCTION A7 - A17 UWE, LWE 2 FUNCTION Chip select input Output enable input VCC Power supply Refresh input GND Ground Chip enable input CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 TRUTH TABLE CE CS RFSH OE UWE LWE MODE I/O0 - 7 L H H L H H Word Read Output data H L L H L L H H X I/O8 - 15 Output data Lower byte write Input data Don’t care Upper byte write Don’t care Input data L Word write Input data Input data H H Invalid High-Z High-Z Write H X L X X X Auto refresh High-Z High-Z L L H X X X CS standby High-Z High-Z H X H X X X Standby High-Z High-Z NOTES: H = High L = Low X = Don’t care REQUIREMENTS 2WE control Please do not separate the UWE and LWE operation timing intentionally in the same write cycles. Each of the UWE/LWE should satisfy the timing specifications individually. Refresh after self-refresh or data retention mode • If address refresh is used during normal read/write cycles, the first address refresh must be executed within 15 µs after self-refresh or data retention mode ends and the address refresh must be executed continuously for 2,048 refresh cycles. • If distributed auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within 15 µs after self-refresh or data retention mode ends. • If burst auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within 15 µs after self-refresh or data retention mode ends, and the auto-refresh must be executed continuously for 2,048 refresh cycles. Bypass capacitor for power supply noise reduction Because a PSRAM operates dynamically like a DRAM, it is recommended to put bypass capacitors between V CC and GND to absorb power supply noise due to the peak current. 3 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Supply voltage VT -0.5 to +4.6 V 1 Output short circuit current IO 50 mA Power dissipation PD 600 mW Operating temperature TOPR 0 to +70 °C Storage temperature TSTG -65 to +150 °C NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER Supply voltage Input voltage SYMBOL MIN. TYP. MAX. UNIT NOTE VCC 2.85 3.0 3.15 V 1 GND 0 0 0 V 1 VIH 2.0 VCC + 0.3 V VIL -0.3 0.8 V NOTE: 1. The supply voltage with all VCC pins must be on the same level. The supply voltage with all GND pins must be on the same level. PIN CAPACITANCE (TA = 0 to +70°C, f = 1 MHz, VCC = 3.0 V ± 0.15 V) PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT A0 - A17 CIN1 8 pF Input capacitance UWE, LWE OE, RFSH CIN2 8 pF CE, CS CIN3 8 pF Input/output capacitance I/O0 - I/O15 COUT1 10 pF DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70°C, VCC = 3.0 V ± 0.15 V) PARAMETER Operating current in normal operation Standby current Self-refresh average current SYMBOL ICC1 ICC2 ICC3 MIN. MAX. UNIT NOTE tRC = tRC (MIN.) 40 mA 1, 2 CE, RFSH = VIH (MIN.) 1 mA 1 CE, RFSH = VCC - 0.2 V 30 mA 1 CE = VIH (MIN.) RFSH = VIL (MAX.) 1 mA 1 CE = VCC - 0.2 V, RFSH = 0.2 V 70 mA 1 Input leakage current ILI 0 V ≤ VIN ≤ 6.5 V 0 V on all other pins -10 10 µA Output leakage current ILO 0 V ≤ VOUT ≤ V CC + 0.3 V Input/output pins in High-Z state -10 10 µA Output HIGH voltage VOH IOUT = -1 mA 2.4 V IOUT = -100 µA VCC - 0.2 V IOUT = 1 mA 0.4 V Output LOW voltage VOL Data retention voltage VR NOTES: 1. The input/output pins are in high impedance state. 2. I CC1 depends on the cycle time. 4 CONDITIONS IOUT = 100 µA 0.2 V 2.2 3.15 V CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 AC ELECTRICAL CHARACTERISTICS 1,2,7 (TA = 0 to +70°C, VCC = 3.0 V ± 0.15 V) PARAMETER Random read, write cycle time Random modify write cycle time CE pulse width CE precharge time Address setup time Row address hold time from CE Column address hold time from CE CS setup time from CE CS hold time from CE Read command setup time Read command hold time CE access time OE access time CE to output in Low-Z OE to output in Low-Z Write disable to output in Low-Z Chip disable to output in High-Z SYMBOL MIN. MAX. UNIT NOTES tRC 190 250 120 60 0 30 120 0 30 0 0 20 0 10,000 120 60 ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 11 9 4 4 ns ns 0 0 0 0 35 35 120 30 30 0 30 0 20 0 3 0 15 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 11 tRMW tCE tP tAS tRAH tCAH tCSS tCSH tRCS tRCH tCEA tOEA tCLZ tOLZ tWLZ tCHZ Output disable to output in High-Z WE to output in High-Z Write command pulse width Write command setup time Write command hold time tWHZ tWCP tWCS tWCH Data setup time from write disable Data setup time from chip disable Data hold time from write disable tDSW tDSC tDHW Data hold time from chip disable Data hold time from column address Column address hold time from chip disable Column address hold time from write disable Transition time (rise and fall) Output disable setup time tDHC tOH tAHC tAHW tT tODS Output disable hold time Refresh time interval (2048 cycle) Auto refresh cycle time tODH tREF tFC Refresh delay time from CE Refresh pulse width (Auto refresh) Refresh precharge time (Auto refresh) CE delay time from refresh enable (Auto refresh) Refresh pulse width (Self refresh) CE delay time from refresh precharge (Self refresh) VCC recovery time from data retention Refresh setup hold time Refresh disable hold time Chip disable delay time from RFSH tOHZ 10,000 10,000 50 32 tRFD tFAP tFP 190 90 80 40 1,000 tFCE 9, 13 13 10, 13 12, 13 5, 12, 13 5 5, 11, 13 5 5 5, 13 6 6 8 ns ns ns ns 190 ns tFAS 8,000 ns 8 tFRS 600 ns tR tFS 5 0 15 15 ms ns ns ns tRDH tRDD 5 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 NOTES: 1. AC characteristics are measured at t T = 5 ns. 2. AC characteristics are measured at the following condition: 3. Row address signals are latched in the memory at the falling edge of CE. INPUT OUTPUT 2.4 V 2.2 V 0.8 V 0.4 V 2.0 V 0.8 V 5PV16256S-13 Figure 3. AC Characteristics 4. Measured with a load equivalent to 50 pF. 5. Input data is latched in the memory at the earlier rising edge of CE and UWE/LWE. One of (t AHW , tDSW, tDHW ) and (tAHC, tDSC, tDHC) needs to be satisfied. The other is "Don’t care." 6. Address refresh or auto refresh is needed to be executed 2,048 times within 32 ms. 7. In order to initialize the internal circuits, an initial pause of 500 µs with CE = RFSH = VIH is required after power-up, and followed by at least 8 dummy cycles. When supply voltage falls down below the recommended supply voltage by temporarily power-down, a waiting time is required at VCC = 0 V for more than 400 ms before power-up, and a pause of 500 µs with CE = RFSH = VIH and 8 dummy cycles are also necessary after power-up. 8. Auto refresh and self refresh are defined by RFSH pulse width during CE = VIH. If RFSH pulse width is shorter than tFAP (MAX.), the cycle is an auto refresh cycle and memory cells are refreshed by an internal counter. If RFSH pulse width is longer than t FAS (MIN.), the cycle is a self refresh cycle and memory cells are refreshed by an internal clock generator automatically. 9. t RCH and tWHZ are determined by the earlier falling edge of UWE and LWE. 10. t WCS is determined by the later falling edge of UWE and LWE. 11. t RCS, tWLZ, and t DHW are determined by the later rising edge of UWE and LWE. 12. t WCH and tDSW are determined by the earlier rising edge of UWE and LWE. 13. t WHZ, tWCP, tWCS, tWCH, tDSW, tDHW, tWLZ, and t AHW should be satisfied by both UWE and LWE. 14. The transition time of the supply voltage in data retention mode is less than 0.05 V/ms. 15. The width of data retention period is more than tFAS (MIN.) like self-refresh cycle. 16. All input pins are required to be higher than -0.3 V. 17. RFSH must be lower than 0.2 V during the data retention period. 18. CE and CS must be higher than VCC - 0.2 V during the data retention period. 6 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 tRC tP CE tCE VIH VIL tCSS CS tP tCSH VIH VIL tRDH RFSH VIH VIL tAS A7 - A17 VIH VIL tRAH ROW ADDRESS INPUT tAS A0 - A6 VIH VIL OE tCAH COLUMN ADDRESS INPUT VIH VIL tRCS tRCH UWE, LWE VIH VIL tCEA tCHZ tOEA I/O0 - I/O15 VOH VOL tOH tOHZ VALID-DATA OUTPUT tOLZ tCLZ 5PV16256S-3 Figure 4. Read Cycle 7 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 tRC tP CE tCE VIH VIL tCSS CS tP tCSH VIH VIL tRDD tRDH RFSH VIH VIL tAS A7 - A17 VIH VIL tRAH ROW ADDRESS INPUT tAS tCAH A0 - A6 VIH VIL COLUMN ADDRESS INPUT tAHW OE VIH VIL tWCH tWCS tWCP UWE, LWE VIH VIL tDSW VIH VIL tDHW VALID-DATA INPUT tWHZ I/O0 - I/O15 tCLZ tOHZ tOLZ tCHZ tWLZ VOH VOL 5PV16256S-4 Figure 5. Write Cycle (1) (OE Clock) 8 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 tRC tP CE tCE tP VIH VIL CS VIH VIL RFSH VIH VIL A7 - A17 VIH VIL tCSS tCSH tAS tRAH ROW ADDRESS INPUT tAS tCAH A0 - A6 VIH VIL COLUMN ADDRESS INPUT tAHC V OE IH VIL tWCS UWE, LWE VIH VIL tDSC VIH VIL VALID-DATA INPUT tCLZ I/O0 - I/O15 tDHC tWHZ VOH VOL 5PV16256S-5 Figure 6. Write Cycle (2) (OE = Low , CE Control) 9 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 tRMW tP CE tCE VIH VIL tCSS CS tP tCSH VIH VIL tRDH RFSH VIH VIL tAS A7 - A17 VIH VIL tRAH ROW ADDRESS INPUT tAS tCAH A0 - A6 VIH VIL COLUMN ADDRESS INPUT tAHC tAHW OE VIH VIL tRCS tWCS tWCP UWE, LWE VIH VIL tDSW tDHW tDSC VIH VIL tDHC VALID-DATA INPUT tCEA I/O0 - I/O15 tOEA VOH VOL tWHZ tOHZ VALID-DATA OUTPUT tOLZ tCLZ 5PV16256S-6 Figure 7. Read-Modify-Write Cycle 10 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 tRC tP CE VIH VIL tCSS CS tP tCE tCSH VIH VIL tRDH RFSH VIH VIL A7 - A17 VIH VIL tAS tRAH ROW ADDRESS INPUT tODS OE tODH VIH VIL tRCS UWE, LWE VIH VIL I/O0 - I/O15 VOH VOL tRCH OPEN NOTE: A0 - A6 = Don't Care 5PV16256S-7 Figure 8. Address Refresh Cycle 11 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 CE VIH VIL tCSS CS tCSH VIH VIL tRFD tFC tFP RFSH VIH VIL I/O0 - I/O15 VOH VOL tFAP tFCE tFP tFAP OPEN NOTE: A0 - A17, UWE, LWE and OE = Don't Care 5PV16256S-8 Figure 9. Auto Refresh Cycle CE VIH VIL CS VIH VIL tRFD tFC tFP RFSH VIH VIL I/O0 - I/O15 VOH VOL tFAS tFRS OPEN NOTE: A0 - A17, UWE, LWE and OE = Don't Care Figure 10. Self Refresh Cycle 12 5PV16256S-9 CMOS 4M (256 × 16) Pseudo-Static RAM VCC LH5PV16256 3.0 V VR tR tFS tRFD tFP RFSH VIH VIL CE VIH VIL CS VIH VIL DATA RETENTION PERIOD tFRS RFSH ≤ 0.2 V CE ≥ VCC -0.2 V CS ≥ VCC -0.2 V NOTE: Ao - A17, UWE, LWE and OE = Don't Care 5PV16256S-10 Figure 11. Data Retention Mode tRC tP CE tCE VIH VIL tCSS CS tP tCSH VIH VIL tRFD RFSH VIH VIL I/O0 - I/O15 VOH VOL OPEN NOTE: A0 - A17, UWE, LWE and OE = Don't Care 5PV16256S-11 Figure 12. CS Standby Mode 13 CMOS 4M (256 × 16) Pseudo-Static RAM LH5PV16256 PACKAGE DIAGRAM 44TSOP (Type II) (TSOP44-P-400) 0.38 [0.015] 0.22 [0.009] 0.80 [0.031] TYP. 0.15 [0.006] M 44 23 10.40 [0.409] 10.00 [0.394] 1 12.10 [0.476] 11.50 [0.453] 11.00 [0.433] 10.60 [0.417] 22 18.60 [0.732] 18.20 [0.716] 0.125 [0.005] 0.12 [0.005] 1.10 [0.043] 0.90 [0.035] DETAIL 1.20 [0.047] MAX. 1.10 [0.043] 0.90 [0.035] 0.10 [0.004] DIMENSIONS IN MM [INCHES] 0.15 [0.006] 0.05 [0.002] MAXIMUM LIMIT MINIMUM LIMIT 0.15 [0.006] 0.05 [0.002] 0 - 10° 44TSOP ORDERING INFORMATION LH5PV16256 Device Type S Package - ## Speed 12 120 Access Time (ns) 44-pin, 400-mil TSOP (Type II) (TSOP44-P-400) CMOS 4M (256K x 16) Pseudo-Static RAM Example: LH5PV16256S-12 (CMOS 4M (256K x 16) Pseudo-Static RAM, 120 ns, 44-pin, 400-mil TSOP) 5PV16256S-12 14