LH5P864 FEATURES • 65,536 × 8 bit organization CMOS 512K (64K × 8) Pseudo-Static RAM PIN CONNECTIONS TOP VIEW 32-PIN SOP • Access time: 80 ns (MAX.) • Cycle time: 140 ns (MIN.) • Single +5 V power supply • Power consumption: Operating: 440 mW (MAX.) Standby (TTL level): 22 mW (MAX.) Standby (CMOS level): 2.75 mW (MAX.) • Operating temperature: 0 to 70°C • TTL compatible I/O • 512 refresh cycles/8 ms (MAX.) • Available for auto-refresh and self-refresh modes • Package: 32-pin, 525-mil SOP TEST 1 32 VCC NC 2 31 NC A14 3 30 CE2 A12 4 29 R/W A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE/RFSH A2 10 23 A10 A1 11 22 CE1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 5P864-1 Figure 1. Pin Connections for SOP Package DESCRIPTION The LH5P864 is a 512K-bit Pseudo-Static RAM organized as 65,536 × 8 bits. It is fabricated using silicon-gate CMOS process technology. With its built-in oscillator, it is easy to refresh memories without an external clock. 1 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P864 16 GND 32 VCC A0 12 A1 11 A2 10 A3 9 VBB GENERATOR A8 - A14 A4 8 A5 7 A6 A7 A8 A9 COLUMN ADDRESS BUFFER COLUMN DECODER 6 5 27 26 A10 23 A0 - A7 SENSE AMPS ROW ADDRESS BUFFER A11 25 A12 4 A13 28 A14 3 REFRESH ADDRESS COUNTER CE1 22 CE2 30 CLOCK GENERATOR EXT/INT ADDRESS MUX ROW DECODER REFRESH CONTROLLER TEST1 1 I/O SELECTOR DATA IN BUFFER 17 I/O3 18 I/O4 MEMORY ARRAY 256K MEMORY ARRAY 256K 13 I/O0 14 I/O1 15 I/O2 19 I/O5 20 I/O6 DATA OUT BUFFER 21 I/O7 REFRESH TIMER OE/ 24 RFSH R/W 29 5P864-2 Figure 2. LH5P864 Block Diagram PIN DESCRIPTION SIGNAL A0 - A14 R/W OE/RFSH CE1, CE2 I/O0 - I/O7 2 PIN NAME Address input Read/Write Enable input Output Enable input/Refresh input Chip Enable input Data input/output SIGNAL VCC GND Test NC PIN NAME Power Supply Ground Test Input No Connection CMOS 512K (64K × 8) Pseudo-Static RAM LH5P864 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE 1 Applied voltage on any pin VT -1.0 to +7.0 V Output short circuit current IO 50 mA Power dissipation PD 600 mW Operating temperature Topr 0 to +70 °C Storage temperature Tstg -65 to +150 °C NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V VIH 2.4 VCC + 0.3 V VIL -1.0 0.8 V Supply voltage Input voltage CAPACITANCE (TA = 0 to +70°C, f = 1MHz, VCC = 5.0 V ±10%) PARAMETER Input capacitance CONDITIONS MIN. MAX. UNIT A0 - A14 CIN1 8 pF R/W, OE/RFSH CIN2 8 pF CE1, CE 2 CIN3 8 pF CIN4 10 pF COUT1 10 pF TEST1 Input/Output capacitance SYMBOL I/O0 - I/O7 DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5.0 V ±10%) PARAMETER SYMBOL Operating current ICC1 Standby current ICC2 Self refresh average current ICC3 CONDITIONS MIN. MAX. UNIT NOTE tRC = t RC (MIN.) 80 mA 1, 2 TTL input 4.0 mA 1, 3, 5 CMOS input 0.5 mA 1, 3, 6 TTL input 4.0 mA 1, 4, 5 CMOS input 0.5 mA 1, 4, 6 Input leakage current ILI 0 V ≤ V IN ≤ 6.5 V, 0 V except on test pins -10 10 µA Output leakage current ILO 0 V ≤ V OUT ≤ V CC + 0.3 V, Outputs in High-Z state -10 10 µA Output HIGH voltage VOH IOUT = -1.0 mA 2.4 Output LOW voltage VOL IOUT = 4.0 mA V 0.4 V NOTES: 1. Specified values are with outputs open. 2. I CC1 depends on the cycle time. 3. CE1 = CE2 = VIH, OE/RFSH = VIH 4. CE1 = CE2 = VIH, OE/RFSH = VIL 5. CE1 = CE2 = VCC – 0.2 V, OE/RFSH = VCC – 0.2 V 6. CE1 = CE2 = VCC – 0.2 V, OE/RFSH = 0.2 V 3 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P864 AC CHARACTERISTICS 1,2,3 (TA = 0 to +70°C, VCC = 5.0 V ±10%) PARAMETER SYMBOL MIN. Random read, write cycle time MAX. UNIT NOTE tRC 140 ns tRMW 205 ns CE pulse width tCE 80 CE precharge time tP 50 Address setup time tAS 0 ns 4 Address hold time tAH 20 ns 4 Read modify write cycle time 10,000 ns ns Read command setup time tRCS 0 ns Read command hold time tRCH 0 ns CE access time tCEA 80 ns 5 OE access time tOEA 30 ns 5 CE to output in Low-Z tCLZ 20 ns OE to output in Low-Z tOLZ 0 ns R/W to output in Low-Z tWLZ 0 Chip disable to output in High-Z tCHZ 25 ns Output disable to output in High-Z tOHZ 25 ns Write enable to output in High-Z tWHZ 25 ns ns OE setup time tOES 10 ns OE hold time tOEH 10 ns OE lead time tOEL 10 ns Write command pulse width tWCP 30 ns Write command setup time tWCS 30 ns Write command hold time tWCH 50 ns Data setup time from write tDSW 30 ns 6 Data setup time from CE tDSC 30 ns 6 Data hold time from write tDHW 0 ns 6 Data hold time from CE tDHC 0 ns 6 tT 3 Transition time (rise and fall) Refresh time interval tREF 35 ns 8 ms Auto refresh cycle time tFC 130 ns Refresh delay time from CE tRFD 50 ns Refresh pulse width (Auto refresh) tFAP 30 Refresh precharge time (Auto refresh) tFP 30 ns CE delay time from refresh precharge (Auto refresh) tFCE 160 ns Refresh pulse width (Self refresh) tFAS 8,000 ns CE delay time from refresh precharge (Self refresh) tFRS 160 ns NOTES: 1. In order to initialize the circuit, CE1, CE2 and OE/RFSH should be kept in VIH for 100 µs after power-up and followed by at least 8 dummy cycles. 2. AC characteristics are measured at t T = 5 ns. 3. AC characteristics are measured at the following condition (see figure at right). 4. Address is latched at the negative edge of CE1 or CE2. 5. Measured with a load equivalent to 2TTL + 100 pF. 6. Data is latched at the positive edge of R/W or at the positive edge of CE1 or CE2. INPUT OUTPUT 8,000 ns 2.6 V 2.4 V 0.8 V 0.6 V 2.2 V 0.8 V 5P864-3 Figure 3. AC Characteristics 4 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P864 tRC tCE tP tP VIH CE1 (OR CE2) VIL VIH CE2 (OR CE1) VIL tAS A0 - A14 VIH VIL tAH ADDRESS INPUT tOEH tOEL tOES V OE/RFSH VIH IL tRCH tRCS VIH R/W VIL tCHZ tOEA tOHZ tCEA tOLZ tCLZ V I/O0 - I/O7 VOH OL VALID-DATA OUTPUT 5P864-4 Figure 4. Read Cycle 5 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P864 tRC tCE tP tP VIH CE1 (OR CE2) VIL VIH CE2 (OR CE1) VIL tAS A0 - A14 VIH VIL tAH ADDRESS INPUT tOEH tOES V OE/RFSH VIH IL tWCH tWCS tWCP VIH R/W VIL tDSW tDSC V I/O0 - I/O7 VIH IL tDHW tDHC VALID-DATA INPUT 5P864-5 Figure 5. Write Cycle 6 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P864 tRMW tP tP VIH CE1 (OR CE2) VIL VIH CE2 (OR CE1) VIL A0 - A14 VIH VIL tAS tAH ADDRESS INPUT tOEH tOES V OE/RFSH VIH IL tWCS tRCS tWCP VIH R/W VIL tDSW tDHW tDSC VIH VIL tDHC VALID-DATA INPUT tCEA tOEA I/O0 - I/O7 tOLZ tCLZ VOH VOL tWHZ tOHZ tWLZ tCHZ VALID-DATA OUTPUT 5P864-6 Figure 6. Read-Modify-Write Cycle 7 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P864 tRC tCE tP tP VIH CE1 (OR CE2) VIL VIH CE2 (OR CE1) VIL tAS A0 - A7 VIH VIL tAH ADDRESS INPUT tOEH tOES OE/RFSH VIH VIL tRCH tRCS R/W VIH VIL V I/O0 - I/O7 VOH OL HIGH-Z NOTE: A8 - A14 Don't Care 5P864-7 Figure 7. CE Only Refresh Cycle VIH CE1 VIL V CE2 VIH IL tRFD tFC tFAP tFCE tFP tFAP V OE/RFSH VIH IL V I/O0 - I/O7 VOH OL HIGH-Z NOTE: A0 - A14, R/W Don't Care 5P864-8 Figure 8. Auto Refresh Cycle 8 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P864 VIH CE1 VIL V CE2 VIH IL tRFD tFAS tFRS V OE/RFSH VIH IL V I/O0 - I/O7 VOH OL HIGH-Z NOTE: A0 - A14, R/W Don't Care 5P864-9 Figure 9. Self Refresh Cycle PACKAGE DIAGRAM 32SOP (SOP032-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 32 17 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 20.80 [0.819] 20.40 [0.803] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32SOP 32-pin, 525-mil SOP 9 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P864 ORDERING INFORMATION LH5P864 Device Type N Package - ## Speed 80 Access Time (ns) 32-pin, 525-mil SOP (SOP032-P-0525) CMOS 512K (64K x 8) Pseudo-Static RAM Example: LH5P864N-80 (CMOS 512K (64K x 8) Pseudo-Static RAM, 80 ns, 32-pin, 525-mil SOP) 5P864-10 10