Ordering number : EN4430C CMOS LSI LC33832P, S, M, PL, SL, ML-70/80/10 256 K (32768 words × 8 bits) Pseudo-SRAM Overview Package Dimensions The LC33832 series is composed of pseudo static RAM that operates on a single 5 V power supply and is organized as 32768 words × 8 bits. By using memory cells each composed of a single transistor and capacitor, together with peripheral CMOS circuitry, this series achieves ease of use with high density, high speed, and low power dissipation. The LC33832 series can easily accomplish auto-refresh and self-refresh by means of OE/RFSH input. As with asynchronous static RAM, WE input uses a system for incorporating input data at the WE rise, thereby facilitating interfacing with a microcomputer. unit: mm 3012A-DIP28 [LC33832P, PL] The LC33832 series features pin compatibility with 256 K static RAM (the LC36256A series), and available packages are the standard 28-pin DIP with widths of 600 mil or 300 mil, and the SOP with a width of 450 mil. SANYO: DIP28 CE-only refresh can be accomplished by selecting address 256 (A0 to A7) within 4 ms. unit: mm Features • • • • • • • • 32768 words × 8 bits configuration Single 5 V ±10% power supply All input and output (I/O) TTL compatible Fast access times and low power dissipation 4 ms refresh using 256 refresh cycle CE-only refresh, auto-refresh, and self-refresh Low-power version: 100 µA self-refresh current Package DIP28-pin (600 mil) plastic package: LC33832P, PL DIP28-pin (300 mil) plastic package: LC33832S, SL SOP28-pin (450 mil) plastic package: LC33832M, ML 3133-DIP28 [LC33832S, SL] SANYO: DIP28 • CE access time/OE access time/Cycle time/Current drain Parameter CE access time LC33832P, S, M, PL, SL, ML -70 -80 -10 70 ns 80 ns 100 ns OE access time 30 ns 35 ns 40 ns Cycle time 115 ns 130 ns 160 ns 60 mA 50 mA Current drain Operating Standby 65 mA 1 mA/100 µA (L version) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 22897HA (OT)/52595TH (OT)/N1993JN/40893JN A8-9957, 58, 59, No. 4430-1/9 LC33832P, S, M, PL, SL, ML-70/80/10 unit : mm 3158-SOP28 [LC33832M, ML] SANYO: SOP28 Block Diagram No. 4430-2/9 LC33832P, S, M, PL, SL, ML-70/80/10 Pin Assignment Pin Functions A0 to A14 WE OE/RFSH Address input Read/Write input Output-enable input/ refresh input CE Chip-enable input I/O1 to I/O8 Data input/output VCC Power supply GND Ground Functional Logic CE OE /RFSH WE A0 to A7 A8 to A14 I/O1 to I/O8 State H H X X X HZ L L H VX VX OUT Read Standby L H L VX VX IN Write L H H VX X HZ CE-only refresh H L X X X HZ Self-refresh H NP X X X HZ Auto-refresh H ...................High-level input of VIN = 6.5 V to VIH (min) L ....................Low-level input of VIN = VIL (max) to –1.0 V X....................High- or low-level input NP.................Negative-polarity pulse input VX.................“IN” when CE = L is confirmed, then “X” HZ.................High impedance IN ..................Input state OUT..............Output state No. 4430-3/9 LC33832P, S, M, PL, SL, ML-70/80/10 Specifications Absolute Maximum Ratings Symbol Ratings Unit Note Maximum supply voltage Parameter VCC max –1.0 to +7.0 V 1 Input voltage VIN –1.0 to +7.0 V 1 Output voltage VOUT –1.0 to +7.0 V 1 Allowable power dissipation Pd max 600 mW 1 Output short-circuit current IOUT 50 mA 1 Operating temperature Topr 0 to +70 °C 1 Storage temperature Tstg –55 to +150 °C 1 Note: 1) Stresses greater than the above listed maximum values may result in damage to the device. DC Recommended Operating Ranges at Ta = 0 to +70°C Parameter Symbol min typ max Unit Note Supply voltage VCC 4.5 5.0 5.5 V 2 Input high level voltage VIH 2.4 6.5 V 2 Input low level voltage VIL –1.0 +0.8 V 2 Note: 2) All voltages are referenced to GND. DC Electrical Characteristics at Ta = 0 to +70°C, VCC = 5V±10% Parameter Operating current Symbol ICCA Conditions min Average current during operation Standby current 1 ICCS1 CE = OE/RFSH = VIH Standby current 2 ICCS2 CE = OE/RFSH = VCC –0.2V Self-refresh current ICCSR CE = VCC–0.2V, OE/RFSH = 0.2V Access time max 70ns 65 80ns 60 100ns 50 1 LC33832P, S, M 1 LC33832PL, SL, ML LC33832P, S, M LC33832PL, SL, ML Input leakage current IIL 0V≤VIN≤VCC, pins other than test pin = 0V Output leakage current IOL Output high level voltage Output low level voltage –10 mA 3,4 mA mA 100 1 Unit Note µA mA 100 +10 µA DOUT disable, 0V≤VOUT≤VCC –10 +10 VOH IOUT = –5mA 2.4 VOL IOUT = 4.2mA µA µA V 0.4 V Note: 3) All current values are measured at minimal cycle rate. Since current flows immoderately, cycle times may become longer and shorter than shown here. 4) Dependent on output load. Maximum value is value during free state. Input/Output Capacitance Characteristics at Ta = 25°C, f = 1MHz, VCC = 5V±10% Parameter Input capacitance (A0 to A14) Symbol min max Unit Test conditions CIN1 5 pF VIN1 = 0 V Input capacitance (CE, OE/RFSH, WE) CIN2 7 pF VIN2 = 0 V 10 pF VI/O = 0 V Input/output capacitance CI/O Sampling inspections, and not full-lot inspections, are carried out for these parameters. No. 4430-4/9 LC33832P, S, M, PL, SL, ML-70/80/10 AC Electrical Characteristics at Ta = 0 to +70°C, VCC 5V±10% (Notes 5, 6, 7, 8, 9) LC33832P, S, M, PL, SL, ML Parameter Symbol -70 min -80 max min -10 max min Unit Note max Random read, write cycle time tRC 115 130 160 ns Read-write cycle time tRMW 165 195 240 ns CE pulse width tCE 70 10000 80 10000 100 10000 ns CE precharge time tP 35 40 CE access time tCEA 70 80 100 ns OE access time tOEA 30 35 40 ns CE output enable time tCLZ 10 10 10 ns OE output enable time tOLZ 0 0 0 ns WE output enable time tWLZ 0 0 0 ns CE output disable time tCHZ 0 20 0 25 0 30 ns 10 OE output disable time tOHZ 0 20 0 25 0 30 ns 10 WE output disable time tWHZ 0 20 0 25 0 30 ns 10 OE hold time for CE tOHC 0 0 0 OE setup time for CE tOSC 10 10 10 ns Read command setup time tRCS 0 0 0 ns Read command hold time tRCH 0 0 0 ns Write pulse width tWP 55 60 70 ns Write command hold time tWCH 55 60 70 ns Write command lead time tCWL 55 60 70 ns Input data setup time for WE tDSW 30 35 40 ns 11 Input data setup time for CE tDSC 30 35 40 ns 11 Input data hold time for WE tDHW 0 0 0 ns 11 Input data hold time for CE tDHC 0 0 0 ns 11 Address setup time for CE tASC 0 0 0 ns 12 Address hold time for CE tAHC 15 20 25 ns 12 50 ns ns Auto-refresh cycle time tFC 115 130 160 ns RFSH delay time for CE tRFD 35 40 50 ns RFSH pulse width (auto-refresh) tFAP 75 RFSH precharge time (auto-refresh) tFP 30 30 RFSH active CE delay time (auto-refresh) tFCE 135 RFSH pulse width (self-refresh) tFAS RFSH precharge CE delay time (self-refresh) tFRS Refresh time tREF Rise and fall time tT 8000 80 ns 13 30 ns 13 160 190 ns 13 8000 8000 8000 ns 13 135 160 190 ns 13 4 3 50 8000 80 4 3 50 3 8000 4 ms 50 ns Continued on next page. No. 4430-5/9 LC33832P, S, M, PL, SL, ML-70/80/10 Continued from preceding page. Note : 5) To accomplish internal initialization, CE and OE/RFSH are fixed at VIH for an interval of 1 ms when VCC reaches the specified voltage after power is switched on. 6) Measured at tT = 5 ns. 7) When measuring input signal timing, VIH (min) and VIL (max) are reference levels. 8) Measured using an equivalent of 100 pF and two standard TTL loads. 9) OE/RFSH input functions as output-enable input (OE) when CE = VIL, and as refresh input (RFSH) when CE = VIH. 10) tCHZ, tOHZ, and tWHZ are defined as the time until output enters the open circuit state and the output voltage level becomes immeasurable. 11) As with ordinary static RAM, write data is incorporated at the rise of WE input or CE input, whichever is earlier, and write data is therefore held during tDSW, tDSC, tDHW, or tDHC. 12) Because address input is incorporated at the fall of CE, the address is maintained during tASC or tAHC. 13) Auto-refresh and self-refresh are determined by OE/RFSH pulse width when CE = VIH, and are defined as auto-refresh when below tFAP (max), or as self-refresh when above tFAS (min). In order to activate CE after the completion of each refresh, tFCE must be assured for auto-refresh, or tFRS must be assured for self-refresh. No. 4430-6/9 LC33832P, S, M, PL, SL, ML-70/80/10 Timing Chart Read Cycle Write Cycle No. 4430-7/9 LC33832P, S, M, PL, SL, ML-70/80/10 Read-Write Cycle CE-Only Refresh Cycle No. 4430-8/9 LC33832P, S, M, PL, SL, ML-70/80/10 Auto-Refresh Cycle Note: A0 to A14, WE: “H” or “L” Self-Refresh Cycle Note: A0 to A14, WE: “H” or “L” ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 4430-9/9