LH5P860 CMOS 512K (64K × 8) Pseudo-Static RAM FEATURES DESCRIPTION • 65,536 × 8 bit organization • Cycle time: 140 ns (MIN.) The LH5P860 is a 512K-bit Pseudo-Static RAM organized as 65,536 × 8 bits. It is fabricated using silicon-gate CMOS process technology. With its built-in oscillator, it is easy to refresh memories without an external clock. • Single +5 V power supply PIN CONNECTIONS • Access time: 80 ns (MAX.) • Pin compatible with 1M standard SRAM • Power consumption (MAX.): Operating: 440 mW Self refresh (TTL level): 5.5 mW Self refresh (CMOS level): 2.75 mW • TTL compatible I/O • 512 refresh cycles/8 ms (MAX.) • Available for auto-refresh and self-refresh modes • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP TOP VIEW 32-PIN DIP 32-PIN SOP RFSH 1 32 VCC NC 2 31 A15 A14 3 30 CE2 A12 4 29 R/W A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 5P860-1 Figure 1. Pin Connections for DIP and SOP Packages 1 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 16 GND 32 VCC A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 A7 A8 A9 VBB GENERATOR A9 - A15 COLUMN ADDRESS BUFFER COLUMN DECODER 6 5 27 26 A10 23 SENSE AMPS ROW ADDRESS A0 - A8 BUFFER A11 25 A12 4 A13 28 A14 3 A15 31 CE1 22 CE2 30 REFRESH ADDRESS COUNTER EXT/INT ADDRESS MUX ROW DECODER I/O SELECTOR MEMORY ARRAY 512 K DATA IN BUFFER 13 I/O0 14 15 17 18 I/O1 I/O2 I/O3 I/O4 19 I/O5 20 I/O6 DATA OUT BUFFER 21 I/O7 CLOCK GENERATOR REFRESH CONTROLLER REFRESH TIMER RFSH 1 OE 24 R/W 29 5P860-2 Figure 2. LH5P860 Block Diagram PIN DESCRIPTION SIGNAL A0 - A15 R/W OE RFSH CE1, CE2 2 PIN NAME Address input Read/Write input Output Enable input Refresh input Chip Enable input SIGNAL I/O0 - I/O7 VCC GND NC PIN NAME Data input/output Power Supply Ground No Connection CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE 1 Applied voltage on all pins VT –1.0 to +7.0 V Output short circuit current IO 50 mA Power dissipation PD 600 mW Operating temperature Topr 0 to +70 °C Storage temperature Tstg –65 to +150 °C NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V GND 0 0 0 V Supply voltage Input voltage VIH 2.4 VCC + 0.3 V VIL –1.0 0.8 V CAPACITANCE (TA = 0 to +70°C, f = 1 MHz, VCC = 5.0 V ±10%) PARAMETER Input capacitance Input/Output capacitance MAX. UNIT A0 – A15 CONDITIONS SYMBOL CIN1 MIN. 8 pF R/W, OE, RFSH CIN2 5 pF CE1, CE 2 CIN3 5 pF I/O0 – I/O7 COUT1 10 pF DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5.0 V ±10%) PARAMETER SYMBOL Average supply current in normal operation ICC1 Supply current in standby mode ICC2 Average supply current in self refresh cycle ICC3 CONDITIONS MIN. MAX. UNIT NOTE 80 mA 1, 2 TTL input 1.0 CMOS input 0.5 TTL input 1.0 CMOS input 0.5 Input leakage current ILI 0 V ≤ V IN ≤ 6.5 V, 0 V except on test pins I/O leakage current ILO 0 V ≤ V OUT ≤ V CC + 0.3 V, Outputs in high-impedance state –10 Output HIGH voltage VOH IOUT = –1.0 mA 2.4 Output LOW voltage VOL IOUT = 4.0 mA mA mA 1, 3 1, 4 1, 5 1, 6 –10 10 µA 10 µA V 0.4 V NOTES: 1. Specified values are with outputs open. 2. I CC1 depends on the cycle time. 3. CE1 = VIH, RFSH = VIH. 4. CE1 = VCC – 0.2 V, RFSH = VCC – 0.2 V. 5. CE1 = VIH, RFSH = VIL. 6. CE1 = VCC – 0.2 V, RFSH = 0.2 V. 3 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 AC CHARACTERISTICS 1, 2, 3 (TA = 0 to +70°C, VCC = 5.0 V ±10%) PARAMETER SYMBOL MIN. Random read, write cycle time MAX. UNIT NOTE tRC 140 ns tRMW 205 ns CE pulse width tCE 80 CE precharge time tP 50 Address setup time tAS 0 ns 4 Address hold time tAH 20 ns 4 Read modify write cycle time 10,000 ns ns Read command setup time tRCS 0 ns Read command hold time tRCH 0 ns CE access time tCEA 80 ns 5 OE access time tOEA 30 ns 5 Output enable time from CE tCLZ 20 ns Output enable time from OE tOLZ 0 ns Output enable time from R/W tWLZ 0 Output disable time from CE tCHZ 25 ns Output disable time from OE tOHZ 25 ns Output diable time from R/W tWHZ 25 ns ns OE setup time tOES 10 ns OE hold time tOEH 10 ns Write command pulse width tWP 30 ns Write command setup time tWCS 30 ns Write command hold time tWCH 50 ns Data setup time from R/W tDSW 30 ns 6 Data setup time from CE tDSC 30 ns 6 Data hold time from R/W tDHW 0 ns 6 Data hold time from CE tDHC 0 ns 6 tT 3 Transition time (rise and fall) 35 ns 8 ms Refresh time interval tREF Refresh command hold time tRHC 15 ns Auto refresh cycle time tFC 130 ns Refresh delay time from CE tRFD 50 ns Refresh pulse width (Auto refresh) tFAP 30 Refresh precharge time (Auto refresh) tFP 30 Refresh pulse width (Self refresh) tFAS 8,000 ns CE delay time from refresh precharge (Self refresh) tFRS 160 ns INPUT 2.4 V 0.8 V NOTES: 1. In order to initialize the circuit, an initialize pause of 100 µs with CE1 = VIH, RFSH = VIH (or CE2 = VIL, RFSH = VIH) is required after power-up, followed by at least 8 dummy cycles. 2. AC characteristics are measured at t T = 5 ns. 3. AC characteristics are measured at the following condition (see figure at right): 4. Address is latched at the negative edge of CE1 or at the positive edge of CE2. 5. Measured with a load equivalent to 2TTL + 100 pF. 6. Data is latched at the positive edge of R/W, at the positive edge of CE1, or at the negative edge of CE2. OUTPUT 8,000 ns ns 2.6 V 0.6 V 2.2 V 0.8 V 5P860-12 Figure 3. AC Characteristics 4 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 tRC tCE tP VIH CE1 VIL VIH CE2 V IL tAS VIH A0 - A15 V IL tAH ADDRESS INPUT VIH OE V IL tRCS tRCH VIH R/W V IL tOEA tCEA tOLZ tOHZ tCLZ VOH I/O0 - I/O7 V OL tCHZ VALID-DATA OUTPUT tFP tFRS tRHC tRFD VIH RFSH VIL NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH). 5P860-3 Figure 4. Read Cycle 5 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 tRC tP CE1 VIH VIL CE2 VIH VIL tCE tAS A0 - A15 VIH VIL tAH ADDRESS INPUT tOES tOEH VIH OE V IL tWCS tWCH tWP VIH R/W V IL tDSW tDHW tDSC VOH I/O0 - I/O7 VOL tDHC DATA INPUT tFP tFRS tRHC tRFD VIH RFSH VIL NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH). Figure 5. Write Cycle 1 (OE = Fix ‘H’) 6 5P860-4 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 tRC tCE tP VIH CE1 VIL VIH CE2 VIL tAS VIH A0 - A15 V IL OE tAH ADDRESS INPUT VIH VIL tWCS tWCH tWP R/W VIH VIL tDSW tDHW tDSC VIH DIN V IL tDHC DATA INPUT tCLZ I/O0 - I/O7 tWHZ tOHZ tOLZ tWLZ tCHZ VOH DOUT V OL tFP tFRS tRHC tRFD VIH RFSH VIL NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH). 5P860-5 Figure 6. Write Cycle 2 (OE Clock) 7 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 tRC tP tCE VIH CE1 VIL V CE2 VIH IL tAH tAS A0 - A15 VIH VIL OE VIH VIL ADDRESS INPUT tWCS tWCH tWP VIH R/W V IL tDSW tDHW tDSC DIN VIH VIL tDHC DATA INPUT tCLZ I/O0 - I/O7 tWHZ tWLZ tCHZ V DOUT VOH OL tFP tFRS tFD tRHC tRFD V RFSH VIH IL NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH). Figure 7. Write Cycle 3 (OE = Fix ‘L’) 8 5P860-6 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 tRMW tP CE1 VIH VIL CE2 VIH VIL tAS A0 - A15 VIH VIL tAH ADDRESS INPUT V OE VIH IL tWCS tRCS R/W tWP VIH VIL tOEA tDSW tCEA tDHW tDSC tDHC VIH DIN V IL DATA INPUT tWHZ tOLZ I/O0 - I/O7 tCLZ V DOUT VOH OL tOHZ tWLZ tCHZ DATA OUTPUT tFP tFRS RFSH tRHC tRFD VIH VIL NOTE: Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH). 5P860-7 Figure 8. Read-Modify-Write Cycle 9 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 tRC tP tCE VIH CE1 VIL VIH CE2 V IL tAS VIH A0 - A8 VIL tAH ADDRESS INPUT tOES tOEH tRCS tRCH VIH OE VIL VIH R/W V IL V I/O0 - I/O7 VOH OL OPEN tFP tFRS tRHC tRFD VIH RFSH VIL NOTES: 1. Operation is possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH). 2. A9 - A16 = Don't Care. Figure 9. CE Only Refresh Cycle 10 5P860-8 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 V CE1 VIH IL V CE2 VIH IL OR CE1 VIH VIL tFC tFC V CE2 VIH IL tRFD tRHC tFP RFSH VIH VIL I/O0 - I/O7 VOH VOL tFAP tFP tFP tFAP OPEN NOTE: OE, R/W, A0 - A16 = Don't care 5P860-9 Figure 11. Auto Refresh Cycle CE1 VIH VIL V CE2 VIH IL OR V CE1 VIH IL CE2 VIH VIL tRHC tRFD tFP RFSH VIH VIL I/O0 - I/O7 VOH VOL tFAS tFRS OPEN NOTE: OE, R/W, A0 - A16 = Don't care 5P860-10 Figure 10. Self Refresh Cycle 11 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 PACKAGE DIAGRAMS 32DIP (DIP032-P-0600) 32 17 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 16 0.30 [0.012] 0.20 [0.008] 41.30 [1.626] 40.70 [1.602] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.51 [0.020] MIN. 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32DIP 32-pin, 600-mil DIP 32SOP (SOP032-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 32 17 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 20.80 [0.819] 20.40 [0.803] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32SOP 32-pin, 525-mil SOP 12 CMOS 512K (64K × 8) Pseudo-Static RAM LH5P860 ORDERING INFORMATION LH5P860 Device Type X Package - ## Speed 80 Access Time (ns) D 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) CMOS 512K (64K x 8) Pseudo-Static RAM Example: LH5P860N-80 (CMOS 512K (64K x 8) Pseudo-Static RAM, 80 ns, 32-pin, 525-mil SOP) 5P860-11 13