IRF IPS031G

Data Sheet No.PD 60151-J
IPS031G/IPS032G
SINGLE/DUAL FULLY PROTECTED POWER MOSFET SWITCH
Features
•
•
•
•
•
Product Summary
Over temperature shutdown
Over current shutdown
Active clamp
Low current & logic level input
E.S.D protection
Description
Rds(on)
70mΩ (max)
V clamp
50V
Ishutdown
12A
Ton/Toff
The IPS031G/IPS032G are fully protected single/dual
low side SMART POWER MOSFETs that feature overcurrent, over-temperature, ESD protection and drain
to source active clamp.These devices combine a
HEXFET ® POWER MOSFET and a gate driver. They
offer full protection and high reliability required in
harsh environments. The driver allows short switching times and provides efficient protection by turning
off the power MOSFET when the temperature exceeds 165oC or when the drain current reaches 12A.
The device restarts once the input is cycled. The
avalanche capability is significantly enhanced by the
active clamp and covers most inductive load demagnetizations.
1.5µs
Packages
16-Lead SOIC
IPS032G
(Dual)
8-Lead SOIC
IPS031G
Typical Connection
Load
R in series
(if needed)
D
IN
Q
control
S
S
Logic signal
(Refer to lead assignment for correct pin assignment)
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1
IPS031G/IPS032G
31
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are referenced to SOURCE lead. (TAmbient = 25oC unless otherwise specified). PCB mounting uses the standard footprint with 70 µm
copper thickness. All Sources leads of each mosfet must be connected together to get full current capability
Symbol Parameter
Min.
Max.
—
47
Maximum input voltage
-0.3
7
V
Maximum IN current
Diode max. continuous current (1)
-10
+10
mA
(rth=125oC/W) IPS031G
—
1.4
rth=85oC/W)
IPS032G
—
2
Isd pulsed Diode max. pulsed current (1) (for ea. mosfet)
Pd
Maximum power dissipation(1)
(rth=125oC/W) IPS031G
—
15
—
1
(for all Pd mosfets, rth=85oC/W) IPS032G
—
1.5
Vds
Maximum drain to source voltage
Vin
Iin, max
Isd cont.
(for all sd mosfets,
Units
Test Conditions
A
W
ESD1
Electrostatic discharge voltage (Human Body)
—
4
ESD2
Electrostatic discharge voltage (Machine Model)
—
0.5
T stor.
Tj max.
Max. storage temperature
-55
150
Max. junction temperature
-40
150
Min.
Typ.
—
100
—
—
65
—
—
85
—
—
100
—
—
60
—
C=100pF, R=1500Ω,
kV
C=200pF, R=0Ω, L=10µH
o
C
Thermal Chacteristics
Symbol Parameter
Rth1
Thermal resistance
Rth2
Thermal resistance
Rth1
Thermal resistance
(2 mos on)
(2 mosfets on)
Rth2
Thermal resistance
(1 mos on)
(1 mosfet on)
Rth3
Thermal resistance
(2 mos on)
(2 mosfets on)
with standard footprint
with 1" square footprint
with standard footprint
Max. Units Test Conditions
with standard footprint
SOIC-8
o
C/W
SOIC-16
with 1" square footprint
(1) Limited by junction temperature (pulsed current limited also by internal wiring)
2
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IPS031G/IPS032G
Recommended Operating Conditions
These values are given for a quick design. For operation outside these conditions, please consult the application notes.
Symbol Parameter
Min.
Max.
Vds (max)
VIH
VIL
Ids
—
4
0
35
6
0.5
—
—
0.2
—
0
2.2
1.65
5
1
1
Continuous Drain to Source voltage
High level input voltage
Low level input voltage
Continuous drain current
Tamb=85 oC
(TAmbient = 85oC, IN = 5V, rth = 100oC/W, Tj = 125oC) IPS031G
(TAmbient = 85oC, IN = 5V, rth = 85oC/W, Tj = 125oC) IPS032G
Rin
Recommended resistor in series with IN pin
Tr-in(max) Max recommended rise time for IN signal (see fig. 2)
Fr-I sc (2) Max. frequency in short circuit condition (Vcc = 14V)
Units
V
A
kΩ
µS
kHz
Static Electrical Characteristics
(Tj = 25oC unless otherwise specified.)
Symbol Parameter
Rds(on)
Rds(on)
Idss
Min.
Typ.
ON state resistance Tj = 25oC
ON state resistance Tj = 150 oC
Drain to source leakage current
20
—
0
45
75
0.5
Max. Units Test Conditions
60
100
25
Drain to source leakage current
0
5
50
Drain to source clamp voltage 1
Drain to source clamp voltage 2
IN to source clamp voltage
IN threshold voltage
ON state IN positive current
OFF state IN positive current
47
50
7
1
25
50
52
53
8.1
1.6
90
130
56
60
9.5
2
200
250
@Tj=25oC
Idss2
mΩ
Vin = 5V, Ids = 1A
Vcc = 14V, Tj = 25oC
µA
Vcc = 40V, Tj = 25oC
@Tj=25oC
V clamp 1
V clamp 2
Vin clamp
Vth
Iin, -on
Iin, -off
V
µA
Id = 20mA (see Fig.3 & 4)
Id=Ishutdown (see Fig.3 & 4)
Iin = 1 mA
Id = 50mA, Vds = 14V
Vin = 5V
Vin = 5V
over-current triggered
Switching Electrical Characteristics
Vcc = 14V, Resistive Load = 5Ω (IPS031), Resistive Load = 3Ω (IPS031S), Rinput = 50Ω, 100µs pulse,Tj = 25oC, (unless
otherwise specified).
Symbol Parameter
Min.
Ton
Tr
Trf
T off
Tf
Qin
0.05
0.4
—
0.8
0.5
—
Turn-on delay time
Rise time
Time to 130% final Rds(on)
Turn-off delay time
Fall time
Total gate charge
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Typ. Max. Units Test Conditions
0.3
1
8
2
1.5
1.1
0.6
2
—
3.5
2.5
—
See figure 2
µs
See figure 2
nC
Vin = 5V
3
IPS031G/IPS032G
Protection Characteristics
Symbol Parameter
T sd
I sd
V reset
Treset
EOI_OT
Over temperature threshold
Over current threshold
IN protection reset threshold
Time to reset protection
Short circuit energy (see application note)
Min.
Typ.
—
10
1.5
2
—
165
14
2.3
10
400
Max. Units Test Conditions
—
18
3
40
—
o
C
A
V
µs
µJ
See fig. 1
See fig. 1
Vin = 0V, Tj = 25oC
Vcc = 14V
Functional Block Diagram
All values are typical
DRAIN
47 V
300 Ω
IN
8.1 V
S
Q
R
Q
200 kΩ
I sense
80 µA
T > 165°c
I > 1sd
SOURCE
Lead Assignments
D
D
D
D
D1 D1 D1 D1 D2 D2 D2 D2
1
1
S
S
S
S1 S1 S1 I1 S2 S2 S2 I2
In
8 Lead SOIC
16 Lead SOIC
(Dual)
IPS032G
IPS031G
Part Number
4
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IPS031G/IPS032G
Vin
5V
90 %
0V
Vin 10 %
Ids
t < T reset
Tr-in
t > T reset
I shutdown
Isd
90 %
Ids
10 %
Td on
Td off
tf
tr
T
T shutdown
Tsd
(165 °c)
Vds
Figure 1 - Timing diagram
Figure 2 - IN rise time & switching time definitions
T clamp
Vin
L
Rem : V load is negative
during demagnetization
V load
+
R
14 V
-
Ids
Vin
Vds clamp
( Vcc )
Vds
5v
0v
D
IN
Vds
S
Ids
( see Appl . Notes to evaluate power dissipation )
Figure 3 - Active clamp waveforms
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Figure 4 - Active clamp test circuit
5
IPS031G/IPS032G
All curves are typical values with standard footprints. Operating in the shaded area is not recommended.
100
200%
90
180%
80
160%
70
140%
o
Tj = 150 C
60
120%
50
100%
Tj = 25oC
40
80%
30
60%
20
40%
10
20%
0
0
1
2
3
4
5
6
7
8
Figure 5 - Rds ON (mΩ) Vs Input Voltage (V)
0%
-50 -25
10
9
9
8
8
50
75 100 125 150 175
toff delay
fall tim e
7
ton delay
rise tim e
130% final rdson
6
5
4
6
5
4
3
3
2
2
1
1
0
0
0
1
2
3
4
5
6
7
8
Figure 7 - Turn-ON Delay Time, Rise Time &
Time to 130% final Rds(on) (us) Vs Input Voltage
(V)
6
25
Figure 6 - Normalised Rds ON (%) Vs Tj (oC)
10
7
0
0
1
2
3
4
5
6
7
8
Figure 8 - Turn-OFF Delay Time & Fall Time (us)
Vs Input Voltage (V)
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IPS031G/IPS032G
100
100
delay off
fall tim e
delay on
rise tim e
130% rdson
10
10
1
1
0 .1
0 .1
10
10
100
1000
Figure 9 - Turn-ON Delay Time, Rise Time &
Time to 130% final Rds(on) Vs IN Resistor (Ω)
20
18
18
16
16
14
14
12
12
10
10
8
8
6
6
4
Isd 25°C
4
2
Ilim 25°C
2
0
1
2
3
4
5
6
7
8
Figure 11 - Current Iimimitation & I shutdown (A)
Vs Vin (V)
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1000
10000
Figure 10 - Turn-OFF Delay Time & Fall Time (us)
Vs IN Resistor (Ω)
20
0
100
10000
0
-50 -25
0
25
50
75 100 125 150
Figure 12 - I shutdown (A) Vs Temperature (oC)
7
IPS031G/IPS032G
10
10
rth = 50°C/W
SO8 Std. footprint 100°C/W
8
6
4
4
2
2
0
50
100
150
200
SO8 Std. footprint 2 m osfets on
8
6
0
-50
SO16 Std. footprint 1 m osfet on
0
-50
Figure 13a - Max.Cont. Ids (A)
Vs Amb. Temperature (oC) - IPS031G
0
T = 100 °C
100
150
200
Figure 13b - Max.Cont. Ids (A)
Vs Amb. Temperature (oC) - IPS032G
100
T = 25°C
50
100
single pulse
100 Hz rth=100°C/W dT=25°C
1kHz rth=100°C/W dT=25°C
10
10
1
1
Vbat = 14 V
Tjini = T sd
0.1
0 .0 1
Figure 14 - Ids (A) Vs Protection Resp. Time (s)
IPS031G/IPS032G
8
0 .1
1
10
100
Figure 15 - Iclamp (A) Vs Inductive Load (mH)
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IPS031G/IPS032G
100
1 00
rth SO8 std footprint
10
10
1
1
Single pulse
Single pulse
0 .1
0 .1
0 .0 1
0 .0 1
Figure 16a - Transient Thermal Imped. (oC/W)
Vs Time (s) - IPS031G
rth SO16 std footprint 1
mosfet active
rth SO16 std footprint 2
mosfets active
Figure 16b - Transient Thermal Imped. (oC/W)
Vs Time (s) - IPS032G
200
120%
180
115%
160
110%
140
120
105%
100
100%
80
95%
60
Iin,on
40
20
Iin,off
0
-50
-25
0
25
50
75
100 125 150
Figure 17 - Input current (µA) Vs Tj (oC)
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90%
Vds clam p @ Isd
85%
Vin clam p @ 10m A
80%
-50 -25
0
25
50
75 100 125 150
Figure 18 - Vin clamp and V clamp2 (%)
Vs Tj (oC)
9
IPS031G/IPS032G
16
14
Treset
rise tim e
12
fall tim e
10
8
6
4
2
0
-50
-25
0
25
50
75
100 125 150
Figure 19 - Turn-on, Turn-off, and Treset KI
Vs Tj (oC)
Case Outlines
D
DIM
B
5
A
F OOT PRINT
6
8
7
6
5
H
E
0.25 [.010]
1
2
3
A
4
6.46 [.255]
MIN
.0532
.0688
1.35
1.75
A1 .0040
3X 1.27 [.050]
8X 1.78 [.070]
MAX
.0098
0.10
0.25
b
.013
.020
0.33
0.51
c
.0075
.0098
0.19
0.25
D
.189
.1968
4.80
5.00
E
.1497
.1574
3.80
4.00
e
.050 BAS IC
1.27 BAS IC
.025 BAS IC
0.635 BAS IC
e1
6X e
MILLIMETERS
MAX
A
8X 0.72 [.028]
INCHES
MIN
H
.2284
.2440
5.80
6.20
K
.0099
.0196
0.25
0.50
L
.016
.050
0.40
1.27
y
0°
8°
0°
8°
K x 45°
e1
A
C
y
0.10 [.004]
8X b
0.25 [.010]
A1
8X L
7
C A B
NOT ES:
1. DIMENS IONING & T OLERANCING PE R ASME Y14.5M-1994.
5 DIMENSION DOES NOT INCLUDE MOLD PROT RUS IONS.
MOLD PROTRUSIONS NOT T O E XCEED 0.15 [.006].
2. CONT ROLLING DIMENSION: MILLIMET ER
6 DIMENSION DOES NOT INCLUDE MOLD PROT RUS IONS.
MOLD PROTRUSIONS NOT T O E XCEED 0.25 [.010].
3. DIMENS IONS ARE SHOWN IN MILLIME TE RS [INCHES].
4. OUT LINE CONF ORMS T O JEDEC OUTLINE MS-012AA.
8-Lead SOIC
10
8X c
7 DIMENSION IS T HE LE NGTH OF LEAD FOR SOLDE RING TO
A SUBS TRAT E.
01-6027
01-0021 11 (MS-012AA)
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IPS031G/IPS032G
16 -Lead SOIC (narrow body)
01-6018
01-3064 00 (MS-012AC)
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 6/11/2001
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