HITACHI HD74CDCF2510B

HD74CDCF2510B
140 MHz, 0 to 85°C Operation
3.3-V Phase-lock Loop Clock Driver
ADE-205-225F (Z)
7th. Edition
January 2000
Description
The HD74CDCF2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the
clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The
HD74CDCF2510B operates at 3.3 V VCC and is designed to drive up to five clock loads per output.
Bank of outputs provide ten low-skew, low-jitter copies of the input clock. Output signal duty cycles are
adjusted to 50 percent independent of the duty cycle at the input clock. Bank of outputs can be enabled or
disabled via the control (G) inputs. When the G inputs are high, the outputs switch in phase and frequency
with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the HD74CDCF2510B does not require external RC networks.
The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, HD74CDCF2510B requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL
reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
Features
•
•
•
•
•
•
•
Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”
Phase-lock loop clock distribution for synchronous DRAM applications
External feedback (FBIN) pin is used to synchronize the outputs to the clock input
No external RC network required
Support spread spectrum clock (SSC) synthesizers
Supports frequencies up to 140 MHz
0 to 85°C operating range
HD74CDCF2510B
Function Table
Inputs
Outputs
G
CLK
1Y (0:9)
FBOUT
X
L
L
L
L
H
L
H
H
H
H
H
H:
L:
X:
High level
Low level
Immaterial
Pin Arrangement
AGND 1
24 CLK
VCC
23 AVCC
2
1Y0 3
22 VCC
1Y1 4
21 1Y9
1Y2 5
20 1Y8
6
19 GND
GND 7
18 GND
1Y3 8
17 1Y7
9
16 1Y6
VCC 10
15 1Y5
G 11
14 VCC
GND
1Y4
FBOUT 12
13 FBIN
(Top view)
2
HD74CDCF2510B
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
V CC
–0.5 to 4.6
V
VI
–0.5 to 6.5
V
VO
–0.5 to VCC +0.5 V
Input clamp current
IIK
–50
mA
VI < 0
Output clamp current
IOK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±50
mA
VO = 0 to VCC
Supply current
ICC or IGND
±100
mA
Maximum power dissipation
at Ta = 55°C (in still air) *3
PT
0.7
W
Storage temperature
Tstg
–65 to +150
°C
Supply voltage
Input voltage
*1
Output voltage
Notes:
*1, 2
Conditions
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and
a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol Min
Supply voltage
V CC
Input voltage
Output current
Operating temperature
Typ
Max
Unit
3.0
—
3.6
V
VIH
2.0
—
—
V
VIL
—
—
0.8
VI
0
—
V CC
IO H
—
—
–12
IO L
—
—
12
Ta
0
—
85
Conditions
mA
°C
Note: Unused inputs must be held high or low to prevent them from floating.
3
HD74CDCF2510B
Logic Diagram
G
11
3
1Y0
4
1Y1
5
1Y2
8
1Y3
9
1Y4
15
1Y5
16
17
CLK
AVCC
4
1Y7
24
20
PLL
FBIN
1Y6
13
23
21
12
1Y8
1Y9
FBOUT
HD74CDCF2510B
Pin Function
Pin name
No.
Type
Description
CLK
24
I
Clock input. CLK provides the clock signal to be distributed by the
HD74CDCF2510B clock driver. CLK is used to provide the
reference signal to the integrated PLL that generates the clock
output signals. CLK must have a fixed frequency and fixed phase
for the PLL to obtain phase lock. Once the circuit is powered up
and a valid CLK signal is applied, a stabilization time is required for
the PLL to phase lock the feedback signal to its reference signal.
FBIN
13
I
Feedback input. FBIN provides the feedback signal to the internal
PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The
integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
G
11
I
Output bank enable. G is the output enable for outputs 1Y(0:9).
When G is low, outputs 1Y(0:9)are disabled to a logic-low state.
When G is high, all outputs 1Y(0:9) are enabled and switch at the
same frequency as CLK.
FBOUT
12
O
Feedback output. FBOUT is dedicated for external feedback. It
switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL.
1Y(0:9)
3, 4, 5, 8, 9, O
15, 16, 17,
20, 21
Clock outputs. These outputs provide low-skew copies of CLK.
Output bank 1Y(0:9) is enabled via the G input. These outputs can
be disabled to a logic low state by deasserting the G control input.
AVCC
23
Power
Analog power supply. AVCC provides the power reference for the
analog circuitry. In addition, AVCC can be used to bypass the PLL
for test purposes. When AVCC is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
AGND
1
Ground Analog ground. AGND provides the ground reference for the
analog circuitry.
V CC
2, 10, 14, 22 Power
GND
6, 7, 18,19
Power supply
Ground Ground
5
HD74CDCF2510B
Electrical Characteristics
Item
Symbol Min
Input clamp voltage
VIK
—
Output voltage
VOH
VOL
Typ
*1
Max
Unit Test Conditions
—
–1.2
V
VCC = 3 V, II = –18 mA
VCC–0.2
—
—
V
VCC = Min to Max, IOH = –100 µA
2.1
—
—
VCC = 3 V, IOH = –12 mA
2.4
—
—
VCC = 3 V, IOH = –6 mA
—
—
0.2
VCC = Min to Max, IOL = 100 µA
—
—
0.8
VCC = 3 V, IOL = 12 mA
—
—
0.55
VCC = 3 V, IOL = 6 mA
Input current
IIN
—
—
±5
µA
VCC = 3.6 V, VIN = VCC or GND
Quiescent supply
current
IC C
—
—
10
µA
AVCC = GND, VCC = 3.6 V,
VI = VCC or GND, IO = 0
∆I C C
—
—
500
µA
AVCC = GND, VCC = 3.3 to 3.6 V
One input at VCC–0.6 V,
Other inputs at VCC or GND
Input capacitance
CIN
—
4
—
pF
VCC = 3.3 V, VI = VCC or GND
Output capacitance
CO
—
6
—
pF
VCC = 3.3 V, VO = VCC or GND
Note:
6
1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions.
HD74CDCF2510B
Switching Characteristics (CL = 25 pF, Ta = 0 to 85°C)
Item
Symbol
V C C = 3.3 V±0.3 V
Unit
From (Input)
To (Output)
FBIN↑
Min
Typ
Max
–125
—
125
ps
66 MHz <
CLKIN↑
≤ 133 MHz
Between output pins skew *1 t sk (O)
—
—
150
ps
Any Y or FBOUT Any Y or
FBOUT
Cycle to cycle jitter
–75
—
75
ps
F (clkin =
133 MHz)
Duty cycle
45
—
55
%
F (clkin =
Any Y or
66 to 133 MHz) FBOUT
Slew rate
5.0
—
1.0
volts/ns
Any Y or
FBOUT
100
—
—
mVP–P
AVCC
Phase error time
tp e
Analog power supply
rejection
(DC to 10 MHz)
Notes:
Vapsr *2
Any Y or
FBOUT
The specifications for parameters in this table are applicable only after any appropriate
stabilization time has elapsed.
1. The tsk(O) specification is only valid for equal loading of all outputs.
2. This parameter is characterized but not tested.
Timing requirements
Item
Symbol Min
Input clock frequency
f clock
Input clock duty cycle
Stabilization time
Note:
*1
Max
Unit
50
140
MHz
40
60
%
—
1
ms
Test Conditions
After power up
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its
reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase
reference signal must be present at CLK. Until phase lock is obtained, the specifications for
propagation delay and skew parameters given in the switching characteristics table are not
applicable.
7
HD74CDCF2510B
Test Circuit
From output
under test
*1
C L = 25 pF
Note:
1.
500 Ω
CL includes probe and jig capacitance.
Waveforms – 1
3V
Input
50% VCC
50% VCC
0V
Output
(=FBOUT)
2V
tTLH
Notes:
1.
2.
8
VOH
2V
50% VCC
0.4 V
0.4 V
VOL
tTHL
All input pulses are supplied by generators having the following characteristics: PRR ≤ 100
MHz, ZO = 50 Ω, tr = 1.2 ns, tf = 1.2 ns.
The outputs are measured one at a time with one transition per measurement.
HD74CDCF2510B
Waveforms – 2
CLKIN
t phase error
FBIN
FBOUT
t sk (o)
Any Y
Any Y
t sk (o)
Any Y
9
HD74CDCF2510B
Package Dimensions
Unit : mm
7.80
8.10 Max
13
1
12
4.4
24
0.65
0.20 ± 0.06
1.0
0.13 M
6.4 ± 0.2
0.10
Dimension including the plating thickness
Base material dimension
10
0.17 ± 0.05
0.15 ± 0.04
1.10 Max
0.65 Max
0° – 8°
0.07 +0.03
–0.04
0.22 +0.08
–0.07
0.5 ± 0.1
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-24DB
—
—
0.08 g
HD74CDCF2510B
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that
the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential
damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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