HD74CDC857 3.3/2.5-V Phase-lock Loop Clock Driver ADE-205-222E (Z) 6th. Edition July 1999 Description The HD74CDC857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is specifically designed for use with DDR (Double Data Rate) synchronous DRAMs. Features • Supports 100 MHz to 150 MHz operation range *1 • Distributes one differential clock input pair to ten differential clock outputs pairs • SSTL_2 (Stub Series Terminated Logic) differential inputs and LVCMOS reset (G) input • Supports spread spectrum clock • External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input • Supports both 3.3 V/2.5V analog supply voltage (AV CC), and 2.5 V VDDQ • No external RC network required • Sleep mode detection • 48pin TSSOP (Thin Shrink Small Outline Package) Note: 1. 200 MHz (Max) ver. will be available by 4Q/’99 Function Table Inputs : Outputs : PLL G CLK CLK : Y Y FBOUT FBOUT L L H : Z Z Z Z : off L H L : Z Z Z Z : off H L H : L H L H : run H H L : H L H L : run X 0 MHz 0 MHz : Z Z Z Z : off H: L: Z: X: High level Low level High impedance Don’t care HD74CDC857 Pin Arrangement 48 GND GND 1 Y0 2 47 Y5 Y0 3 46 Y5 V DDQ 4 45 V DDQ Y1 5 44 Y6 Y1 6 43 Y6 GND 7 42 GND GND 8 41 GND Y2 9 40 Y7 Y2 10 39 Y7 V DDQ 11 38 V DDQ V DDQ 12 37 G CLK 13 36 FBIN CLK 14 35 FBIN V DDQ 15 34 V DDQ AV CC 16 33 FBOUT AGND 17 32 FBOUT 31 GND GND 18 Y3 19 30 Y8 Y3 20 29 Y8 V DDQ 21 28 V DDQ Y4 22 27 Y9 Y4 23 26 Y9 GND 24 25 GND (Top view) 2 HD74CDC857 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VDDQ –0.5 to 4.6 V VI –0.5 to 4.6 V VO –0.5 to VDDQ +0.5 V Input clamp current I IK –50 mA VI < 0 Output clamp current I OK –50 mA VO < 0 Continuous output current IO ±50 mA VO = 0 to VDDQ Supply current through each V DDQ or GND I VDDQ or IGND ±100 mA Maximum power dissipation at Ta = 55°C (in still air) 0.7 W –65 to +150 °C Input voltage Output voltage *1 Storage temperature Notes: Tstg Conditions Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 3 HD74CDC857 Recommended Operating Conditions Item Symbol Min Typ Max Unit Conditions Supply voltage AVCC (1) 2.3 — 2.7 V AVCC (2) 3.0 — 3.6 2.3 — 2.7 V –0.3 — VDDQ+0.3 V Output supply voltage DC input signal voltage VDDQ *1 f CLK = 100 to 150 MHz f CLK = 130 to 150 MHz All pins High level input voltage VIHD 1.7 — — V Low level input voltage VILD — — 0.8 V High level input voltage VIHG 1.7 — VDDQ+0.3 V G input pin VILG –0.3 — 0.7 V G input pin VID 0.36 — VDDQ+0.6 V DC 0.7 — VDDQ+0.6 0.5×VDDQ –0.35 — 0.5×VDDQ +0.35 V Vref 1.15 1.25 1.35 V I OH –7 — –30 mA I OL 7 — 30 Input slew rate SR 1 — — V/ns Operating temperature Ta 0 — 70 °C Low level input voltage Differential input signal voltage Differential cross point voltage Reference voltage *4 Output current Notes: 1. 2. 3. 4. 4 *2 *3 AC Vref = 0.5 × V DDQ Unused inputs must be held high or low to prevent them from floating. Feedback inputs (FBIN, FBIN) may float when the device is in low power mode. DC input signal voltage specifies the allowable dc execution of differential input. Differential input signal voltage specifies the differential voltage |VTR–VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. Differential cross point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing. (See figure1-1) Vref is the reference DC level, when using single clock input. When CLK (pin#13) is single ended input, CLK (pin#14) must be set Vref . (See figure1-2) HD74CDC857 VDDQ VTR VID VCP GND Crossing point Figure 1-1 Differential input levels VDDQ CLK CLK *4 CLK CLK Vref Vref GND Figure 1-2 Single input levels 5 HD74CDC857 Logic Diagram G Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 CLK CLK Y7 PLL FBIN FBIN Y8 Y8 Y9 Y9 AVCC FBOUT FBOUT Note: All inputs and outputs are associated with VDDQ = 2.5 V. 6 HD74CDC857 Pin Function Pin name No. Type AGND 17 Ground Analog ground. AGND provides the ground reference for the analog circuitry. AVCC 16 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AV CC can be used to bypass the PLL for test purposes. When AV CC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. CLK, CLK 13, 14 I Clock input. CLK provides the clock signal to be distributed by the HD74CDC857 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN, FBIN 35, 36 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. FBOUT, FBOUT 32, 33 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. G 37 I Output bank enable. G is the output enable for all outputs. When G is low, VCO will stop and all outputs are disabled to a high impedance state. When G will be returned high, PLL will resynchroniz to CLK frequency and all outputs are enabled. GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 Ground Ground VDDQ 4, 11, 12, 15, 21, 28, 34, 38, 45 Power Y 3, 5, 10, 20, O 22, 27, 29, 39, 44, 46 Clock outputs. These outputs provide low-skew copies of CLK. Y 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 Clock outputs. These outputs provide low-skew copies of CLK. O Description Power supply 7 HD74CDC857 Electrical Characteristics Min Typ *1 Max Unit Test Conditions VIK Input clamp CLK, CLK voltage FBIN, FBIN, G — — –1.2 V I I = –18 mA, VDDQ = 2.3 V Output voltage VCC–0.2 — — V I OH = –100 µA, VCC = 2.3 to 2.7 V 1.95 — — I OH = –8 mA, VCC = 2.3 V 1.70 — — I OH = –16 mA, VCC = 2.3 V — — 0.2 I OL = 100 µA, VCC = 2.3 to 2.7 V — — 0.35 I OL = 8 mA, VCC = 2.3 V — — 0.55 I OL = 16 mA, VCC = 2.3 V Item Symbol VOH VOL Input current II — — ±10 µA Input capacitance CI — — 4 pF Note: VI = 0 V to 2.7 V, VDDQ = 2.7 V 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Switching Characteristics Item Symbol Cycle to cycle jitter Min Typ Max Unit Test Conditions –100 — 100 ps See figure 2 Phase error time t (phase error) –150 — 150 ps See figure 2, 3, 4 Output skew t sk (o) — — 200 ps See figure 2 Differential clock skew t sk (diff) –100 — 100 ps See figure 2 45 — 55 % See figure 2 — 25 — Ω See figure 2 Duty cycle Output impedance Clock frequency ZO f CLK 100 — 150 *1 MHz See figure 2, AV CC = 2.5±0.2 V *1 See figure 2, AV CC = 2.5±0.2 V or AV CC = 3.3±0.3 V 130 — 150 Slew rate 1.2 — — V/ns See figure 2 Stabilization time — — 0.1 ms Note: 8 1. 200 MHz (Max) ver. will be available by 4Q/’99. See figure 2, 3 HD74CDC857 Differential clock outputs are directly terminated by a 120 Ω resistor. Figure 2 is typical usage conditions of outputs load. V DDQ V DDQ Device under OUT test RT = 120 Ω OUT Figure 2 Differential signal using direct termination resistor Differential cross point voltage Vref V IH V ref +0.35 V V ref V ref –0.35 V V IL 0.5 × VDDQ VIH 1.7 V VIL 0.8 V Figure 3 CLKIN waveforms 9 HD74CDC857 CLKIN (Differential input) FBIN t(phase error) CLKIN (Single input) Vref FBIN t(phase error) FBOUT Yx tsk(o) Yx Yx' tsk(o) Yx Yx tsk(diff) Figure 4 Timings 10 HD74CDC857 Package Dimensions Unit : mm +0.3 12.50 –0.1 25 6.10 +0.3 –0.1 48 0.15 ± 0.05 24 0.08 M 0.65 Max 0.10 0.05 Min 0.20 +0.1 –0.05 0.50 1.20 max 1 8.10 ± 0.3 10° Max 0.50 ± 0.1 Hitachi code EIAJ code JEDEC code TTP-48DC — — 11 HD74CDC857 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 12