HITACHI HD74CDCV857

HD74CDCV857
2.5-V Phase-lock Loop Clock Driver
ADE-205-335C (Z)
Preliminary
4th Edition
March 2000
Description
The HD74CDCV857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is
specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.
Features
• Supports 60 MHz to 200 MHz operation range
• Distributes one differential clock input pair to ten differential clock outputs pairs
• Supports spread spectrum clock requirements meeting the PC100 SDRAM registered DIMM
specification
• External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input
• Supports 2.5V analog supply voltage (AVCC), and 2.5 V VDDQ
• No external RC network required
• Sleep mode detection
• 48pin TSSOP (Thin Shrink Small Outline Package)
HD74CDCV857
Function Table
Inputs
:
Outputs
:
PLL
AV CC
PWRDWN CLK
CLK
:
Y
Y
FBOUT
FBOUT
GND
H
L
H
:
L
H
L
H
:
Bypassed / off
*1
GND
H
H
L
:
H
L
H
L
:
Bypassed / off
*1
X
L
L
H
:
Z
Z
Z
Z
:
off
X
L
H
L
:
Z
Z
Z
Z
:
off
2.5 V
H
L
H
:
H
L
H
L
:
on
2.5 V
H
H
L
:
H
L
H
L
:
on
2.5 V
X
0 MHz 0 MHz
:
Z
Z
Z
Z
:
off
H:
L:
X:
Z:
Note:
2
High level
Low level
Don’t care
High impedance
1. Bypasse mode is used for Hitachi test mode.
HD74CDCV857
Pin Arrangement
48 GND
GND 1
Y0 2
47 Y5
Y0 3
46 Y5
V DDQ 4
45 V DDQ
Y1 5
44 Y6
Y1 6
43 Y6
GND 7
42 GND
GND 8
41 GND
Y2 9
40 Y7
Y2 10
39 Y7
V DDQ 11
38 V DDQ
V DDQ 12
37 PWRDWN
CLK 13
36 FBIN
CLK 14
35 FBIN
V DDQ 15
34 V DDQ
AV CC 16
33 FBOUT
AGND 17
32 FBOUT
31 GND
GND 18
Y3 19
30 Y8
Y3 20
29 Y8
V DDQ 21
28 V DDQ
Y4 22
27 Y9
Y4 23
26 Y9
GND 24
25 GND
(Top view)
3
HD74CDCV857
Pin Function
Pin name
No.
Type
Description
AGND
17
Ground
Analog ground. AGND provides the ground reference for the
analog circuitry.
AVCC
16
Power
Analog power supply. AVCC provides the power reference for
the analog circuitry. In addition, AV CC can be used to bypass
the PLL for test purposes. When AVCC is strapped to ground,
PLL is bypassed and CLK is buffered directly to the device
outputs. This bypass mode is used for Hitachi test.
CLK, CLK
13, 14
I
Clock input. CLK provides the clock signal to be distributed by
the HD74CDCV857 clock driver. CLK is used to provide the
reference signal to the integrated PLL that generates the clock
output signals. CLK must have a fixed frequency and fixed
phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization
time is required for the PLL to phase lock the feedback signal to
its reference signal.
Differential
input
FBIN, FBIN
35, 36
I
Differential
input
FBOUT, FBOUT 32, 33
O
Differential
output
Feedback input. FBIN provides the feedback signal to the
internal PLL. FBIN must be hard-wired to FBOUT to complete
the PLL. The integrated PLL synchronizes CLK and FBIN so
that there is nominally zero phase error between CLK and
FBIN.
Feedback output. FBOUT is dedicated for external feedback. It
switches at the same frequency as CLK. When externally wired
to FBIN, FBOUT completes the feedback loop of the PLL.
PWRDWN
37
I
Output bank enable. PWRDWN is the output enable for all
outputs. When PWRDWN is low, VCO will stop and all outputs
are disabled to a high impedance state. When PWRDWN will
be returned high, PLL will re-synchroniz to CLK frequency and
all outputs are enabled.
GND
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
Ground
Ground
VDDQ
4, 11, 12,
15, 21, 28,
34, 38, 45
Power
Power supply
Y
3, 5, 10, 20, O
22, 27, 29, Differential
39, 44, 46
output
Clock outputs. These outputs provide low-skew copies of CLK.
Y
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
Clock outputs. These outputs provide low-skew copies of CLK.
4
O
Differential
output
HD74CDCV857
Logic Diagram
PWRDWN
AVCC
CLK
CLK
3
2
37
16
Y0
Powerdown
and Test
Logic
13
14
PLL
FBIN
FBIN
Y0
36
35
5
6
Y1
10
9
Y2
20
19
Y3
22
23
Y4
46
47
Y5
44
43
Y6
39
40
Y7
29
30
Y8
27
26
Y9
32
33
FBOUT
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
FBOUT
Note: All inputs and outputs are associated with VDDQ = 2.5 V.
5
HD74CDCV857
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
VDDQ
–0.5 to 3.6
V
VI
–0.5 to VDDQ+0.5 V
VO
–0.5 to VDDQ
+0.5
V
Input clamp current
I IK
–50
mA
VI < 0
Output clamp current
I OK
–50
mA
VO < 0
Continuous output current
IO
±50
mA
VO = 0 to VDDQ
Supply current through each V DDQ or GND I VDDQ or IGND
±100
mA
Maximum power dissipation
at Ta = 55°C (in still air)
0.7
W
–65 to +150
°C
Input voltage
Output voltage
*1
Storage temperature
Notes:
6
Tstg
Conditions
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
HD74CDCV857
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit Conditions
Supply voltage
AVCC
2.3
2.5
2.7
V
VDDQ
2.3
2.5
2.7
V
–0.3
—
VDDQ+0.3
V
All pins
VIHG
1.7
—
VDDQ+0.3
V
PWRDWN input pin
VILG
–0.3
—
0.7
V
PWRDWN input pin
VID
0.36
—
VDDQ+0.6
V
VIX
VOX
0.5×VDDQ
–0.20
—
0.5×VDDQ
+0.20
V
I OH
—
—
–12
mA
I OL
—
—
12
Input slew rate
SR
1
—
4
V/ns 20% – 80%
Operating temperature
Ta
0
—
70
°C
Output supply voltage
DC input signal voltage
*1
High level input voltage
Low level input voltage
Differential input signal voltage
Differential cross point voltage
Output current
Notes:
*2
*3
Inputs pins must be prevent from floating.
Feedback inputs (FBIN, FBIN) may float when the device is in low power mode.
1. DC input signal voltage specifies the allowable dc execution of differential input.
2. Differential cross point voltage is expected to track variations of VDDQ and is the voltage at which
the differential signals must be crossing. (See figure1-1)
CLK
VID
CLK
Crossing point
Figure 1 Differential input levels
7
HD74CDCV857
Electrical Characteristics
Min
Typ *1
Max
Unit
Test Conditions
VIK
Input clamp CLK, CLK
voltage
FBIN, FBIN, G
—
—
–1.2
V
I I = –18 mA, VDDQ = 2.3 V
Output voltage
VCC–0.2 —
—
V
I OH = –100 µA, VCC = 2.3 to 2.7 V
1.7
—
—
I OH = –12 mA, VCC = 2.3 V
—
—
0.2
I OL = 100 µA, VCC = 2.3 to 2.7 V
—
—
0.6
I OL = 12 mA, VCC = 2.3 V
Item
Symbol
VOH
VOL
Input current
II
—
—
±10
µA
VI = 0 V to 2.7 V, VDDQ = 2.7 V
Input capacitance
CI
2.5
—
3.5
pF
CLK and CLK, FBIN and FBIN
Delta input capacitance
CDI
–0.25
—
0.25
pF
CLK and CLK, FBIN and FBIN
Supply current
DICC
—
250
TBD
mA
AI CC
—
9
TBD
I CCpd
—
—
100
Supply current in power
down mode
Note:
8
µA
1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions.
HD74CDCV857
Switching Characteristics
Item
Symbol
Min
Typ
Max
Unit Test Conditions
Notes
Period jitter
t PER
–75
—
75
ps
See figure 6, 9
7, 8
Half period jitter
t HPER
–100
—
100
ps
See figure 7, 9
8
Cycle to cycle jitter
t CC
–75
—
75
ps
See figure 5, 9
Static phase error
t SPE
–50
—
50
ps
See figure 3, 9
Output clock skew
t sk
—
—
100
ps
See figure 4, 9
Operating clock frequency f CLK(O)
60
—
200
MHz See figure 9
1, 2
Application clock
frequency
f CLK(A)
95
133
170
MHz See figure 9
1, 3
Slew rate
t SL
1.0
—
2.0
V/ns See figure 9
20% – 80%
PLL stabilization time
t STAB
—
—
0.1
ms
6
See figure 9
4, 5
Notes: 1. The PLL must be able to handle spread spectrum induced skew (the specification for this
frequency modulation can be found in the latest Intel PC100 Registered DIMM specification)
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in
which it is not required to meet the other timing parameters.
3. Application clock frequency indicates a range over which the PLL must meet all timing
parameters.
4 Assumes equal wire length and loading on the clock output and feedback path.
5. Static phase error does not include jitter.
6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its
feedback signal to its reference signal after power up.
7. Period jitter defines the largest variation in clock period, around anominal clock period.
8. Period jitter and half period jitter are independent from each other.
9
HD74CDCV857
Differential clock outputs are directly terminated by a 120 Ω resistor. Figure 2 is typical usage conditions
of outputs load.
V DDQ
V DDQ
Device
under OUT
test
RT =
120 Ω
C = 14 pF
OUT
C = 14 pF
Figure 2 Differential signal using direct termination resistor
CLKIN
CLKIN
FBIN
FBIN
tSPE
Figure 3 Static phase error
10
HD74CDCV857
FBOUT
FBOUT
Yx
Yx
tsk
Yx
Yx
Yx'
Yx'
tsk
Figure 4 Output skew
11
HD74CDCV857
Yx, FBOUT
Yx, FBOUT
t cycle n
t cycle n+1
t cc = t cycle n – t cycle n+1
Figure 5 Cycle to cycle jitter
Yx, FBOUT
Yx, FBOUT
t cycle n
Yx, FBOUT
Yx, FBOUT
1
fo
t PER = t cycle n –
1
fo
Figure 6 Period jitter
Yx, FBOUT
Yx, FBOUT
t half period n
t half period n+1
Yx, FBOUT
Yx, FBOUT
1
fo
t HPER = t half period n –
1
2*fo
Figure 7 Half period jitter
12
HD74CDCV857
Yx, FBOUT
Yx, FBOUT
t half cycle n
t half cycle n+1
t HCC = t half cycle n – t half cycle n+1
Figure 8 Half cycle to cycle jitter
V DDQ
V DDQ /2
AVCC
AVCC /2
Device
under OUT
test
OUT
AGND
GND
RT =
10 Ω
Z = 60 Ω
C=
14 pF
–V DDQ /2
Z = 60 Ω
–V DDQ /2
V DDQ
V DDQ
AVCC
AV CC
Device
under OUT
test
Oscillo
scope
RT =
10 Ω
C=
14 pF
–V DDQ /2
RT =
50 Ω
Z = 50 Ω
RT =
50 Ω
Z = 60 Ω
RT =
120 Ω
OUT
Z = 50 Ω
Z = 60 Ω
AGND
GND
C=
14 pF
C=
14 pF
Figure 9 Output load test circuit
13
HD74CDCV857
Package Dimensions
Unit : mm
+0.3
12.50 –0.1
25
6.10 +0.3
–0.1
48
0.20 +0.1
–0.05
0.50
24
0.15 ± 0.05
1
0.08 M
14
0.05 Min
0.10
1.20 max
0.65 Max
8.10 ± 0.3
10° Max
0.50 ± 0.1
Hitachi code
EIAJ code
JEDEC code
TTP-48DC
—
—
HD74CDCV857
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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For further information write to:
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Copyright ' Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
15